adding part 2 and 3

824 files changed, 41968 insertions, 0 deletions

diff --git a/part_2/ex5/c5_pin_model_dump.txt b/part_2/ex5/c5_pin_model_dump.txt
new file mode 100755
index 0000000..d8a635e
--- /dev/null
+++ b/part_2/ex5/c5_pin_model_dump.txt
@@ -0,0 +1,120 @@
+io_4iomodule_c5_index: 77gpio_index: 2

+io_4iomodule_c5_index: 60gpio_index: 476

+io_4iomodule_c5_index: 62gpio_index: 6

+io_4iomodule_c5_index: 26gpio_index: 472

+io_4iomodule_c5_index: 20gpio_index: 10

+io_4iomodule_c5_index: 12gpio_index: 468

+io_4iomodule_c5_index: 27gpio_index: 14

+io_4iomodule_c5_index: 71gpio_index: 464

+io_4iomodule_c5_index: 56gpio_index: 19

+io_4iomodule_c5_index: 14gpio_index: 460

+io_4iomodule_c5_index: 22gpio_index: 22

+io_4iomodule_c5_index: 10gpio_index: 456

+io_4iomodule_c5_index: 11gpio_index: 27

+io_4iomodule_c5_index: 73gpio_index: 452

+io_4iomodule_c5_index: 74gpio_index: 30

+io_4iomodule_c5_index: 76gpio_index: 448

+io_4iomodule_c5_index: 2gpio_index: 35

+io_4iomodule_c5_index: 78gpio_index: 444

+io_4iomodule_c5_index: 9gpio_index: 38

+io_4iomodule_c5_index: 36gpio_index: 440

+io_4iomodule_c5_index: 51gpio_index: 43

+io_4iomodule_c5_index: 23gpio_index: 436

+io_4iomodule_c5_index: 53gpio_index: 46

+io_4iomodule_c5_index: 50gpio_index: 432

+io_4iomodule_c5_index: 0gpio_index: 51

+io_4iomodule_c5_index: 43gpio_index: 428

+io_4iomodule_c5_index: 67gpio_index: 54

+io_4iomodule_c5_index: 16gpio_index: 424

+io_4iomodule_c5_index: 44gpio_index: 59

+io_4iomodule_c5_index: 29gpio_index: 420

+io_4iomodule_c5_index: 1gpio_index: 62

+io_4iomodule_c5_index: 8gpio_index: 416

+io_4iomodule_c5_index: 65gpio_index: 67

+io_4iomodule_c5_index: 25gpio_index: 412

+io_4iomodule_c5_index: 40gpio_index: 70

+io_4iomodule_c5_index: 55gpio_index: 408

+io_4iomodule_c5_index: 66gpio_index: 75

+io_4iomodule_c5_index: 5gpio_index: 404

+io_4iomodule_c5_index: 61gpio_index: 78

+io_4iomodule_c5_index: 17gpio_index: 400

+io_4iomodule_c5_index: 42gpio_index: 83

+io_4iomodule_c5_index: 59gpio_index: 396

+io_4iomodule_c5_index: 54gpio_index: 86

+io_4iomodule_c5_index: 58gpio_index: 392

+io_4iomodule_c5_index: 33gpio_index: 91

+io_4iomodule_c5_index: 41gpio_index: 388

+io_4iomodule_c5_index: 69gpio_index: 94

+io_4iomodule_c5_index: 3gpio_index: 384

+io_4iomodule_c5_index: 18gpio_index: 99

+io_4iomodule_c5_index: 15gpio_index: 380

+io_4iomodule_c5_index: 6gpio_index: 102

+io_4iomodule_c5_index: 7gpio_index: 376

+io_4iomodule_c5_index: 47gpio_index: 107

+io_4iomodule_c5_index: 39gpio_index: 372

+io_4iomodule_c5_index: 32gpio_index: 110

+io_4iomodule_c5_index: 24gpio_index: 368

+io_4iomodule_c5_index: 48gpio_index: 115

+io_4iomodule_c5_index: 57gpio_index: 364

+io_4iomodule_c5_index: 64gpio_index: 118

+io_4iomodule_c5_index: 31gpio_index: 360

+io_4iomodule_c5_index: 46gpio_index: 123

+io_4iomodule_c5_index: 21gpio_index: 356

+io_4iomodule_c5_index: 72gpio_index: 126

+io_4iomodule_c5_index: 70gpio_index: 352

+io_4iomodule_c5_index: 49gpio_index: 131

+io_4iomodule_c5_index: 63gpio_index: 348

+io_4iomodule_c5_index: 79gpio_index: 134

+io_4iomodule_c5_index: 28gpio_index: 344

+io_4iomodule_c5_index: 34gpio_index: 139

+io_4iomodule_c5_index: 4gpio_index: 340

+io_4iomodule_c5_index: 68gpio_index: 142

+io_4iomodule_c5_index: 37gpio_index: 336

+io_4iomodule_c5_index: 45gpio_index: 147

+io_4iomodule_c5_index: 35gpio_index: 332

+io_4iomodule_c5_index: 38gpio_index: 150

+io_4iomodule_c5_index: 19gpio_index: 328

+io_4iomodule_c5_index: 52gpio_index: 155

+io_4iomodule_c5_index: 30gpio_index: 324

+io_4iomodule_c5_index: 75gpio_index: 158

+io_4iomodule_c5_index: 13gpio_index: 320

+io_4iomodule_h_c5_index: 0gpio_index: 161

+io_4iomodule_h_c5_index: 15gpio_index: 165

+io_4iomodule_h_c5_index: 27gpio_index: 169

+io_4iomodule_h_c5_index: 30gpio_index: 173

+io_4iomodule_h_c5_index: 36gpio_index: 176

+io_4iomodule_h_c5_index: 37gpio_index: 180

+io_4iomodule_h_c5_index: 26gpio_index: 184

+io_4iomodule_h_c5_index: 24gpio_index: 188

+io_4iomodule_h_c5_index: 1gpio_index: 192

+io_4iomodule_h_c5_index: 21gpio_index: 196

+io_4iomodule_h_c5_index: 18gpio_index: 200

+io_4iomodule_h_c5_index: 6gpio_index: 204

+io_4iomodule_h_c5_index: 31gpio_index: 208

+io_4iomodule_h_c5_index: 3gpio_index: 212

+io_4iomodule_h_c5_index: 20gpio_index: 216

+io_4iomodule_h_c5_index: 4gpio_index: 220

+io_4iomodule_h_c5_index: 29gpio_index: 224

+io_4iomodule_h_c5_index: 22gpio_index: 228

+io_4iomodule_h_c5_index: 16gpio_index: 232

+io_4iomodule_h_c5_index: 9gpio_index: 236

+io_4iomodule_h_c5_index: 25gpio_index: 240

+io_4iomodule_h_c5_index: 11gpio_index: 244

+io_4iomodule_h_c5_index: 19gpio_index: 248

+io_4iomodule_h_c5_index: 23gpio_index: 252

+io_4iomodule_h_c5_index: 17gpio_index: 256

+io_4iomodule_h_c5_index: 8gpio_index: 260

+io_4iomodule_h_c5_index: 38gpio_index: 264

+io_4iomodule_h_c5_index: 2gpio_index: 268

+io_4iomodule_h_c5_index: 12gpio_index: 272

+io_4iomodule_h_c5_index: 35gpio_index: 276

+io_4iomodule_h_c5_index: 13gpio_index: 280

+io_4iomodule_h_c5_index: 5gpio_index: 284

+io_4iomodule_h_c5_index: 28gpio_index: 288

+io_4iomodule_h_c5_index: 7gpio_index: 292

+io_4iomodule_h_c5_index: 34gpio_index: 296

+io_4iomodule_h_c5_index: 14gpio_index: 300

+io_4iomodule_h_c5_index: 33gpio_index: 304

+io_4iomodule_h_c5_index: 39gpio_index: 308

+io_4iomodule_h_c5_index: 32gpio_index: 312

+io_4iomodule_h_c5_index: 10gpio_index: 316

diff --git a/part_2/ex5/db/.cmp.kpt b/part_2/ex5/db/.cmp.kpt
new file mode 100755
index 0000000..1dafbef
--- /dev/null
+++ b/part_2/ex5/db/.cmp.kpt
diff --git a/part_2/ex5/db/ex5.(0).cnf.cdb b/part_2/ex5/db/ex5.(0).cnf.cdb
new file mode 100755
index 0000000..5df78fc
--- /dev/null
+++ b/part_2/ex5/db/ex5.(0).cnf.cdb
diff --git a/part_2/ex5/db/ex5.(0).cnf.hdb b/part_2/ex5/db/ex5.(0).cnf.hdb
new file mode 100755
index 0000000..169e96a
--- /dev/null
+++ b/part_2/ex5/db/ex5.(0).cnf.hdb
diff --git a/part_2/ex5/db/ex5.analyze_file.qmsg b/part_2/ex5/db/ex5.analyze_file.qmsg
new file mode 100755
index 0000000..d39cdf7
--- /dev/null
+++ b/part_2/ex5/db/ex5.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806631495 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:23:51 2016 " "Processing started: Tue Nov 22 09:23:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "652 " "Peak virtual memory: 652 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:24:08 2016 " "Processing ended: Tue Nov 22 09:24:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}

diff --git a/part_2/ex5/db/ex5.asm.qmsg b/part_2/ex5/db/ex5.asm.qmsg
new file mode 100755
index 0000000..822de0a
--- /dev/null
+++ b/part_2/ex5/db/ex5.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806915392 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806915398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:28:35 2016 " "Processing started: Tue Nov 22 09:28:35 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806915398 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479806915398 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479806915398 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479806916542 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479806936975 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "708 " "Peak virtual memory: 708 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:28:58 2016 " "Processing ended: Tue Nov 22 09:28:58 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479806938289 ""}

diff --git a/part_2/ex5/db/ex5.asm.rdb b/part_2/ex5/db/ex5.asm.rdb
new file mode 100755
index 0000000..cb19986
--- /dev/null
+++ b/part_2/ex5/db/ex5.asm.rdb
diff --git a/part_2/ex5/db/ex5.cbx.xml b/part_2/ex5/db/ex5.cbx.xml
new file mode 100755
index 0000000..2959ffa
--- /dev/null
+++ b/part_2/ex5/db/ex5.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex5">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex5/db/ex5.cmp.bpm b/part_2/ex5/db/ex5.cmp.bpm
new file mode 100755
index 0000000..7a0383d
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.bpm
diff --git a/part_2/ex5/db/ex5.cmp.cdb b/part_2/ex5/db/ex5.cmp.cdb
new file mode 100755
index 0000000..bf4e81f
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.cdb
diff --git a/part_2/ex5/db/ex5.cmp.hdb b/part_2/ex5/db/ex5.cmp.hdb
new file mode 100755
index 0000000..64b27e8
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.hdb
diff --git a/part_2/ex5/db/ex5.cmp.idb b/part_2/ex5/db/ex5.cmp.idb
new file mode 100755
index 0000000..39203dc
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.idb
diff --git a/part_2/ex5/db/ex5.cmp.logdb b/part_2/ex5/db/ex5.cmp.logdb
new file mode 100755
index 0000000..0866a7b
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.logdb
@@ -0,0 +1,50 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;10;0;0;10;10;0;8;0;0;0;0;8;0;0;0;0;8;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,10;10;10;10;10;0;10;10;0;0;10;2;10;10;10;10;2;10;10;10;10;2;10;10;10;10;10;10,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,count[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,clock,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,enable,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex5/db/ex5.cmp.rdb b/part_2/ex5/db/ex5.cmp.rdb
new file mode 100755
index 0000000..a1fc9aa
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.rdb
diff --git a/part_2/ex5/db/ex5.cmp_merge.kpt b/part_2/ex5/db/ex5.cmp_merge.kpt
new file mode 100755
index 0000000..46430f8
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp_merge.kpt
diff --git a/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..71fed4b
--- /dev/null
+++ b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd
new file mode 100755
index 0000000..c53e8d2
--- /dev/null
+++ b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd
diff --git a/part_2/ex5/db/ex5.db_info b/part_2/ex5/db/ex5.db_info
new file mode 100755
index 0000000..83604aa
--- /dev/null
+++ b/part_2/ex5/db/ex5.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Version_Index = 419480576

+Creation_Time = Tue Nov 22 09:10:44 2016

diff --git a/part_2/ex5/db/ex5.fit.qmsg b/part_2/ex5/db/ex5.fit.qmsg
new file mode 100755
index 0000000..a42b5fb
--- /dev/null
+++ b/part_2/ex5/db/ex5.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479806830418 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479806830418 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex5 5CGXFC7C7F23C8 " "Selected device 5CGXFC7C7F23C8 for design \"ex5\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479806830529 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1479806830770 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1479806830770 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479806832299 ""}

+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1479806833191 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479806834602 ""}

+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "10 10 " "No exact pin location assignment(s) for 10 pins of 10 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1479806835217 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479806850286 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clock~inputCLKENA0 8 global CLKCTRL_G10 " "clock~inputCLKENA0 with 8 fanout uses global clock CLKCTRL_G10" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479806850601 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479806850601 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806850602 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479806850862 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479806850870 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479806850871 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479806850872 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479806850880 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479806850881 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex5.sdc " "Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479806854662 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479806854669 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479806854672 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479806854672 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479806854673 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479806854690 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479806854690 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479806854690 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:21 " "Fitter preparation operations ending: elapsed time is 00:00:21" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806855238 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479806869358 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479806870144 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:05 " "Fitter placement preparation operations ending: elapsed time is 00:00:05" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806874879 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479806877557 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479806881279 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806881280 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479806883680 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y35 X89_Y45 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45" {  } { { "loc" "" { Generic "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45"} { { 12 { 0 ""} 78 35 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479806897785 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479806897785 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479806898158 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479806898158 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806898163 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.42 " "Total time spent on timing analysis during the Fitter is 0.42 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479806902813 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479806902906 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479806903630 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479806903630 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479806905010 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:07 " "Fitter post-fit operations ending: elapsed time is 00:00:07" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806909506 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg " "Generated suppressed messages file C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479806910231 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2264 " "Peak virtual memory: 2264 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:28:31 2016 " "Processing ended: Tue Nov 22 09:28:31 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:28 " "Elapsed time: 00:01:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:40 " "Total CPU time (on all processors): 00:01:40" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479806911666 ""}

diff --git a/part_2/ex5/db/ex5.hier_info b/part_2/ex5/db/ex5.hier_info
new file mode 100755
index 0000000..8d49b87
--- /dev/null
+++ b/part_2/ex5/db/ex5.hier_info
@@ -0,0 +1,27 @@
+|ex5

+clock => count[0]~reg0.CLK

+clock => count[1]~reg0.CLK

+clock => count[2]~reg0.CLK

+clock => count[3]~reg0.CLK

+clock => count[4]~reg0.CLK

+clock => count[5]~reg0.CLK

+clock => count[6]~reg0.CLK

+clock => count[7]~reg0.CLK

+enable => count[0]~reg0.ENA

+enable => count[1]~reg0.ENA

+enable => count[2]~reg0.ENA

+enable => count[3]~reg0.ENA

+enable => count[4]~reg0.ENA

+enable => count[5]~reg0.ENA

+enable => count[6]~reg0.ENA

+enable => count[7]~reg0.ENA

+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

diff --git a/part_2/ex5/db/ex5.hif b/part_2/ex5/db/ex5.hif
new file mode 100755
index 0000000..a9b1b07
--- /dev/null
+++ b/part_2/ex5/db/ex5.hif
diff --git a/part_2/ex5/db/ex5.lpc.html b/part_2/ex5/db/ex5.lpc.html
new file mode 100755
index 0000000..7d68592
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+</TABLE>

diff --git a/part_2/ex5/db/ex5.lpc.rdb b/part_2/ex5/db/ex5.lpc.rdb
new file mode 100755
index 0000000..c179f4d
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.rdb
diff --git a/part_2/ex5/db/ex5.lpc.txt b/part_2/ex5/db/ex5.lpc.txt
new file mode 100755
index 0000000..dbfe520
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex5/db/ex5.map.ammdb b/part_2/ex5/db/ex5.map.ammdb
new file mode 100755
index 0000000..a4afc79
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.ammdb
diff --git a/part_2/ex5/db/ex5.map.bpm b/part_2/ex5/db/ex5.map.bpm
new file mode 100755
index 0000000..3592b20
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.bpm
diff --git a/part_2/ex5/db/ex5.map.cdb b/part_2/ex5/db/ex5.map.cdb
new file mode 100755
index 0000000..256c526
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.cdb
diff --git a/part_2/ex5/db/ex5.map.hdb b/part_2/ex5/db/ex5.map.hdb
new file mode 100755
index 0000000..3d0d6f2
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.hdb
diff --git a/part_2/ex5/db/ex5.map.kpt b/part_2/ex5/db/ex5.map.kpt
new file mode 100755
index 0000000..6a235ab
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.kpt
diff --git a/part_2/ex5/db/ex5.map.logdb b/part_2/ex5/db/ex5.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/db/ex5.map.qmsg b/part_2/ex5/db/ex5.map.qmsg
new file mode 100755
index 0000000..342e059
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806798609 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806798617 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:26:38 2016 " "Processing started: Tue Nov 22 09:26:38 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806798617 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806798617 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806798617 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479806799115 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479806799115 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog files/counter_8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog files/counter_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_8 " "Found entity 1: counter_8" {  } { { "verilog files/counter_8.v" "" { Text "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/counter_8.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479806815578 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806815578 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog files/ex5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog files/ex5.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex5 " "Found entity 1: ex5" {  } { { "verilog files/ex5.v" "" { Text "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479806815580 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806815580 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex5 " "Elaborating entity \"ex5\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479806815642 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479806818460 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479806820436 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479806820436 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479806821948 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479806821948 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479806821948 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479806821948 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "698 " "Peak virtual memory: 698 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:27:02 2016 " "Processing ended: Tue Nov 22 09:27:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Elapsed time: 00:00:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806822084 ""}

diff --git a/part_2/ex5/db/ex5.map.rdb b/part_2/ex5/db/ex5.map.rdb
new file mode 100755
index 0000000..d90a0c1
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.rdb
diff --git a/part_2/ex5/db/ex5.map_bb.cdb b/part_2/ex5/db/ex5.map_bb.cdb
new file mode 100755
index 0000000..ebced3a
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.cdb
diff --git a/part_2/ex5/db/ex5.map_bb.hdb b/part_2/ex5/db/ex5.map_bb.hdb
new file mode 100755
index 0000000..bb6499e
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.hdb
diff --git a/part_2/ex5/db/ex5.map_bb.logdb b/part_2/ex5/db/ex5.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/db/ex5.pre_map.hdb b/part_2/ex5/db/ex5.pre_map.hdb
new file mode 100755
index 0000000..fecb803
--- /dev/null
+++ b/part_2/ex5/db/ex5.pre_map.hdb
diff --git a/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb b/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..5cd114f
--- /dev/null
+++ b/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb
diff --git a/part_2/ex5/db/ex5.routing.rdb b/part_2/ex5/db/ex5.routing.rdb
new file mode 100755
index 0000000..34ca13b
--- /dev/null
+++ b/part_2/ex5/db/ex5.routing.rdb
diff --git a/part_2/ex5/db/ex5.rtlv.hdb b/part_2/ex5/db/ex5.rtlv.hdb
new file mode 100755
index 0000000..a8a9b60
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv.hdb
diff --git a/part_2/ex5/db/ex5.rtlv_sg.cdb b/part_2/ex5/db/ex5.rtlv_sg.cdb
new file mode 100755
index 0000000..6214e3f
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv_sg.cdb
diff --git a/part_2/ex5/db/ex5.rtlv_sg_swap.cdb b/part_2/ex5/db/ex5.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..0be030c
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv_sg_swap.cdb
diff --git a/part_2/ex5/db/ex5.sld_design_entry.sci b/part_2/ex5/db/ex5.sld_design_entry.sci
new file mode 100755
index 0000000..1bd84ed
--- /dev/null
+++ b/part_2/ex5/db/ex5.sld_design_entry.sci
diff --git a/part_2/ex5/db/ex5.sld_design_entry_dsc.sci b/part_2/ex5/db/ex5.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..1bd84ed
--- /dev/null
+++ b/part_2/ex5/db/ex5.sld_design_entry_dsc.sci
diff --git a/part_2/ex5/db/ex5.smart_action.txt b/part_2/ex5/db/ex5.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex5/db/ex5.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex5/db/ex5.sta.qmsg b/part_2/ex5/db/ex5.sta.qmsg
new file mode 100755
index 0000000..b8bb557
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta.qmsg
@@ -0,0 +1,21 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806941525 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806941531 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:29:00 2016 " "Processing started: Tue Nov 22 09:29:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806941531 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806941531 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex5 -c ex5 " "Command: quartus_sta ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806941531 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806941769 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942710 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942710 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942796 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942796 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex5.sdc " "Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944125 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944125 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clock clock " "create_clock -period 1.000 -name clock clock" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1479806944126 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944126 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944128 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944128 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806944143 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806944169 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479806944219 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944219 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.444 " "Worst-case setup slack is -1.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.444              -8.970 clock  " "   -1.444              -8.970 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944241 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.487 " "Worst-case hold slack is 0.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.487               0.000 clock  " "    0.487               0.000 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944250 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944259 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944268 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.724 " "Worst-case minimum pulse width slack is -0.724" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724              -8.917 clock  " "   -0.724              -8.917 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""}  } {
\ No newline at end of file
diff --git a/part_2/ex5/db/ex5.sta.rdb b/part_2/ex5/db/ex5.sta.rdb
new file mode 100755
index 0000000..2a68d94
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta.rdb
diff --git a/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb b/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..29b23ee
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb
diff --git a/part_2/ex5/db/ex5.tis_db_list.ddb b/part_2/ex5/db/ex5.tis_db_list.ddb
new file mode 100755
index 0000000..dec6bed
--- /dev/null
+++ b/part_2/ex5/db/ex5.tis_db_list.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb b/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..06cd923
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb b/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb
new file mode 100755
index 0000000..0c58cfe
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb b/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..6bedbe6
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex5/db/ex5.tmw_info b/part_2/ex5/db/ex5.tmw_info
new file mode 100755
index 0000000..fcbb322
--- /dev/null
+++ b/part_2/ex5/db/ex5.tmw_info
@@ -0,0 +1,4 @@
+start_analysis_synthesis:s:00:00:24-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:01:30-start_full_compilation

+start_assembler:s:00:00:27-start_full_compilation

diff --git a/part_2/ex5/db/ex5.vpr.ammdb b/part_2/ex5/db/ex5.vpr.ammdb
new file mode 100755
index 0000000..8dd3884
--- /dev/null
+++ b/part_2/ex5/db/ex5.vpr.ammdb
diff --git a/part_2/ex5/db/ex5_partition_pins.json b/part_2/ex5/db/ex5_partition_pins.json
new file mode 100755
index 0000000..1c05513
--- /dev/null
+++ b/part_2/ex5/db/ex5_partition_pins.json
@@ -0,0 +1,49 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "count[0]",

+					"strict" : false

+				},

+				{

+					"name" : "count[1]",

+					"strict" : false

+				},

+				{

+					"name" : "count[2]",

+					"strict" : false

+				},

+				{

+					"name" : "count[3]",

+					"strict" : false

+				},

+				{

+					"name" : "count[4]",

+					"strict" : false

+				},

+				{

+					"name" : "count[5]",

+					"strict" : false

+				},

+				{

+					"name" : "count[6]",

+					"strict" : false

+				},

+				{

+					"name" : "count[7]",

+					"strict" : false

+				},

+				{

+					"name" : "clock",

+					"strict" : false

+				},

+				{

+					"name" : "enable",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex5/db/prev_cmp_ex5.qmsg b/part_2/ex5/db/prev_cmp_ex5.qmsg
new file mode 100755
index 0000000..d39cdf7
--- /dev/null
+++ b/part_2/ex5/db/prev_cmp_ex5.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806631495 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:23:51 2016 " "Processing started: Tue Nov 22 09:23:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "652 " "Peak virtual memory: 652 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:24:08 2016 " "Processing ended: Tue Nov 22 09:24:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}

diff --git a/part_2/ex5/ex5.qpf b/part_2/ex5/ex5.qpf
new file mode 100755
index 0000000..ffc3e43
--- /dev/null
+++ b/part_2/ex5/ex5.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 2016  Intel Corporation. All rights reserved.

+# Your use of Intel Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Intel Program License 

+# Subscription Agreement, the Intel Quartus Prime License Agreement,

+# the Intel MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Intel and sold by Intel or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+# Date created = 09:10:34  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "16.1"

+DATE = "09:10:34  November 22, 2016"

+

+# Revisions

+

+PROJECT_REVISION = "ex5"

diff --git a/part_2/ex5/ex5.qsf b/part_2/ex5/ex5.qsf
new file mode 100755
index 0000000..c70ecfe
--- /dev/null
+++ b/part_2/ex5/ex5.qsf
@@ -0,0 +1,53 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 2016  Intel Corporation. All rights reserved.

+# Your use of Intel Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Intel Program License 

+# Subscription Agreement, the Intel Quartus Prime License Agreement,

+# the Intel MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Intel and sold by Intel or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+# Date created = 09:10:35  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex5_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CGXFC7C7F23C8

+set_global_assignment -name TOP_LEVEL_ENTITY ex5

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:10:35  NOVEMBER 22, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE "verilog files/counter_8.v"

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_global_assignment -name VERILOG_FILE "verilog files/ex5.v"

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex5/ex5.qws b/part_2/ex5/ex5.qws
new file mode 100755
index 0000000..b27ab95
--- /dev/null
+++ b/part_2/ex5/ex5.qws
diff --git a/part_2/ex5/ex5_nativelink_simulation.rpt b/part_2/ex5/ex5_nativelink_simulation.rpt
new file mode 100755
index 0000000..833b429
--- /dev/null
+++ b/part_2/ex5/ex5_nativelink_simulation.rpt
@@ -0,0 +1,21 @@
+Info: Start Nativelink Simulation process

+Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

+

+========= EDA Simulation Settings =====================

+

+Sim Mode              :  RTL

+Family                :  cyclonev

+Quartus root          :  c:/altera/16.0/quartus/bin64/

+Quartus sim root      :  c:/altera/16.0/quartus/eda/sim_lib

+Simulation Tool       :  modelsim-altera

+Simulation Language   :  verilog

+Simulation Mode       :  GUI

+Sim Output File       :  

+Sim SDF file          :  

+Sim dir               :  simulation\modelsim

+

+=======================================================

+

+Info: Starting NativeLink simulation with ModelSim-Altera software

+Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl

+Info: Spawning ModelSim-Altera Simulation software 

diff --git a/part_2/ex5/incremental_db/README b/part_2/ex5/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_2/ex5/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.

+

+The compiled_partitions sub-folder contains previous compilation results for each partition.

+As long as this folder is preserved, incremental compilation results from earlier compiles

+can be re-used.  To perform a clean compilation from source files for all partitions, both

+the db and incremental_db folder should be removed.

+

+The imported_partitions sub-folder contains the last imported QXP for each imported partition.

+As long as this folder is preserved, imported partitions will be automatically re-imported

+when the db or incremental_db/compiled_partitions folders are removed.

+

diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.db_info b/part_2/ex5/incremental_db/compiled_partitions/ex5.db_info
new file mode 100755
index 0000000..d20478d
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Version_Index = 419480576

+Creation_Time = Tue Nov 22 09:26:56 2016

diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.ammdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.ammdb
new file mode 100755
index 0000000..b275595
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.ammdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.cdb
new file mode 100755
index 0000000..3d7e429
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.dfp b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.dfp
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..1e1fcec
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..3645c01
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.sig b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hdb
new file mode 100755
index 0000000..89aab09
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.logdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.rcfdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..521454b
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.rcfdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.cdb
new file mode 100755
index 0000000..80c6973
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.dpi b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.dpi
new file mode 100755
index 0000000..6955961
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.dpi
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..46fb310
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hb_info b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..a4a4882
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.sig b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hdb
new file mode 100755
index 0000000..7dfc1cd
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.kpt b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.kpt
new file mode 100755
index 0000000..40bb8bb
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.kpt
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olf.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olf.cdb
new file mode 100755
index 0000000..a6a7b4a
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olf.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olm.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olm.cdb
new file mode 100755
index 0000000..c6265be
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olm.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.oln.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.oln.cdb
new file mode 100755
index 0000000..a4c2895
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.oln.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.opi b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.opi
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orf.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orf.cdb
new file mode 100755
index 0000000..a6a7b4a
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orf.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orm.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orm.cdb
new file mode 100755
index 0000000..cd4104f
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orm.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orn.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orn.cdb
new file mode 100755
index 0000000..0494107
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orn.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.rrp.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrp.hdb
new file mode 100755
index 0000000..45ff64f
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrp.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.rrs.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrs.cdb
new file mode 100755
index 0000000..27a2c00
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrs.cdb
diff --git a/part_2/ex5/output_files/ex5.asm.rpt b/part_2/ex5/output_files/ex5.asm.rpt
new file mode 100755
index 0000000..c6bb855
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex5

+Tue Nov 22 09:28:58 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Assembler Summary

+  3. Assembler Settings

+  4. Assembler Generated Files

+  5. Assembler Device Options: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.sof

+  6. Assembler Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------+

+; Assembler Summary                                             ;

++-----------------------+---------------------------------------+

+; Assembler Status      ; Successful - Tue Nov 22 09:28:58 2016 ;

+; Revision Name         ; ex5                                   ;

+; Top-level Entity Name ; ex5                                   ;

+; Family                ; Cyclone V                             ;

+; Device                ; 5CGXFC7C7F23C8                        ;

++-----------------------+---------------------------------------+

+

+

++----------------------------------+

+; Assembler Settings               ;

++--------+---------+---------------+

+; Option ; Setting ; Default Value ;

++--------+---------+---------------+

+

+

++------------------------------------------------------------------------------------------------------+

+; Assembler Generated Files                                                                            ;

++------------------------------------------------------------------------------------------------------+

+; File Name                                                                                            ;

++------------------------------------------------------------------------------------------------------+

+; C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.sof ;

++------------------------------------------------------------------------------------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------+

+; Assembler Device Options: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.sof ;

++----------------+---------------------------------------------------------------------------------------------------------------+

+; Option         ; Setting                                                                                                       ;

++----------------+---------------------------------------------------------------------------------------------------------------+

+; Device         ; 5CGXFC7C7F23C8                                                                                                ;

+; JTAG usercode  ; 0x00EC478F                                                                                                    ;

+; Checksum       ; 0x00EC478F                                                                                                    ;

++----------------+---------------------------------------------------------------------------------------------------------------+

+

+

++--------------------+

+; Assembler Messages ;

++--------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Assembler

+    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+    Info: Processing started: Tue Nov 22 09:28:35 2016

+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (115030): Assembler is generating device programming files

+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 708 megabytes

+    Info: Processing ended: Tue Nov 22 09:28:58 2016

+    Info: Elapsed time: 00:00:23

+    Info: Total CPU time (on all processors): 00:00:15

+

+

diff --git a/part_2/ex5/output_files/ex5.done b/part_2/ex5/output_files/ex5.done
new file mode 100755
index 0000000..da27f96
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.done
@@ -0,0 +1 @@
+Tue Nov 22 09:24:09 2016

diff --git a/part_2/ex5/output_files/ex5.fit.rpt b/part_2/ex5/output_files/ex5.fit.rpt
new file mode 100755
index 0000000..63955aa
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.fit.rpt
@@ -0,0 +1,1228 @@
+Fitter report for ex5

+Tue Nov 22 09:28:30 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Fitter Summary

+  3. Fitter Settings

+  4. Parallel Compilation

+  5. Fitter Netlist Optimizations

+  6. Incremental Compilation Preservation Summary

+  7. Incremental Compilation Partition Settings

+  8. Incremental Compilation Placement Preservation

+  9. Pin-Out File

+ 10. Fitter Resource Usage Summary

+ 11. Fitter Partition Statistics

+ 12. Input Pins

+ 13. Output Pins

+ 14. I/O Bank Usage

+ 15. All Package Pins

+ 16. I/O Assignment Warnings

+ 17. Fitter Resource Utilization by Entity

+ 18. Delay Chain Summary

+ 19. Pad To Core Delay Chain Fanout

+ 20. Control Signals

+ 21. Global & Other Fast Signals

+ 22. Routing Usage Summary

+ 23. I/O Rules Summary

+ 24. I/O Rules Details

+ 25. I/O Rules Matrix

+ 26. Fitter Device Options

+ 27. Operating Settings and Conditions

+ 28. Estimated Delay Added for Hold Timing Summary

+ 29. Estimated Delay Added for Hold Timing Details

+ 30. Fitter Messages

+ 31. Fitter Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-------------------------------------------------------------------------------+

+; Fitter Summary                                                                ;

++---------------------------------+---------------------------------------------+

+; Fitter Status                   ; Successful - Tue Nov 22 09:28:30 2016       ;

+; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;

+; Revision Name                   ; ex5                                         ;

+; Top-level Entity Name           ; ex5                                         ;

+; Family                          ; Cyclone V                                   ;

+; Device                          ; 5CGXFC7C7F23C8                              ;

+; Timing Models                   ; Final                                       ;

+; Logic utilization (in ALMs)     ; 5 / 56,480 ( < 1 % )                        ;

+; Total registers                 ; 8                                           ;

+; Total pins                      ; 10 / 268 ( 4 % )                            ;

+; Total virtual pins              ; 0                                           ;

+; Total block memory bits         ; 0 / 7,024,640 ( 0 % )                       ;

+; Total RAM Blocks                ; 0 / 686 ( 0 % )                             ;

+; Total DSP Blocks                ; 0 / 156 ( 0 % )                             ;

+; Total HSSI RX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % )                               ;

+; Total HSSI TX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA TX Serializers   ; 0 / 6 ( 0 % )                               ;

+; Total PLLs                      ; 0 / 13 ( 0 % )                              ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                               ;

++---------------------------------+---------------------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Settings                                                                                                                                            ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Option                                                                     ; Setting                               ; Default Value                         ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Device                                                                     ; 5CGXFC7C7F23C8                        ;                                       ;

+; Use smart compilation                                                      ; Off                                   ; Off                                   ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;

+; Enable compact report table                                                ; Off                                   ; Off                                   ;

+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;

+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;

+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;

+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;

+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;

+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;

+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;

+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;

+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;

+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;

+; SSN Optimization                                                           ; Off                                   ; Off                                   ;

+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;

+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;

+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;

+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;

+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;

+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;

+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;

+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;

+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;

+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;

+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;

+; Auto Delay Chains                                                          ; On                                    ; On                                    ;

+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;

+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;

+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;

+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;

+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;

+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;

+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;

+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;

+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;

+; Auto Global Clock                                                          ; On                                    ; On                                    ;

+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;

+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;

+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;

+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;

+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;

+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;

+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;

+; Clamping Diode                                                             ; Off                                   ; Off                                   ;

+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;

+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 4           ;

+; Maximum allowed            ; 2           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 2           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.3%      ;

++----------------------------+-------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Netlist Optimizations                                                                                                                                     ;

++--------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+

+; Node               ; Action  ; Operation ; Reason                     ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;

++--------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+

+; clock~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ;           ;                ;                  ;                  ;                       ;

++--------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+

+

+

++-------------------------------------------------------------------------------------------------+

+; Incremental Compilation Preservation Summary                                                    ;

++---------------------+-------------------+----------------------------+--------------------------+

+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;

++---------------------+-------------------+----------------------------+--------------------------+

+; Placement (by node) ;                   ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 38 ) ; 0.00 % ( 0 / 38 )          ; 0.00 % ( 0 / 38 )        ;

+;     -- Achieved     ; 0.00 % ( 0 / 38 ) ; 0.00 % ( 0 / 38 )          ; 0.00 % ( 0 / 38 )        ;

+;                     ;                   ;                            ;                          ;

+; Routing (by net)    ;                   ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

++---------------------+-------------------+----------------------------+--------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Partition Settings                                                                                                                                             ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;

+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Placement Preservation                                                                                     ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Top                            ; 0.00 % ( 0 / 38 )     ; N/A                     ; Source File       ; N/A                 ;       ;

+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+

+

++--------------+

+; Pin-Out File ;

++--------------+

+The pin-out file can be found in C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.pin.

+

+

++------------------------------------------------------------------------------------------+

+; Fitter Resource Usage Summary                                                            ;

++-------------------------------------------------------------+--------------------+-------+

+; Resource                                                    ; Usage              ; %     ;

++-------------------------------------------------------------+--------------------+-------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 5 / 56,480         ; < 1 % ;

+; ALMs needed [=A-B+C]                                        ; 5                  ;       ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 5 / 56,480         ; < 1 % ;

+;         [a] ALMs used for LUT logic and registers           ; 4                  ;       ;

+;         [b] ALMs used for LUT logic                         ; 1                  ;       ;

+;         [c] ALMs used for registers                         ; 0                  ;       ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 56,480         ; 0 %   ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 56,480         ; 0 %   ;

+;         [a] Due to location constrained logic               ; 0                  ;       ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;

+;         [c] Due to LAB input limits                         ; 0                  ;       ;

+;         [d] Due to virtual I/Os                             ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Difficulty packing design                                   ; Low                ;       ;

+;                                                             ;                    ;       ;

+; Total LABs:  partially or completely used                   ; 2 / 5,648          ; < 1 % ;

+;     -- Logic LABs                                           ; 2                  ;       ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Combinational ALUT usage for logic                          ; 9                  ;       ;

+;     -- 7 input functions                                    ; 0                  ;       ;

+;     -- 6 input functions                                    ; 0                  ;       ;

+;     -- 5 input functions                                    ; 0                  ;       ;

+;     -- 4 input functions                                    ; 0                  ;       ;

+;     -- <=3 input functions                                  ; 9                  ;       ;

+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Dedicated logic registers                                   ; 8                  ;       ;

+;     -- By type:                                             ;                    ;       ;

+;         -- Primary logic registers                          ; 8 / 112,960        ; < 1 % ;

+;         -- Secondary logic registers                        ; 0 / 112,960        ; 0 %   ;

+;     -- By function:                                         ;                    ;       ;

+;         -- Design implementation registers                  ; 8                  ;       ;

+;         -- Routing optimization registers                   ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Virtual pins                                                ; 0                  ;       ;

+; I/O pins                                                    ; 10 / 268           ; 4 %   ;

+;     -- Clock pins                                           ; 1 / 11             ; 9 %   ;

+;     -- Dedicated input pins                                 ; 0 / 23             ; 0 %   ;

+;                                                             ;                    ;       ;

+; M10K blocks                                                 ; 0 / 686            ; 0 %   ;

+; Total MLAB memory bits                                      ; 0                  ;       ;

+; Total block memory bits                                     ; 0 / 7,024,640      ; 0 %   ;

+; Total block memory implementation bits                      ; 0 / 7,024,640      ; 0 %   ;

+;                                                             ;                    ;       ;

+; Total DSP Blocks                                            ; 0 / 156            ; 0 %   ;

+;                                                             ;                    ;       ;

+; Fractional PLLs                                             ; 0 / 7              ; 0 %   ;

+; Global signals                                              ; 1                  ;       ;

+;     -- Global clocks                                        ; 1 / 16             ; 6 %   ;

+;     -- Quadrant clocks                                      ; 0 / 88             ; 0 %   ;

+;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;

+; SERDES Transmitters                                         ; 0 / 120            ; 0 %   ;

+; SERDES Receivers                                            ; 0 / 120            ; 0 %   ;

+; JTAGs                                                       ; 0 / 1              ; 0 %   ;

+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;

+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;

+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;

+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;

+; Hard IPs                                                    ; 0 / 1              ; 0 %   ;

+; Standard RX PCSs                                            ; 0 / 6              ; 0 %   ;

+; HSSI PMA RX Deserializers                                   ; 0 / 6              ; 0 %   ;

+; Standard TX PCSs                                            ; 0 / 6              ; 0 %   ;

+; HSSI PMA TX Serializers                                     ; 0 / 6              ; 0 %   ;

+; Channel PLLs                                                ; 0 / 6              ; 0 %   ;

+; Impedance control blocks                                    ; 0 / 3              ; 0 %   ;

+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;

+; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.0% ;       ;

+; Peak interconnect usage (total/H/V)                         ; 0.0% / 0.0% / 0.1% ;       ;

+; Maximum fan-out                                             ; 8                  ;       ;

+; Highest non-global fan-out                                  ; 8                  ;       ;

+; Total fan-out                                               ; 58                 ;       ;

+; Average fan-out                                             ; 1.53               ;       ;

++-------------------------------------------------------------+--------------------+-------+

+

+

++---------------------------------------------------------------------------------------------------------------------+

+; Fitter Partition Statistics                                                                                         ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Statistic                                                   ; Top                  ; hard_block:auto_generated_inst ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 5 / 56480 ( < 1 % )  ; 0 / 56480 ( 0 % )              ;

+; ALMs needed [=A-B+C]                                        ; 5                    ; 0                              ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 5 / 56480 ( < 1 % )  ; 0 / 56480 ( 0 % )              ;

+;         [a] ALMs used for LUT logic and registers           ; 4                    ; 0                              ;

+;         [b] ALMs used for LUT logic                         ; 1                    ; 0                              ;

+;         [c] ALMs used for registers                         ; 0                    ; 0                              ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                    ; 0                              ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 56480 ( 0 % )    ; 0 / 56480 ( 0 % )              ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 56480 ( 0 % )    ; 0 / 56480 ( 0 % )              ;

+;         [a] Due to location constrained logic               ; 0                    ; 0                              ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                    ; 0                              ;

+;         [c] Due to LAB input limits                         ; 0                    ; 0                              ;

+;         [d] Due to virtual I/Os                             ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Difficulty packing design                                   ; Low                  ; Low                            ;

+;                                                             ;                      ;                                ;

+; Total LABs:  partially or completely used                   ; 2 / 5648 ( < 1 % )   ; 0 / 5648 ( 0 % )               ;

+;     -- Logic LABs                                           ; 2                    ; 0                              ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Combinational ALUT usage for logic                          ; 9                    ; 0                              ;

+;     -- 7 input functions                                    ; 0                    ; 0                              ;

+;     -- 6 input functions                                    ; 0                    ; 0                              ;

+;     -- 5 input functions                                    ; 0                    ; 0                              ;

+;     -- 4 input functions                                    ; 0                    ; 0                              ;

+;     -- <=3 input functions                                  ; 9                    ; 0                              ;

+; Combinational ALUT usage for route-throughs                 ; 0                    ; 0                              ;

+; Memory ALUT usage                                           ; 0                    ; 0                              ;

+;     -- 64-address deep                                      ; 0                    ; 0                              ;

+;     -- 32-address deep                                      ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Dedicated logic registers                                   ; 0                    ; 0                              ;

+;     -- By type:                                             ;                      ;                                ;

+;         -- Primary logic registers                          ; 8 / 112960 ( < 1 % ) ; 0 / 112960 ( 0 % )             ;

+;         -- Secondary logic registers                        ; 0 / 112960 ( 0 % )   ; 0 / 112960 ( 0 % )             ;

+;     -- By function:                                         ;                      ;                                ;

+;         -- Design implementation registers                  ; 8                    ; 0                              ;

+;         -- Routing optimization registers                   ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+;                                                             ;                      ;                                ;

+; Virtual pins                                                ; 0                    ; 0                              ;

+; I/O pins                                                    ; 10                   ; 0                              ;

+; I/O registers                                               ; 0                    ; 0                              ;

+; Total block memory bits                                     ; 0                    ; 0                              ;

+; Total block memory implementation bits                      ; 0                    ; 0                              ;

+; Clock enable block                                          ; 1 / 122 ( < 1 % )    ; 0 / 122 ( 0 % )                ;

+;                                                             ;                      ;                                ;

+; Connections                                                 ;                      ;                                ;

+;     -- Input Connections                                    ; 0                    ; 0                              ;

+;     -- Registered Input Connections                         ; 0                    ; 0                              ;

+;     -- Output Connections                                   ; 0                    ; 0                              ;

+;     -- Registered Output Connections                        ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Internal Connections                                        ;                      ;                                ;

+;     -- Total Connections                                    ; 58                   ; 0                              ;

+;     -- Registered Connections                               ; 17                   ; 0                              ;

+;                                                             ;                      ;                                ;

+; External Connections                                        ;                      ;                                ;

+;     -- Top                                                  ; 0                    ; 0                              ;

+;     -- hard_block:auto_generated_inst                       ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Partition Interface                                         ;                      ;                                ;

+;     -- Input Ports                                          ; 2                    ; 0                              ;

+;     -- Output Ports                                         ; 8                    ; 0                              ;

+;     -- Bidir Ports                                          ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Registered Ports                                            ;                      ;                                ;

+;     -- Registered Input Ports                               ; 0                    ; 0                              ;

+;     -- Registered Output Ports                              ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Port Connectivity                                           ;                      ;                                ;

+;     -- Input Ports driven by GND                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by GND                           ; 0                    ; 0                              ;

+;     -- Input Ports driven by VCC                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by VCC                           ; 0                    ; 0                              ;

+;     -- Input Ports with no Source                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Source                          ; 0                    ; 0                              ;

+;     -- Input Ports with no Fanout                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Fanout                          ; 0                    ; 0                              ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Input Pins                                                                                                                                                                                                                                                                            ;

++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;

++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; clock  ; M16   ; 5B       ; 89           ; 35           ; 60           ; 8                     ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;

+; enable ; N16   ; 5B       ; 89           ; 35           ; 43           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;

++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;

++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;

++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; count[0] ; M20   ; 5B       ; 89           ; 37           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[1] ; N21   ; 5B       ; 89           ; 35           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[2] ; N19   ; 5B       ; 89           ; 36           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[3] ; L22   ; 5B       ; 89           ; 36           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[4] ; N20   ; 5B       ; 89           ; 35           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[5] ; M18   ; 5B       ; 89           ; 36           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[6] ; M22   ; 5B       ; 89           ; 36           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[7] ; L18   ; 5B       ; 89           ; 38           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+

+

++----------------------------------------------------------------------------+

+; I/O Bank Usage                                                             ;

++----------+------------------+---------------+--------------+---------------+

+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;

++----------+------------------+---------------+--------------+---------------+

+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; B1L      ; 0 / 14 ( 0 % )   ; --            ; --           ; --            ;

+; B0L      ; 0 / 14 ( 0 % )   ; --            ; --           ; --            ;

+; 3A       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 3B       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 4A       ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 5A       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 5B       ; 10 / 16 ( 63 % ) ; 2.5V          ; --           ; 2.5V          ;

+; 7A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 8A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

++----------+------------------+---------------+--------------+---------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; All Package Pins                                                                                                                                                            ;

++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;

++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; A1       ;            ;          ; RREF                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A2       ; 538        ; 9A       ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A3       ;            ; --       ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;

+; A4       ; 540        ; 9A       ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A5       ; 466        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A6       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A7       ; 475        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A8       ; 473        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A9       ; 464        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A10      ; 462        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A12      ; 444        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A13      ; 432        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A14      ; 420        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A15      ; 418        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A16      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A17      ; 403        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A18      ; 401        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A19      ; 404        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A20      ; 402        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A22      ; 396        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA1      ; 39         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA2      ; 38         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA3      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA4      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA5      ; 47         ; 3A       ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AA6      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA7      ; 105        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA8      ; 108        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA9      ; 115        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA10     ; 113        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA11     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA12     ; 131        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA13     ; 139        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA14     ; 137        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA15     ; 142        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA16     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA17     ; 153        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA18     ; 155        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA19     ; 156        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA20     ; 158        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA21     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA22     ; 163        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB1      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB2      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB3      ; 49         ; 3A       ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB4      ; 51         ; 3A       ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB5      ; 102        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB6      ; 100        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB7      ; 107        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB8      ; 110        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB9      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB10     ; 124        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB11     ; 126        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB12     ; 134        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB13     ; 132        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB14     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB15     ; 140        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB16     ;            ; 4A       ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB17     ; 145        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB18     ; 147        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB19     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB20     ; 148        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB21     ; 150        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB22     ; 161        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B3       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B4       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B5       ; 468        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B6       ; 470        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B7       ; 472        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B8       ;            ; 8A       ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; B9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B10      ; 465        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B11      ; 452        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B12      ; 442        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B13      ; 430        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B15      ; 427        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B16      ; 406        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B17      ; 384        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B18      ; 382        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B19      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; B20      ; 380        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B21      ; 387        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B22      ; 394        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C1       ; 19         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C2       ; 18         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C5       ; 542        ; 9A       ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C6       ; 474        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C7       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C8       ; 480        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C9       ; 467        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C10      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C11      ; 450        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C12      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C13      ; 443        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C14      ;            ; 7A       ; VREFB7AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; C15      ; 425        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C16      ; 408        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C18      ; 395        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C19      ; 393        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C20      ; 378        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C21      ; 385        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C22      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D3       ; 16         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D4       ; 17         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D6       ; 476        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D7       ; 478        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D8       ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D9       ; 479        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D11      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D12      ; 449        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D13      ; 441        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D14      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D15      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D16      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D17      ; 409        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D18      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D19      ; 379        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D20      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D21      ; 376        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D22      ; 392        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E1       ; 20         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E2       ; 21         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E5       ; 539        ; 9A       ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E6       ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E7       ; 484        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E8       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E9       ; 477        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E10      ; 469        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E11      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E12      ; 451        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E14      ; 433        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E15      ; 417        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E16      ; 411        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E17      ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E18      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E19      ; 377        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E20      ; 398        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E21      ; 374        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E22      ; 390        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F3       ; 541        ; 9A       ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F4       ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F5       ; 14         ; B1L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; F6       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F7       ; 482        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F8       ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; F9       ; 471        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F10      ; 455        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F11      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F12      ; 440        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F13      ; 435        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F14      ; 428        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F15      ; 419        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F16      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F17      ; 372        ; 7A       ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F18      ; 399        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F19      ; 397        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F20      ; 400        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F21      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F22      ; 388        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G1       ; 23         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G2       ; 22         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G4       ; 15         ; B1L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; G5       ; 537        ; 9A       ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G6       ; 481        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G7       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G8       ; 460        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G10      ; 453        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G11      ; 438        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G12      ; 447        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G13      ; 439        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G14      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G15      ; 426        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G16      ; 412        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G17      ; 410        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G18      ; 413        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G19      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G20      ; 389        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G21      ; 375        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G22      ; 386        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H5       ; 536        ; 9A       ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H6       ; 483        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H8       ; 458        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H9       ; 463        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H10      ; 436        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H11      ; 445        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H13      ; 437        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H14      ; 429        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H15      ; 423        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H16      ; 421        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H17      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H18      ; 415        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H19      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H20      ; 391        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H21      ; 373        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J1       ; 24         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J2       ; 25         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J6       ; 535        ; 9A       ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J7       ; 457        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J8       ; 459        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J9       ; 461        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J11      ; 434        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J13      ; 431        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J16      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J17      ; 422        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J18      ; 416        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J19      ; 414        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J20      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J21      ; 381        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J22      ; 383        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K3       ;            ; --       ; VCCL_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K5       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K6       ; 534        ; 9A       ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K7       ; 456        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K8       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K9       ; 448        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K16      ; 424        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K17      ; 284        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K18      ;            ; 5B       ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K19      ; 407        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K20      ; 405        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K21      ; 289        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K22      ; 291        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L1       ; 27         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L2       ; 26         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L6       ; 533        ; 9A       ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L7       ; 454        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; L8       ; 446        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; L9       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L16      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L17      ; 286        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L18      ; 290        ; 5B       ; count[7]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; L19      ; 288        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L20      ;            ; 5B       ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; L21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L22      ; 283        ; 5B       ; count[3]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M3       ;            ; --       ; VCCH_GXBL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M5       ; 42         ; 3A       ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;

+; M6       ; 64         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M7       ; 66         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M8       ; 112        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M9       ; 114        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M16      ; 278        ; 5B       ; clock                           ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M17      ;            ; 5B       ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M18      ; 282        ; 5B       ; count[5]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M19      ;            ; 5B       ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M20      ; 285        ; 5B       ; count[0]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M21      ; 287        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M22      ; 281        ; 5B       ; count[6]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N1       ; 28         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; N2       ; 29         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; N3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N6       ; 58         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N8       ; 106        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N9       ; 130        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N16      ; 276        ; 5B       ; enable                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N18      ;            ; 5B       ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N19      ; 280        ; 5B       ; count[2]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N20      ; 277        ; 5B       ; count[4]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N21      ; 279        ; 5B       ; count[1]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P3       ;            ; --       ; VCCL_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P5       ; 44         ; 3A       ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; P6       ; 56         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P7       ; 67         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P8       ; 104        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P9       ; 128        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P12      ; 123        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P14      ; 168        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P16      ; 225        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P17      ; 227        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P18      ; 226        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P19      ; 224        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P20      ;            ; 5A       ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P21      ;            ; 5A       ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P22      ; 222        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R1       ; 31         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; R2       ; 30         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; R3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R4       ; 43         ; 3A       ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; R5       ; 54         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R6       ; 52         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R7       ; 65         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R8       ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R9       ; 119        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R10      ; 125        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R11      ; 127        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R12      ; 121        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R14      ; 170        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R15      ; 219        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R16      ; 221        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R17      ; 223        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R18      ;            ; 5A       ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R19      ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; R20      ;            ; 5A       ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; R21      ; 220        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R22      ; 218        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T3       ;            ; --       ; VCCH_GXBL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T4       ; 45         ; 3A       ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; T5       ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T6       ;            ; 3A       ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T7       ; 60         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T8       ; 62         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T9       ; 109        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T10      ; 117        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T11      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T12      ; 136        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T13      ; 138        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T14      ; 152        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T15      ; 217        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T16      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T17      ; 215        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T18      ; 213        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T19      ; 212        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T20      ; 214        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T22      ; 216        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U1       ; 32         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; U2       ; 33         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; U3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U4       ; 41         ; B0L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; U5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U6       ; 61         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U7       ; 53         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U8       ; 55         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U10      ; 111        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U11      ; 120        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U12      ; 122        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U13      ; 135        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U14      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U15      ; 154        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U16      ; 176        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U17      ; 178        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U18      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U19      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U20      ; 179        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U21      ; 177        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U22      ; 172        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V3       ; 50         ; 3A       ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; V4       ; 40         ; B0L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; V5       ; 46         ; 3A       ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; V6       ; 63         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V8       ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; V9       ; 101        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V10      ; 103        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V11      ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V13      ; 133        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V14      ; 144        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V15      ; 146        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V16      ; 160        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V18      ; 175        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V19      ; 173        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V20      ; 157        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V21      ; 174        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W1       ; 35         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; W2       ; 34         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; W3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W5       ; 48         ; 3A       ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; W6       ;            ; 3A       ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W7       ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W8       ; 57         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W9       ; 59         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W10      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W11      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W12      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W13      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W14      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W15      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W16      ; 162        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W17      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W18      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W19      ; 159        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W20      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W21      ; 171        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W22      ; 166        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y3       ; 36         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y4       ; 37         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y6       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y7       ;            ; 3A       ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y8       ;            ; 3A       ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y9       ; 118        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y10      ; 116        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y11      ; 129        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y12      ;            ; 3B       ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y13      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y14      ; 141        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y15      ; 143        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y16      ; 149        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y17      ; 151        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y18      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y19      ; 167        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y20      ; 165        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y21      ; 169        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y22      ; 164        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+Note: Pin directions (input, output or bidir) are based on device operating in user mode.

+

+

++------------------------------------------+

+; I/O Assignment Warnings                  ;

++----------+-------------------------------+

+; Pin Name ; Reason                        ;

++----------+-------------------------------+

+; count[0] ; Incomplete set of assignments ;

+; count[1] ; Incomplete set of assignments ;

+; count[2] ; Incomplete set of assignments ;

+; count[3] ; Incomplete set of assignments ;

+; count[4] ; Incomplete set of assignments ;

+; count[5] ; Incomplete set of assignments ;

+; count[6] ; Incomplete set of assignments ;

+; count[7] ; Incomplete set of assignments ;

+; clock    ; Incomplete set of assignments ;

+; enable   ; Incomplete set of assignments ;

+; count[0] ; Missing location assignment   ;

+; count[1] ; Missing location assignment   ;

+; count[2] ; Missing location assignment   ;

+; count[3] ; Missing location assignment   ;

+; count[4] ; Missing location assignment   ;

+; count[5] ; Missing location assignment   ;

+; count[6] ; Missing location assignment   ;

+; count[7] ; Missing location assignment   ;

+; clock    ; Missing location assignment   ;

+; enable   ; Missing location assignment   ;

++----------+-------------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                  ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+; |ex5                       ; 4.5 (4.5)            ; 4.5 (4.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 9 (9)               ; 8 (8)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 10   ; 0            ; |ex5                ; ex5         ; work         ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Delay Chain Summary                                                                                                     ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; count[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[7] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; clock    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; enable   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+

+

++----------------------------------------------------+

+; Pad To Core Delay Chain Fanout                     ;

++----------------------+-------------------+---------+

+; Source Pin / Fanout  ; Pad To Core Index ; Setting ;

++----------------------+-------------------+---------+

+; clock                ;                   ;         ;

+; enable               ;                   ;         ;

+;      - count[1]~reg0 ; 1                 ; 0       ;

+;      - count[2]~reg0 ; 1                 ; 0       ;

+;      - count[3]~reg0 ; 1                 ; 0       ;

+;      - count[4]~reg0 ; 1                 ; 0       ;

+;      - count[5]~reg0 ; 1                 ; 0       ;

+;      - count[6]~reg0 ; 1                 ; 0       ;

+;      - count[7]~reg0 ; 1                 ; 0       ;

+;      - count[0]~reg0 ; 1                 ; 0       ;

++----------------------+-------------------+---------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Control Signals                                                                                                           ;

++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+

+; Name   ; Location ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+

+; clock  ; PIN_M16  ; 8       ; Clock        ; yes    ; Global Clock         ; GCLK10           ; --                        ;

+; enable ; PIN_N16  ; 8       ; Clock enable ; no     ; --                   ; --               ; --                        ;

++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------+

+; Global & Other Fast Signals                                                                      ;

++-------+----------+---------+----------------------+------------------+---------------------------+

+; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++-------+----------+---------+----------------------+------------------+---------------------------+

+; clock ; PIN_M16  ; 8       ; Global Clock         ; GCLK10           ; --                        ;

++-------+----------+---------+----------------------+------------------+---------------------------+

+

+

++------------------------------------------------------+

+; Routing Usage Summary                                ;

++------------------------------+-----------------------+

+; Routing Resource Type        ; Usage                 ;

++------------------------------+-----------------------+

+; Block interconnects          ; 9 / 374,484 ( < 1 % ) ;

+; C12 interconnects            ; 0 / 16,664 ( 0 % )    ;

+; C2 interconnects             ; 5 / 155,012 ( < 1 % ) ;

+; C4 interconnects             ; 0 / 72,600 ( 0 % )    ;

+; DQS bus muxes                ; 0 / 30 ( 0 % )        ;

+; DQS-18 I/O buses             ; 0 / 30 ( 0 % )        ;

+; DQS-9 I/O buses              ; 0 / 30 ( 0 % )        ;

+; Direct links                 ; 0 / 374,484 ( 0 % )   ;

+; Global clocks                ; 1 / 16 ( 6 % )        ;

+; Horizontal periphery clocks  ; 0 / 72 ( 0 % )        ;

+; Local interconnects          ; 1 / 112,960 ( < 1 % ) ;

+; Quadrant clocks              ; 0 / 88 ( 0 % )        ;

+; R14 interconnects            ; 0 / 15,868 ( 0 % )    ;

+; R14/C12 interconnect drivers ; 0 / 27,256 ( 0 % )    ;

+; R3 interconnects             ; 1 / 169,296 ( < 1 % ) ;

+; R6 interconnects             ; 5 / 330,800 ( < 1 % ) ;

+; Spine clocks                 ; 1 / 480 ( < 1 % )     ;

+; Wire stub REs                ; 0 / 20,834 ( 0 % )    ;

++------------------------------+-----------------------+

+

+

++------------------------------------------+

+; I/O Rules Summary                        ;

++----------------------------------+-------+

+; I/O Rules Statistic              ; Total ;

++----------------------------------+-------+

+; Total I/O Rules                  ; 28    ;

+; Number of I/O Rules Passed       ; 6     ;

+; Number of I/O Rules Failed       ; 0     ;

+; Number of I/O Rules Unchecked    ; 0     ;

+; Number of I/O Rules Inapplicable ; 22    ;

++----------------------------------+-------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Details                                                                                                                                                                                                                                                                 ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+

+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area                ; Extra Information ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+

+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;

+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;

+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;

+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;

+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;

+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;

+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;

+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;

+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;

+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;

+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;

+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;

+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;

+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;

+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;

+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;

+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                            ; None     ; ----                                                                     ; On Chip Termination ;                   ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                              ;

++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;

++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 10        ; 0            ; 0            ; 10        ; 10        ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Inapplicable ; 10           ; 10           ; 10           ; 10           ; 10           ; 0         ; 10           ; 10           ; 0         ; 0         ; 10           ; 2            ; 10           ; 10           ; 10           ; 10           ; 2            ; 10           ; 10           ; 10           ; 10           ; 2            ; 10           ; 10           ; 10           ; 10           ; 10           ; 10           ;

+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; count[0]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[1]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[2]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[3]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[4]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[5]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[6]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[7]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; clock              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; enable             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+

+

++------------------------------------------------------------------------------------------------+

+; Fitter Device Options                                                                          ;

++------------------------------------------------------------------+-----------------------------+

+; Option                                                           ; Setting                     ;

++------------------------------------------------------------------+-----------------------------+

+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;

+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;

+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;

+; Enable INIT_DONE output                                          ; Off                         ;

+; Configuration scheme                                             ; Passive Serial              ;

+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;

+; Enable CvP_CONFDONE pin                                          ; Off                         ;

+; Enable open drain on CRC_ERROR pin                               ; On                          ;

+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;

+; Enable open drain on INIT_DONE pin                               ; On                          ;

+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;

+; Enable open drain on nCEO pin                                    ; On                          ;

+; Enable Partial Reconfiguration pins                              ; Off                         ;

+; Enable input tri-state on active configuration pins in user mode ; Off                         ;

+; Enable internal scrubbing                                        ; Off                         ;

+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;

+; Device initialization clock source                               ; Internal Oscillator         ;

+; Configuration via Protocol                                       ; Off                         ;

+; Configuration Voltage Level                                      ; Auto                        ;

+; Force Configuration Voltage Level                                ; Off                         ;

+; Enable nCEO output                                               ; Off                         ;

+; Data[15..8]                                                      ; Unreserved                  ;

+; Data[7..5]                                                       ; Unreserved                  ;

+; Base pin-out file on sameframe device                            ; Off                         ;

++------------------------------------------------------------------+-----------------------------+

+

+

++------------------------------------+

+; Operating Settings and Conditions  ;

++---------------------------+--------+

+; Setting                   ; Value  ;

++---------------------------+--------+

+; Nominal Core Voltage      ; 1.10 V ;

+; Low Junction Temperature  ; 0 °C   ;

+; High Junction Temperature ; 85 °C  ;

++---------------------------+--------+

+

+

++------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Summary              ;

++-----------------+----------------------+-------------------+

+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;

++-----------------+----------------------+-------------------+

+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.

+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.

+

+

++------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Details              ;

++-----------------+----------------------+-------------------+

+; Source Register ; Destination Register ; Delay Added in ns ;

++-----------------+----------------------+-------------------+

+; count[0]~reg0   ; count[7]~reg0        ; 0.463             ;

++-----------------+----------------------+-------------------+

+Note: This table only shows the top 1 path(s) that have the largest delay added for hold.

+

+

++-----------------+

+; Fitter Messages ;

++-----------------+

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected

+Info (119006): Selected device 5CGXFC7C7F23C8 for design "ex5"

+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.

+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.

+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.

+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

+Critical Warning (169085): No exact pin location assignment(s) for 10 pins of 10 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.

+Info (184020): Starting Fitter periphery placement operations

+Info (11191): Automatically promoted 1 clock (1 global)

+    Info (11162): clock~inputCLKENA0 with 8 fanout uses global clock CLKCTRL_G10

+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

+Info (176233): Starting register packing

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332144): No user constrained base clocks found in the design

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.

+Info (176235): Finished register packing

+    Extra Info (176219): No registers were packed into other blocks

+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:21

+Info (170189): Fitter placement preparation operations beginning

+Info (14951): The Fitter is using Advanced Physical Optimization.

+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:05

+Info (170191): Fitter placement operations beginning

+Info (170137): Fitter placement was successful

+Info (170192): Fitter placement operations ending: elapsed time is 00:00:04

+Info (170193): Fitter routing operations beginning

+Info (170195): Router estimated average interconnect usage is 0% of the available device resources

+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45

+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.

+    Info (170201): Optimizations that may affect the design's routability were skipped

+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02

+Info (11888): Total time spent on timing analysis during the Fitter is 0.42 seconds.

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:07

+Info (144001): Generated suppressed messages file C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg

+Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings

+    Info: Peak virtual memory: 2264 megabytes

+    Info: Processing ended: Tue Nov 22 09:28:31 2016

+    Info: Elapsed time: 00:01:28

+    Info: Total CPU time (on all processors): 00:01:40

+

+

++----------------------------+

+; Fitter Suppressed Messages ;

++----------------------------+

+The suppressed messages can be found in C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg.

+

+

diff --git a/part_2/ex5/output_files/ex5.fit.smsg b/part_2/ex5/output_files/ex5.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing

+Extra Info (176237): Finished Fast Input/Output/OE register processing

+Extra Info (176238): Start inferring scan chains for DSP blocks

+Extra Info (176239): Inferring scan chains for DSP blocks is complete

+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density

+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

diff --git a/part_2/ex5/output_files/ex5.fit.summary b/part_2/ex5/output_files/ex5.fit.summary
new file mode 100755
index 0000000..65b612c
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Nov 22 09:28:30 2016

+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Revision Name : ex5

+Top-level Entity Name : ex5

+Family : Cyclone V

+Device : 5CGXFC7C7F23C8

+Timing Models : Final

+Logic utilization (in ALMs) : 5 / 56,480 ( < 1 % )

+Total registers : 8

+Total pins : 10 / 268 ( 4 % )

+Total virtual pins : 0

+Total block memory bits : 0 / 7,024,640 ( 0 % )

+Total RAM Blocks : 0 / 686 ( 0 % )

+Total DSP Blocks : 0 / 156 ( 0 % )

+Total HSSI RX PCSs : 0 / 6 ( 0 % )

+Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % )

+Total HSSI TX PCSs : 0 / 6 ( 0 % )

+Total HSSI PMA TX Serializers : 0 / 6 ( 0 % )

+Total PLLs : 0 / 13 ( 0 % )

+Total DLLs : 0 / 4 ( 0 % )

diff --git a/part_2/ex5/output_files/ex5.flow.rpt b/part_2/ex5/output_files/ex5.flow.rpt
new file mode 100755
index 0000000..f868c8e
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.flow.rpt
@@ -0,0 +1,121 @@
+Flow report for ex5

+Tue Nov 22 09:28:58 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Flow Summary

+  3. Flow Settings

+  4. Flow Non-Default Global Settings

+  5. Flow Elapsed Time

+  6. Flow OS Summary

+  7. Flow Log

+  8. Flow Messages

+  9. Flow Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-------------------------------------------------------------------------------+

+; Flow Summary                                                                  ;

++---------------------------------+---------------------------------------------+

+; Flow Status                     ; Successful - Tue Nov 22 09:28:58 2016       ;

+; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;

+; Revision Name                   ; ex5                                         ;

+; Top-level Entity Name           ; ex5                                         ;

+; Family                          ; Cyclone V                                   ;

+; Device                          ; 5CGXFC7C7F23C8                              ;

+; Timing Models                   ; Final                                       ;

+; Logic utilization (in ALMs)     ; 5 / 56,480 ( < 1 % )                        ;

+; Total registers                 ; 8                                           ;

+; Total pins                      ; 10 / 268 ( 4 % )                            ;

+; Total virtual pins              ; 0                                           ;

+; Total block memory bits         ; 0 / 7,024,640 ( 0 % )                       ;

+; Total DSP Blocks                ; 0 / 156 ( 0 % )                             ;

+; Total HSSI RX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % )                               ;

+; Total HSSI TX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA TX Serializers   ; 0 / 6 ( 0 % )                               ;

+; Total PLLs                      ; 0 / 13 ( 0 % )                              ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                               ;

++---------------------------------+---------------------------------------------+

+

+

++-----------------------------------------+

+; Flow Settings                           ;

++-------------------+---------------------+

+; Option            ; Setting             ;

++-------------------+---------------------+

+; Start date & time ; 11/22/2016 09:26:39 ;

+; Main task         ; Compilation         ;

+; Revision Name     ; ex5                 ;

++-------------------+---------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Flow Non-Default Global Settings                                                                                        ;

++-------------------------------------+----------------------------------------+---------------+-------------+------------+

+; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id ;

++-------------------------------------+----------------------------------------+---------------+-------------+------------+

+; COMPILER_SIGNATURE_ID               ; 44883562331268.147980679801764         ; --            ; --          ; --         ;

+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;

+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;

+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;

+; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --         ;

++-------------------------------------+----------------------------------------+---------------+-------------+------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------+

+; Flow Elapsed Time                                                                                                        ;

++----------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;

++----------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Analysis & Synthesis ; 00:00:21     ; 1.0                     ; 686 MB              ; 00:00:43                           ;

+; Fitter               ; 00:01:27     ; 1.0                     ; 2264 MB             ; 00:01:39                           ;

+; Assembler            ; 00:00:23     ; 1.0                     ; 707 MB              ; 00:00:15                           ;

+; Total                ; 00:02:11     ; --                      ; --                  ; 00:02:37                           ;

++----------------------+--------------+-------------------------+---------------------+------------------------------------+

+

+

++------------------------------------------------------------------------------------+

+; Flow OS Summary                                                                    ;

++----------------------+------------------+------------+------------+----------------+

+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;

++----------------------+------------------+------------+------------+----------------+

+; Analysis & Synthesis ; Lenovo-PC-Marco  ; Windows 10 ; 10.0       ; x86_64         ;

+; Fitter               ; Lenovo-PC-Marco  ; Windows 10 ; 10.0       ; x86_64         ;

+; Assembler            ; Lenovo-PC-Marco  ; Windows 10 ; 10.0       ; x86_64         ;

++----------------------+------------------+------------+------------+----------------+

+

+

+------------

+; Flow Log ;

+------------

+quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5

+quartus_fit --read_settings_files=off --write_settings_files=off ex5 -c ex5

+quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5

+

+

+

diff --git a/part_2/ex5/output_files/ex5.jdi b/part_2/ex5/output_files/ex5.jdi
new file mode 100755
index 0000000..9f202d3
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>

+  <project>

+    <hash md5_digest_80b="a02c1fe6114b91718b29"/>

+  </project>

+  <file_info>

+    <file device="5CGXFC7C7F23C8" path="ex5.sof" usercode="0xFFFFFFFF"/>

+  </file_info>

+</sld_project_info>

diff --git a/part_2/ex5/output_files/ex5.map.rpt b/part_2/ex5/output_files/ex5.map.rpt
new file mode 100755
index 0000000..3808bd6
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.map.rpt
@@ -0,0 +1,299 @@
+Analysis & Synthesis report for ex5

+Tue Nov 22 09:27:01 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Analysis & Synthesis Summary

+  3. Analysis & Synthesis Settings

+  4. Parallel Compilation

+  5. Analysis & Synthesis Source Files Read

+  6. Analysis & Synthesis Resource Usage Summary

+  7. Analysis & Synthesis Resource Utilization by Entity

+  8. General Register Statistics

+  9. Parameter Settings for User Entity Instance: Top-level Entity: |ex5

+ 10. Post-Synthesis Netlist Statistics for Top Partition

+ 11. Elapsed Time Per Partition

+ 12. Analysis & Synthesis Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-------------------------------------------------------------------------------+

+; Analysis & Synthesis Summary                                                  ;

++---------------------------------+---------------------------------------------+

+; Analysis & Synthesis Status     ; Successful - Tue Nov 22 09:27:01 2016       ;

+; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;

+; Revision Name                   ; ex5                                         ;

+; Top-level Entity Name           ; ex5                                         ;

+; Family                          ; Cyclone V                                   ;

+; Logic utilization (in ALMs)     ; N/A                                         ;

+; Total registers                 ; 8                                           ;

+; Total pins                      ; 10                                          ;

+; Total virtual pins              ; 0                                           ;

+; Total block memory bits         ; 0                                           ;

+; Total DSP Blocks                ; 0                                           ;

+; Total HSSI RX PCSs              ; 0                                           ;

+; Total HSSI PMA RX Deserializers ; 0                                           ;

+; Total HSSI TX PCSs              ; 0                                           ;

+; Total HSSI PMA TX Serializers   ; 0                                           ;

+; Total PLLs                      ; 0                                           ;

+; Total DLLs                      ; 0                                           ;

++---------------------------------+---------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Settings                                                                                             ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Option                                                                          ; Setting            ; Default Value      ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Device                                                                          ; 5CGXFC7C7F23C8     ;                    ;

+; Top-level entity name                                                           ; ex5                ; ex5                ;

+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;

+; Use smart compilation                                                           ; Off                ; Off                ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;

+; Enable compact report table                                                     ; Off                ; Off                ;

+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;

+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;

+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;

+; Preserve fewer node names                                                       ; On                 ; On                 ;

+; OpenCore Plus hardware evaluation                                               ; Enable             ; Enable             ;

+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;

+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;

+; State Machine Processing                                                        ; Auto               ; Auto               ;

+; Safe State Machine                                                              ; Off                ; Off                ;

+; Extract Verilog State Machines                                                  ; On                 ; On                 ;

+; Extract VHDL State Machines                                                     ; On                 ; On                 ;

+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;

+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;

+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;

+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;

+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;

+; Parallel Synthesis                                                              ; On                 ; On                 ;

+; DSP Block Balancing                                                             ; Auto               ; Auto               ;

+; NOT Gate Push-Back                                                              ; On                 ; On                 ;

+; Power-Up Don't Care                                                             ; On                 ; On                 ;

+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;

+; Remove Duplicate Registers                                                      ; On                 ; On                 ;

+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;

+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;

+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;

+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;

+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;

+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;

+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;

+; Optimization Technique                                                          ; Balanced           ; Balanced           ;

+; Carry Chain Length                                                              ; 70                 ; 70                 ;

+; Auto Carry Chains                                                               ; On                 ; On                 ;

+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;

+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;

+; Auto ROM Replacement                                                            ; On                 ; On                 ;

+; Auto RAM Replacement                                                            ; On                 ; On                 ;

+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;

+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;

+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;

+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;

+; Strict RAM Replacement                                                          ; Off                ; Off                ;

+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;

+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;

+; Auto Resource Sharing                                                           ; Off                ; Off                ;

+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;

+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;

+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;

+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;

+; Report Parameter Settings                                                       ; On                 ; On                 ;

+; Report Source Assignments                                                       ; On                 ; On                 ;

+; Report Connectivity Checks                                                      ; On                 ; On                 ;

+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;

+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;

+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;

+; HDL message level                                                               ; Level2             ; Level2             ;

+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;

+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;

+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;

+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;

+; Clock MUX Protection                                                            ; On                 ; On                 ;

+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;

+; Block Design Naming                                                             ; Auto               ; Auto               ;

+; SDC constraint protection                                                       ; Off                ; Off                ;

+; Synthesis Effort                                                                ; Auto               ; Auto               ;

+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;

+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;

+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;

+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;

+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;

+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;

+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 4           ;

+; Maximum allowed            ; 2           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 2           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.0%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Source Files Read                                                                                                                                                      ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+

+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                        ; Library ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+

+; verilog files/ex5.v              ; yes             ; User Verilog HDL File  ; C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v ;         ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+

+

+

++-----------------------------------------------------------+

+; Analysis & Synthesis Resource Usage Summary               ;

++---------------------------------------------+-------------+

+; Resource                                    ; Usage       ;

++---------------------------------------------+-------------+

+; Estimate of Logic utilization (ALMs needed) ; 4           ;

+;                                             ;             ;

+; Combinational ALUT usage for logic          ; 8           ;

+;     -- 7 input functions                    ; 0           ;

+;     -- 6 input functions                    ; 0           ;

+;     -- 5 input functions                    ; 0           ;

+;     -- 4 input functions                    ; 0           ;

+;     -- <=3 input functions                  ; 8           ;

+;                                             ;             ;

+; Dedicated logic registers                   ; 8           ;

+;                                             ;             ;

+; I/O pins                                    ; 10          ;

+;                                             ;             ;

+; Total DSP Blocks                            ; 0           ;

+;                                             ;             ;

+; Maximum fan-out node                        ; clock~input ;

+; Maximum fan-out                             ; 8           ;

+; Total fan-out                               ; 57          ;

+; Average fan-out                             ; 1.58        ;

++---------------------------------------------+-------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                    ;

++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;

++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+; |ex5                       ; 8 (8)               ; 8 (8)                     ; 0                 ; 0          ; 10   ; 0            ; |ex5                ; ex5         ; work         ;

++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++------------------------------------------------------+

+; General Register Statistics                          ;

++----------------------------------------------+-------+

+; Statistic                                    ; Value ;

++----------------------------------------------+-------+

+; Total registers                              ; 8     ;

+; Number of registers using Synchronous Clear  ; 0     ;

+; Number of registers using Synchronous Load   ; 0     ;

+; Number of registers using Asynchronous Clear ; 0     ;

+; Number of registers using Asynchronous Load  ; 0     ;

+; Number of registers using Clock Enable       ; 8     ;

+; Number of registers using Preset             ; 0     ;

++----------------------------------------------+-------+

+

+

++---------------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: Top-level Entity: |ex5 ;

++----------------+-------+--------------------------------------------+

+; Parameter Name ; Value ; Type                                       ;

++----------------+-------+--------------------------------------------+

+; BIT_SZ         ; 8     ; Signed Integer                             ;

++----------------+-------+--------------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++-----------------------------------------------------+

+; Post-Synthesis Netlist Statistics for Top Partition ;

++-----------------------+-----------------------------+

+; Type                  ; Count                       ;

++-----------------------+-----------------------------+

+; arriav_ff             ; 8                           ;

+;     ENA               ; 8                           ;

+; arriav_lcell_comb     ; 8                           ;

+;     arith             ; 7                           ;

+;         1 data inputs ; 6                           ;

+;         2 data inputs ; 1                           ;

+;     normal            ; 1                           ;

+;         1 data inputs ; 1                           ;

+; boundary_port         ; 10                          ;

+;                       ;                             ;

+; Max LUT depth         ; 1.60                        ;

+; Average LUT depth     ; 1.27                        ;

++-----------------------+-----------------------------+

+

+

++-------------------------------+

+; Elapsed Time Per Partition    ;

++----------------+--------------+

+; Partition Name ; Elapsed Time ;

++----------------+--------------+

+; Top            ; 00:00:02     ;

++----------------+--------------+

+

+

++-------------------------------+

+; Analysis & Synthesis Messages ;

++-------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Analysis & Synthesis

+    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+    Info: Processing started: Tue Nov 22 09:26:38 2016

+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected

+Info (12021): Found 1 design units, including 1 entities, in source file verilog files/counter_8.v

+    Info (12023): Found entity 1: counter_8 File: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/counter_8.v Line: 3

+Info (12021): Found 1 design units, including 1 entities, in source file verilog files/ex5.v

+    Info (12023): Found entity 1: ex5 File: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v Line: 3

+Info (12127): Elaborating entity "ex5" for the top level hierarchy

+Info (286030): Timing-Driven Synthesis is running

+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

+Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different

+    Info (21058): Implemented 2 input pins

+    Info (21059): Implemented 8 output pins

+    Info (21061): Implemented 8 logic cells

+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 698 megabytes

+    Info: Processing ended: Tue Nov 22 09:27:02 2016

+    Info: Elapsed time: 00:00:24

+    Info: Total CPU time (on all processors): 00:00:43

+

+

diff --git a/part_2/ex5/output_files/ex5.map.summary b/part_2/ex5/output_files/ex5.map.summary
new file mode 100755
index 0000000..1b964a4
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Nov 22 09:27:01 2016

+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Revision Name : ex5

+Top-level Entity Name : ex5

+Family : Cyclone V

+Logic utilization (in ALMs) : N/A

+Total registers : 8

+Total pins : 10

+Total virtual pins : 0

+Total block memory bits : 0

+Total DSP Blocks : 0

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0

+Total DLLs : 0

diff --git a/part_2/ex5/output_files/ex5.pin b/part_2/ex5/output_files/ex5.pin
new file mode 100755
index 0000000..1439764
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.pin
@@ -0,0 +1,561 @@
+ -- Copyright (C) 2016  Intel Corporation. All rights reserved.

+ -- Your use of Intel Corporation's design tools, logic functions 

+ -- and other software and tools, and its AMPP partner logic 

+ -- functions, and any output files from any of the foregoing 

+ -- (including device programming or simulation files), and any 

+ -- associated documentation or information are expressly subject 

+ -- to the terms and conditions of the Intel Program License 

+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,

+ -- the Intel MegaCore Function License Agreement, or other 

+ -- applicable license agreement, including, without limitation, 

+ -- that your use is for the sole purpose of programming logic 

+ -- devices manufactured by Intel and sold by Intel or its 

+ -- authorized distributors.  Please refer to the applicable 

+ -- agreement for further details.

+ -- 

+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is

+ -- not intended for use as a Quartus Prime input file. This file cannot be used

+ -- to make Quartus Prime pin assignments - for instructions on how to make pin

+ -- assignments, please see Quartus Prime help.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- NC            : No Connect. This pin has no internal connection to the device.

+ -- DNU           : Do Not Use. This pin MUST NOT be connected.

+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.

+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).

+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC

+ --                 of its bank.

+ --                  Bank 3A:       2.5V

+ --                  Bank 3B:       2.5V

+ --                  Bank 4A:       2.5V

+ --                  Bank 5A:       2.5V

+ --                  Bank 5B:       2.5V

+ --                  Bank 7A:  2.5V

+ --                  Bank 8A:  2.5V

+ --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.

+ -- RREF          : External reference resistor for the quad, MUST be connected to

+ --                 GND via a 2k Ohm resistor.

+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.

+ --                  It can also be used to report unused dedicated pins. The connection

+ --                  on the board for unused dedicated pins depends on whether this will

+ --                  be used in a future design. One example is device migration. When

+ --                  using device migration, refer to the device pin-tables. If it is a

+ --                  GND pin in the pin table or if it will not be used in a future design

+ --                  for another purpose the it MUST be connected to GND. If it is an unused

+ --                  dedicated pin, then it can be connected to a valid signal on the board

+ --                  (low, high, or toggling) if that signal is required for a different

+ --                  revision of the design.

+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.

+ --                  This pin should be connected to GND. It may also be connected  to a

+ --                  valid signal  on the board  (low, high, or toggling)  if that signal

+ --                  is required for a different revision of the design.

+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*

+ --                  either individually through a 10k Ohm resistor to GND or tie all pins

+ --                  together and connect through a single 10k Ohm resistor to GND.

+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.

+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.

+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.

+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.

+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.

+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin

+ --                 must not be connected.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- Pin directions (input, output or bidir) are based on device operating in user mode.

+ ---------------------------------------------------------------------------------

+

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+CHIP  "ex5"  ASSIGNED TO AN: 5CGXFC7C7F23C8

+

+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

+-------------------------------------------------------------------------------------------------------------

+RREF                         : A1        :        :                   :         :           :                

+MSEL2                        : A2        :        :                   :         : 9A        :                

+VCCBAT                       : A3        : power  :                   : 1.2V    :           :                

+nCONFIG                      : A4        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                

+VCCIO8A                      : A6        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                

+GND                          : A11       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7A        :                

+VCCIO7A                      : A16       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7A        :                

+GND                          : A21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A22       :        :                   :         : 7A        :                

+GND                          : AA1       :        :                   :         : B0L       :                

+GND                          : AA2       :        :                   :         : B0L       :                

+GND                          : AA3       : gnd    :                   :         :           :                

+GND                          : AA4       : gnd    :                   :         :           :                

+AS_DATA2, DATA2              : AA5       :        :                   :         : 3A        :                

+GND                          : AA6       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3B        :                

+GND                          : AA11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4A        :                

+VCCIO4A                      : AA16      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                

+VCCIO4A                      : AA21      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 4A        :                

+GND                          : AB1       : gnd    :                   :         :           :                

+GND                          : AB2       : gnd    :                   :         :           :                

+AS_DATA1, DATA1              : AB3       :        :                   :         : 3A        :                

+AS_DATA0, ASDO, DATA0        : AB4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3B        :                

+GND                          : AB9       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4A        :                

+GND                          : AB14      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4A        :                

+VREFB4AN0                    : AB16      : power  :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4A        :                

+GND                          : AB19      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 4A        :                

+GND                          : B1        : gnd    :                   :         :           :                

+GND                          : B2        : gnd    :                   :         :           :                

+DNU                          : B3        :        :                   :         :           :                

+DNU                          : B4        :        :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                

+VREFB8AN0                    : B8        : power  :                   :         : 8A        :                

+GND                          : B9        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7A        :                

+GND                          : B14       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7A        :                

+VCCIO7A                      : B19       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                

+GND                          : C1        :        :                   :         : B1L       :                

+GND                          : C2        :        :                   :         : B1L       :                

+GND                          : C3        : gnd    :                   :         :           :                

+GND                          : C4        : gnd    :                   :         :           :                

+GND                          : C5        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8A        :                

+VCCIO8A                      : C7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                

+VCCPD7A8A                    : C10       : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7A        :                

+VCCIO7A                      : C12       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7A        :                

+VREFB7AN0                    : C14       : power  :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C16       :        :                   :         : 7A        :                

+GND                          : C17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 7A        :                

+VCCIO7A                      : C22       : power  :                   : 2.5V    : 7A        :                

+GND                          : D1        : gnd    :                   :         :           :                

+GND                          : D2        : gnd    :                   :         :           :                

+GXB_NC                       : D3        :        :                   :         : B1L       :                

+GXB_NC                       : D4        :        :                   :         : B1L       :                

+GND                          : D5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                

+VCCPD7A8A                    : D8        : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                

+GND                          : D10       : gnd    :                   :         :           :                

+VCC_AUX                      : D11       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7A        :                

+VCCPD7A8A                    : D14       : power  :                   : 2.5V    : 7A, 8A    :                

+VCCIO7A                      : D15       : power  :                   : 2.5V    : 7A        :                

+VCCPD7A8A                    : D16       : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7A        :                

+VCC_AUX                      : D18       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7A        :                

+GND                          : D20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                

+GXB_NC                       : E1        :        :                   :         : B1L       :                

+GXB_NC                       : E2        :        :                   :         : B1L       :                

+GND                          : E3        : gnd    :                   :         :           :                

+GND                          : E4        : gnd    :                   :         :           :                

+MSEL3                        : E5        :        :                   :         : 9A        :                

+VCC_AUX                      : E6        : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                

+VCCIO8A                      : E8        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8A        :                

+VCCPD7A8A                    : E11       : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7A        :                

+GND                          : E13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7A        :                

+DNU                          : E17       :        :                   :         :           :                

+VCCIO7A                      : E18       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 7A        :                

+GND                          : F1        : gnd    :                   :         :           :                

+GND                          : F2        : gnd    :                   :         :           :                

+MSEL4                        : F3        :        :                   :         : 9A        :                

+VCCA_FPLL                    : F4        : power  :                   : 2.5V    :           :                

+GND                          : F5        :        :                   :         : B1L       :                

+GND                          : F6        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8A        :                

+VCCPGM                       : F8        : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                

+VCCIO7A                      : F11       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7A        :                

+GND                          : F16       : gnd    :                   :         :           :                

+GND                          : F17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7A        :                

+VCCIO7A                      : F21       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 7A        :                

+GND                          : G1        :        :                   :         : B1L       :                

+GND                          : G2        :        :                   :         : B1L       :                

+GND                          : G3        : gnd    :                   :         :           :                

+GND                          : G4        :        :                   :         : B1L       :                

+nCE                          : G5        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G6        :        :                   :         : 8A        :                

+VCCIO8A                      : G7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                

+GND                          : G9        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7A        :                

+VCCIO7A                      : G14       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7A        :                

+GND                          : G19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                

+GND                          : H1        : gnd    :                   :         :           :                

+GND                          : H2        : gnd    :                   :         :           :                

+GND                          : H3        : gnd    :                   :         :           :                

+GND                          : H4        : gnd    :                   :         :           :                

+nSTATUS                      : H5        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 8A        :                

+GND                          : H7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 7A        :                

+GND                          : H12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 7A        :                

+VCCIO7A                      : H17       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7A        :                

+VCCA_FPLL                    : H19       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 7A        :                

+GND                          : H22       : gnd    :                   :         :           :                

+GXB_NC                       : J1        :        :                   :         : B1L       :                

+GXB_NC                       : J2        :        :                   :         : B1L       :                

+GND                          : J3        : gnd    :                   :         :           :                

+VCCE_GXBL                    : J4        : power  :                   : 1.1V    :           :                

+GND                          : J5        : gnd    :                   :         :           :                

+MSEL1                        : J6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                

+VCC                          : J10       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J11       :        :                   :         : 7A        :                

+VCC                          : J12       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 7A        :                

+VCC                          : J14       : power  :                   : 1.1V    :           :                

+GND                          : J15       : gnd    :                   :         :           :                

+VCC                          : J16       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7A        :                

+GND                          : J20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 7A        :                

+GND                          : K1        : gnd    :                   :         :           :                

+GND                          : K2        : gnd    :                   :         :           :                

+VCCL_GXBL                    : K3        : power  :                   : 1.1V    :           :                

+GND                          : K4        : gnd    :                   :         :           :                

+VCCE_GXBL                    : K5        : power  :                   : 1.1V    :           :                

+CONF_DONE                    : K6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                

+GND                          : K8        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K9        :        :                   :         : 7A        :                

+GND                          : K10       : gnd    :                   :         :           :                

+VCC                          : K11       : power  :                   : 1.1V    :           :                

+GND                          : K12       : gnd    :                   :         :           :                

+VCC                          : K13       : power  :                   : 1.1V    :           :                

+GND                          : K14       : gnd    :                   :         :           :                

+VCC                          : K15       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 5B        :                

+VCCIO5B                      : K18       : power  :                   : 2.5V    : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 5B        :                

+GND                          : L1        :        :                   :         : B1L       :                

+GND                          : L2        :        :                   :         : B1L       :                

+GND                          : L3        : gnd    :                   :         :           :                

+VCCE_GXBL                    : L4        : power  :                   : 1.1V    :           :                

+GND                          : L5        : gnd    :                   :         :           :                

+MSEL0                        : L6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 7A        :                

+DNU                          : L9        :        :                   :         :           :                

+VCC                          : L10       : power  :                   : 1.1V    :           :                

+GND                          : L11       : gnd    :                   :         :           :                

+VCC                          : L12       : power  :                   : 1.1V    :           :                

+GND                          : L13       : gnd    :                   :         :           :                

+VCC                          : L14       : power  :                   : 1.1V    :           :                

+GND                          : L15       : gnd    :                   :         :           :                

+VCC                          : L16       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L17       :        :                   :         : 5B        :                

+count[7]                     : L18       : output : 2.5 V             :         : 5B        : N              

+RESERVED_INPUT_WITH_WEAK_PULLUP : L19       :        :                   :         : 5B        :                

+VREFB5BN0                    : L20       : power  :                   :         : 5B        :                

+GND                          : L21       : gnd    :                   :         :           :                

+count[3]                     : L22       : output : 2.5 V             :         : 5B        : N              

+GND                          : M1        : gnd    :                   :         :           :                

+GND                          : M2        : gnd    :                   :         :           :                

+VCCH_GXBL                    : M3        : power  :                   : 2.5V    :           :                

+GND                          : M4        : gnd    :                   :         :           :                

+TDO                          : M5        : output :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 3B        :                

+GND                          : M10       : gnd    :                   :         :           :                

+VCC                          : M11       : power  :                   : 1.1V    :           :                

+GND                          : M12       : gnd    :                   :         :           :                

+VCC                          : M13       : power  :                   : 1.1V    :           :                

+GND                          : M14       : gnd    :                   :         :           :                

+VCC                          : M15       : power  :                   : 1.1V    :           :                

+clock                        : M16       : input  : 2.5 V             :         : 5B        : N              

+VCCPD5B                      : M17       : power  :                   : 2.5V    : 5B        :                

+count[5]                     : M18       : output : 2.5 V             :         : 5B        : N              

+VCCIO5B                      : M19       : power  :                   : 2.5V    : 5B        :                

+count[0]                     : M20       : output : 2.5 V             :         : 5B        : N              

+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5B        :                

+count[6]                     : M22       : output : 2.5 V             :         : 5B        : N              

+GXB_NC                       : N1        :        :                   :         : B0L       :                

+GXB_NC                       : N2        :        :                   :         : B0L       :                

+GND                          : N3        : gnd    :                   :         :           :                

+VCCE_GXBL                    : N4        : power  :                   : 1.1V    :           :                

+GND                          : N5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3A        :                

+GND                          : N7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 3B        :                

+VCC                          : N10       : power  :                   : 1.1V    :           :                

+GND                          : N11       : gnd    :                   :         :           :                

+VCC                          : N12       : power  :                   : 1.1V    :           :                

+GND                          : N13       : gnd    :                   :         :           :                

+VCC                          : N14       : power  :                   : 1.1V    :           :                

+GND                          : N15       : gnd    :                   :         :           :                

+enable                       : N16       : input  : 2.5 V             :         : 5B        : N              

+GND                          : N17       : gnd    :                   :         :           :                

+VCCPD5B                      : N18       : power  :                   : 2.5V    : 5B        :                

+count[2]                     : N19       : output : 2.5 V             :         : 5B        : N              

+count[4]                     : N20       : output : 2.5 V             :         : 5B        : N              

+count[1]                     : N21       : output : 2.5 V             :         : 5B        : N              

+GND                          : N22       : gnd    :                   :         :           :                

+GND                          : P1        : gnd    :                   :         :           :                

+GND                          : P2        : gnd    :                   :         :           :                

+VCCL_GXBL                    : P3        : power  :                   : 1.1V    :           :                

+GND                          : P4        : gnd    :                   :         :           :                

+TMS                          : P5        : input  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P9        :        :                   :         : 3B        :                

+GND                          : P10       : gnd    :                   :         :           :                

+VCC                          : P11       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P12       :        :                   :         : 3B        :                

+VCC                          : P13       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 4A        :                

+VCC                          : P15       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P18       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P19       :        :                   :         : 5A        :                

+VCCIO5A                      : P20       : power  :                   : 2.5V    : 5A        :                

+VCCPD5A                      : P21       : power  :                   : 2.5V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5A        :                

+GND                          : R1        :        :                   :         : B0L       :                

+GND                          : R2        :        :                   :         : B0L       :                

+GND                          : R3        : gnd    :                   :         :           :                

+nCSO, DATA4                  : R4        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 3A        :                

+VCCIO3B                      : R8        : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3B        :                

+GND                          : R13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5A        :                

+VCCIO5A                      : R18       : power  :                   : 2.5V    : 5A        :                

+VCCPGM                       : R19       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VREFB5AN0                    : R20       : power  :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5A        :                

+GND                          : T1        : gnd    :                   :         :           :                

+GND                          : T2        : gnd    :                   :         :           :                

+VCCH_GXBL                    : T3        : power  :                   : 2.5V    :           :                

+AS_DATA3, DATA3              : T4        :        :                   :         : 3A        :                

+VCCA_FPLL                    : T5        : power  :                   : 2.5V    :           :                

+VCCIO3A                      : T6        : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3B        :                

+VCCIO3B                      : T11       : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 5A        :                

+GND                          : T16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T19       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T20       :        :                   :         : 5A        :                

+GND                          : T21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T22       :        :                   :         : 5A        :                

+GXB_NC                       : U1        :        :                   :         : B0L       :                

+GXB_NC                       : U2        :        :                   :         : B0L       :                

+GND                          : U3        : gnd    :                   :         :           :                

+GND                          : U4        :        :                   :         : B0L       :                

+GND                          : U5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3A        :                

+GND                          : U9        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4A        :                

+VCCIO4A                      : U14       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U17       :        :                   :         : 4A        :                

+VCCA_FPLL                    : U18       : power  :                   : 2.5V    :           :                

+VCCIO4A                      : U19       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 4A        :                

+GND                          : V1        : gnd    :                   :         :           :                

+GND                          : V2        : gnd    :                   :         :           :                

+DCLK                         : V3        :        :                   :         : 3A        :                

+GND                          : V4        :        :                   :         : B0L       :                

+TCK                          : V5        : input  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3A        :                

+GND                          : V7        : gnd    :                   :         :           :                

+VCCPGM                       : V8        : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3B        :                

+DNU                          : V11       :        :                   :         :           :                

+GND                          : V12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                

+GND                          : V17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V19       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 4A        :                

+GND                          : V22       : gnd    :                   :         :           :                

+GND                          : W1        :        :                   :         : B0L       :                

+GND                          : W2        :        :                   :         : B0L       :                

+GND                          : W3        : gnd    :                   :         :           :                

+GND                          : W4        : gnd    :                   :         :           :                

+TDI                          : W5        : input  :                   :         : 3A        :                

+VCCPD3A                      : W6        : power  :                   : 2.5V    : 3A        :                

+VCC_AUX                      : W7        : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W9        :        :                   :         : 3A        :                

+VCCIO3B                      : W10       : power  :                   : 2.5V    : 3B        :                

+VCCPD3B4A                    : W11       : power  :                   : 2.5V    : 3B, 4A    :                

+VCCPD3B4A                    : W12       : power  :                   : 2.5V    : 3B, 4A    :                

+VCC_AUX                      : W13       : power  :                   : 2.5V    :           :                

+VCCPD3B4A                    : W14       : power  :                   : 2.5V    : 3B, 4A    :                

+VCCIO4A                      : W15       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                

+VCCPD3B4A                    : W17       : power  :                   : 2.5V    : 3B, 4A    :                

+VCC_AUX                      : W18       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                

+VCCIO4A                      : W20       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 4A        :                

+GND                          : Y1        : gnd    :                   :         :           :                

+GND                          : Y2        : gnd    :                   :         :           :                

+GXB_NC                       : Y3        :        :                   :         : B0L       :                

+GXB_NC                       : Y4        :        :                   :         : B0L       :                

+GND                          : Y5        : gnd    :                   :         :           :                

+DNU                          : Y6        :        :                   :         :           :                

+VREFB3AN0                    : Y7        : power  :                   :         : 3A        :                

+VCCIO3A                      : Y8        : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y11       :        :                   :         : 3B        :                

+VREFB3BN0                    : Y12       : power  :                   :         : 3B        :                

+VCCIO3B                      : Y13       : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y15       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                

+GND                          : Y18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y20       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 4A        :                

diff --git a/part_2/ex5/output_files/ex5.sld b/part_2/ex5/output_files/ex5.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.sld
@@ -0,0 +1 @@
+<sld_project_info/>

diff --git a/part_2/ex5/output_files/ex5.sof b/part_2/ex5/output_files/ex5.sof
new file mode 100755
index 0000000..808b964
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.sof
diff --git a/part_2/ex5/output_files/ex5.sta.summary b/part_2/ex5/output_files/ex5.sta.summary
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.sta.summary
diff --git a/part_2/ex5/pin_assignment.txt b/part_2/ex5/pin_assignment.txt
new file mode 100755
index 0000000..04a3a75
--- /dev/null
+++ b/part_2/ex5/pin_assignment.txt
@@ -0,0 +1,211 @@
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
\ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/ex5_run_msim_rtl_verilog.do b/part_2/ex5/simulation/modelsim/ex5_run_msim_rtl_verilog.do
new file mode 100755
index 0000000..cae582c
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/ex5_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on

+if {[file exists rtl_work]} {

+	vdel -lib rtl_work -all

+}

+vlib rtl_work

+vmap work rtl_work

+

+vlog -vlog01compat -work work +incdir+C:/New\ folder/verilog_files {C:/New folder/verilog_files/counter_8.v}

+

diff --git a/part_2/ex5/simulation/modelsim/modelsim.ini b/part_2/ex5/simulation/modelsim/modelsim.ini
new file mode 100755
index 0000000..3912feb
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/modelsim.ini
@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation

+;

+; All Rights Reserved.

+;

+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 

+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.

+;   

+

+[Library]

+others = $MODEL_TECH/../modelsim.ini

+

+; Altera Primitive libraries

+;

+; VHDL Section

+;

+;

+; Verilog Section

+;

+

+work = rtl_work

+[vcom]

+; VHDL93 variable selects language version as the default. 

+; Default is VHDL-2002.

+; Value of 0 or 1987 for VHDL-1987.

+; Value of 1 or 1993 for VHDL-1993.

+; Default or value of 2 or 2002 for VHDL-2002.

+; Default or value of 3 or 2008 for VHDL-2008.

+VHDL93 = 2002

+

+; Show source line containing error. Default is off.

+; Show_source = 1

+

+; Turn off unbound-component warnings. Default is on.

+; Show_Warning1 = 0

+

+; Turn off process-without-a-wait-statement warnings. Default is on.

+; Show_Warning2 = 0

+

+; Turn off null-range warnings. Default is on.

+; Show_Warning3 = 0

+

+; Turn off no-space-in-time-literal warnings. Default is on.

+; Show_Warning4 = 0

+

+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.

+; Show_Warning5 = 0

+

+; Turn off optimization for IEEE std_logic_1164 package. Default is on.

+; Optimize_1164 = 0

+

+; Turn on resolving of ambiguous function overloading in favor of the

+; "explicit" function declaration (not the one automatically created by

+; the compiler for each type declaration). Default is off.

+; The .ini file has Explicit enabled so that std_logic_signed/unsigned

+; will match the behavior of synthesis tools.

+Explicit = 1

+

+; Turn off acceleration of the VITAL packages. Default is to accelerate.

+; NoVital = 1

+

+; Turn off VITAL compliance checking. Default is checking on.

+; NoVitalCheck = 1

+

+; Ignore VITAL compliance checking errors. Default is to not ignore.

+; IgnoreVitalErrors = 1

+

+; Turn off VITAL compliance checking warnings. Default is to show warnings.

+; Show_VitalChecksWarnings = 0

+

+; Keep silent about case statement static warnings.

+; Default is to give a warning.

+; NoCaseStaticError = 1

+

+; Keep silent about warnings caused by aggregates that are not locally static.

+; Default is to give a warning.

+; NoOthersStaticError = 1

+

+; Turn off inclusion of debugging info within design units.

+; Default is to include debugging info.

+; NoDebug = 1

+

+; Turn off "Loading..." messages. Default is messages on.

+; Quiet = 1

+

+; Turn on some limited synthesis rule compliance checking. Checks only:

+;    -- signals used (read) by a process must be in the sensitivity list

+; CheckSynthesis = 1

+

+; Activate optimizations on expressions that do not involve signals,

+; waits, or function/procedure/task invocations. Default is off.

+; ScalarOpts = 1

+

+; Require the user to specify a configuration for all bindings,

+; and do not generate a compile time default binding for the

+; component. This will result in an elaboration error of

+; 'component not bound' if the user fails to do so. Avoids the rare

+; issue of a false dependency upon the unused default binding.

+; RequireConfigForAllDefaultBinding = 1

+

+; Inhibit range checking on subscripts of arrays. Range checking on

+; scalars defined with subtypes is inhibited by default.

+; NoIndexCheck = 1

+

+; Inhibit range checks on all (implicit and explicit) assignments to

+; scalar objects defined with subtypes.

+; NoRangeCheck = 1

+

+[vlog]

+

+; Turn off inclusion of debugging info within design units.

+; Default is to include debugging info.

+; NoDebug = 1

+

+; Turn off "loading..." messages. Default is messages on.

+; Quiet = 1

+

+; Turn on Verilog hazard checking (order-dependent accessing of global vars).

+; Default is off.

+; Hazard = 1

+

+; Turn on converting regular Verilog identifiers to uppercase. Allows case

+; insensitivity for module names. Default is no conversion.

+; UpCase = 1

+

+; Turn on incremental compilation of modules. Default is off.

+; Incremental = 1

+

+; Turns on lint-style checking.

+; Show_Lint = 1

+

+[vsim]

+; Simulator resolution

+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.

+Resolution = ps

+

+; User time unit for run commands

+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the

+; unit specified for Resolution. For example, if Resolution is 100ps,

+; then UserTimeUnit defaults to ps.

+; Should generally be set to default.

+UserTimeUnit = default

+

+; Default run length

+RunLength = 100

+

+; Maximum iterations that can be run without advancing simulation time

+IterationLimit = 5000

+

+; Directive to license manager:

+; vhdl          Immediately reserve a VHDL license

+; vlog          Immediately reserve a Verilog license

+; plus          Immediately reserve a VHDL and Verilog license

+; nomgc         Do not look for Mentor Graphics Licenses

+; nomti         Do not look for Model Technology Licenses

+; noqueue       Do not wait in the license queue when a license isn't available

+; viewsim	Try for viewer license but accept simulator license(s) instead

+;		of queuing for viewer license

+; License = plus

+

+; Stop the simulator after a VHDL/Verilog assertion message

+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal

+BreakOnAssertion = 3

+

+; Assertion Message Format

+; %S - Severity Level 

+; %R - Report Message

+; %T - Time of assertion

+; %D - Delta

+; %I - Instance or Region pathname (if available)

+; %% - print '%' character

+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

+

+; Assertion File - alternate file for storing VHDL/Verilog assertion messages

+; AssertFile = assert.log

+

+; Default radix for all windows and commands...

+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned

+DefaultRadix = symbolic

+

+; VSIM Startup command

+; Startup = do startup.do

+

+; File for saving command transcript

+TranscriptFile = transcript

+

+; File for saving command history

+; CommandHistory = cmdhist.log

+

+; Specify whether paths in simulator commands should be described

+; in VHDL or Verilog format.

+; For VHDL, PathSeparator = /

+; For Verilog, PathSeparator = .

+; Must not be the same character as DatasetSeparator.

+PathSeparator = /

+

+; Specify the dataset separator for fully rooted contexts.

+; The default is ':'. For example, sim:/top

+; Must not be the same character as PathSeparator.

+DatasetSeparator = :

+

+; Disable VHDL assertion messages

+; IgnoreNote = 1

+; IgnoreWarning = 1

+; IgnoreError = 1

+; IgnoreFailure = 1

+

+; Default force kind. May be freeze, drive, deposit, or default

+; or in other terms, fixed, wired, or charged.

+; A value of "default" will use the signal kind to determine the

+; force kind, drive for resolved signals, freeze for unresolved signals

+; DefaultForceKind = freeze

+

+; If zero, open files when elaborated; otherwise, open files on

+; first read or write.  Default is 0.

+; DelayFileOpen = 1

+

+; Control VHDL files opened for write.

+;   0 = Buffered, 1 = Unbuffered

+UnbufferedOutput = 0

+

+; Control the number of VHDL files open concurrently.

+; This number should always be less than the current ulimit

+; setting for max file descriptors.

+;   0 = unlimited

+ConcurrentFileLimit = 40

+

+; Control the number of hierarchical regions displayed as

+; part of a signal name shown in the Wave window.

+; A value of zero tells VSIM to display the full name.

+; The default is 0.

+; WaveSignalNameWidth = 0

+

+; Turn off warnings from the std_logic_arith, std_logic_unsigned

+; and std_logic_signed packages.

+; StdArithNoWarnings = 1

+

+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.

+; NumericStdNoWarnings = 1

+

+; Control the format of the (VHDL) FOR generate statement label

+; for each iteration.  Do not quote it.

+; The format string here must contain the conversion codes %s and %d,

+; in that order, and no other conversion codes.  The %s represents

+; the generate_label; the %d represents the generate parameter value

+; at a particular generate iteration (this is the position number if

+; the generate parameter is of an enumeration type).  Embedded whitespace

+; is allowed (but discouraged); leading and trailing whitespace is ignored.

+; Application of the format must result in a unique scope name over all

+; such names in the design so that name lookup can function properly.

+; GenerateFormat = %s__%d

+

+; Specify whether checkpoint files should be compressed.

+; The default is 1 (compressed).

+; CheckpointCompressMode = 0

+

+; List of dynamically loaded objects for Verilog PLI applications

+; Veriuser = veriuser.sl

+

+; Specify default options for the restart command. Options can be one

+; or more of: -force -nobreakpoint -nolist -nolog -nowave

+; DefaultRestartOptions = -force

+

+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs

+; (> 500 megabyte memory footprint). Default is disabled.

+; Specify number of megabytes to lock.

+; LockedMemory = 1000

+

+; Turn on (1) or off (0) WLF file compression.

+; The default is 1 (compress WLF file).

+; WLFCompress = 0

+

+; Specify whether to save all design hierarchy (1) in the WLF file

+; or only regions containing logged signals (0).

+; The default is 0 (save only regions with logged signals).

+; WLFSaveAllRegions = 1

+

+; WLF file time limit.  Limit WLF file by time, as closely as possible,

+; to the specified amount of simulation time.  When the limit is exceeded

+; the earliest times get truncated from the file.

+; If both time and size limits are specified the most restrictive is used.

+; UserTimeUnits are used if time units are not specified.

+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}

+; WLFTimeLimit = 0

+

+; WLF file size limit.  Limit WLF file size, as closely as possible,

+; to the specified number of megabytes.  If both time and size limits

+; are specified then the most restrictive is used.

+; The default is 0 (no limit).

+; WLFSizeLimit = 1000

+

+; Specify whether or not a WLF file should be deleted when the

+; simulation ends.  A value of 1 will cause the WLF file to be deleted.

+; The default is 0 (do not delete WLF file when simulation ends).

+; WLFDeleteOnQuit = 1

+

+; Automatic SDF compilation

+; Disables automatic compilation of SDF files in flows that support it.

+; Default is on, uncomment to turn off.

+; NoAutoSDFCompile = 1

+

+[lmc]

+

+[msg_system]

+; Change a message severity or suppress a message.

+; The format is: <msg directive> = <msg number>[,<msg number>...]

+; Examples:

+;   note = 3009

+;   warning = 3033

+;   error = 3010,3016

+;   fatal = 3016,3033

+;   suppress = 3009,3016,3043

+; The command verror <msg number> can be used to get the complete

+; description of a message.

+

+; Control transcripting of elaboration/runtime messages.

+; The default is to have messages appear in the transcript and 

+; recorded in the wlf file (messages that are recorded in the

+; wlf file can be viewed in the MsgViewer).  The other settings

+; are to send messages only to the transcript or only to the 

+; wlf file.  The valid values are

+;    both  {default}

+;    tran  {transcript only}

+;    wlf   {wlf file only}

+; msgmode = both

diff --git a/part_2/ex5/simulation/modelsim/msim_transcript b/part_2/ex5/simulation/modelsim/msim_transcript
new file mode 100755
index 0000000..966f386
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/msim_transcript
@@ -0,0 +1,102 @@
+# Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl 

+# Bad font spec for Editor textFont: t_fixed

+# do ex5_run_msim_rtl_verilog.do 

+# if {[file exists rtl_work]} {

+# 	vdel -lib rtl_work -all

+# }

+# vlib rtl_work

+# vmap work rtl_work

+# Copying C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini

+# Modifying modelsim.ini

+# ** Warning: Copied C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.

+#          Updated modelsim.ini.

+# 

+# vlog -vlog01compat -work work +incdir+C:/New\ folder/verilog_files {C:/New folder/verilog_files/counter_8.v}

+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012

+# -- Compiling module counter_8

+# 

+# Top level modules:

+# 	counter_8

+# 

+vsim -do ex5_run_msim_rtl_verilog.do -l msim_transcript -gui work.counter_8

+# vsim -do ex5_run_msim_rtl_verilog.do -l msim_transcript -gui work.counter_8 

+# Loading work.counter_8

+# do ex5_run_msim_rtl_verilog.do 

+# if {[file exists rtl_work]} {

+# 	vdel -lib rtl_work -all

+# }

+# vlib rtl_work

+# vmap work rtl_work

+# Modifying modelsim.ini

+# 

+# vlog -vlog01compat -work work +incdir+C:/New\ folder/verilog_files {C:/New folder/verilog_files/counter_8.v}

+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012

+# -- Compiling module counter_8

+# 

+# Top level modules:

+# 	counter_8

+# 

+add wave clock enable

+add wave -hexadecimal count

+force enable 1

+run 100ns

+force clock 0 0, 1 10ns -repeat 20ns

+run 100ns

+clear

+# invalid command name "clear"

+clr

+# invalid command name "clr"

+cls

+# 

+restart

+# Loading work.counter_8

+do ./tb_counter.do

+# Cannot open macro file: ./tb_counter.do

+restart

+do ./tb_counter.do

+step

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_info b/part_2/ex5/simulation/modelsim/rtl_work/_info
new file mode 100755
index 0000000..9a599cc
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_info
@@ -0,0 +1,25 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\simulation\modelsim
+vcounter_8
+!i10b 1
+!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
+Ia91@O_<g0BVIc?WTzTbB62
+Vdn7aTnOzPKdeZA;zmQ`Cl3
+Z1 dC:\New folder\simulation\modelsim
+w1479807538
+8C:/New folder/verilog_files/counter_8.v
+FC:/New folder/verilog_files/counter_8.v
+L0 3
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1479807676.024000
+!s107 C:/New folder/verilog_files/counter_8.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_vmake b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
new file mode 100755
index 0000000..2f7e729
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
new file mode 100755
index 0000000..ea67fd1
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
new file mode 100755
index 0000000..8019c2d
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
new file mode 100755
index 0000000..0dd84bc
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
@@ -0,0 +1,14 @@
+library verilog;
+use verilog.vl_types.all;
+entity counter_8 is
+    generic(
+        BIT_SZ          : integer := 8
+    );
+    port(
+        clock           : in     vl_logic;
+        enable          : in     vl_logic;
+        count           : out    vl_logic_vector
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
+end counter_8;
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
new file mode 100755
index 0000000..a7325bf
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm
new file mode 100755
index 0000000..3efd040
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm
diff --git a/part_2/ex5/simulation/modelsim/tb_counter b/part_2/ex5/simulation/modelsim/tb_counter
new file mode 100755
index 0000000..6256691
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/tb_counter
@@ -0,0 +1,9 @@
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
+run 1000
\ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/tb_counter.do b/part_2/ex5/simulation/modelsim/tb_counter.do
new file mode 100755
index 0000000..6256691
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/tb_counter.do
@@ -0,0 +1,9 @@
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
+run 1000
\ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/vsim.wlf b/part_2/ex5/simulation/modelsim/vsim.wlf
new file mode 100755
index 0000000..85c5422
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/vsim.wlf
diff --git a/part_2/ex5/verilog files/counter_8.v b/part_2/ex5/verilog files/counter_8.v
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/ex5/verilog files/counter_8.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog files/counter_8.v.bak b/part_2/ex5/verilog files/counter_8.v.bak
new file mode 100755
index 0000000..bcdbc6b
--- /dev/null
+++ b/part_2/ex5/verilog files/counter_8.v.bak
@@ -0,0 +1,22 @@
+timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog files/ex5.v b/part_2/ex5/verilog files/ex5.v
new file mode 100755
index 0000000..b4adca4
--- /dev/null
+++ b/part_2/ex5/verilog files/ex5.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module ex5(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog files/ex5.v.bak b/part_2/ex5/verilog files/ex5.v.bak
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/ex5/verilog files/ex5.v.bak
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog_files/counter_8.v b/part_2/ex5/verilog_files/counter_8.v
new file mode 100755
index 0000000..61bc861
--- /dev/null
+++ b/part_2/ex5/verilog_files/counter_8.v
@@ -0,0 +1,18 @@
+`timescale 1ns / 100ps

+

+module counter_8(clock,enable,count);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog_files/counter_8.v.bak b/part_2/ex5/verilog_files/counter_8.v.bak
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/ex5/verilog_files/counter_8.v.bak
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex6/c5_pin_model_dump.txt b/part_2/ex6/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_2/ex6/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2

+io_4iomodule_c5_index: 54gpio_index: 465

+io_4iomodule_c5_index: 33gpio_index: 6

+io_4iomodule_c5_index: 51gpio_index: 461

+io_4iomodule_c5_index: 27gpio_index: 10

+io_4iomodule_c5_index: 57gpio_index: 457

+io_4iomodule_c5_index: 34gpio_index: 14

+io_4iomodule_c5_index: 28gpio_index: 453

+io_4iomodule_c5_index: 26gpio_index: 19

+io_4iomodule_c5_index: 47gpio_index: 449

+io_4iomodule_c5_index: 29gpio_index: 22

+io_4iomodule_c5_index: 3gpio_index: 445

+io_4iomodule_c5_index: 16gpio_index: 27

+io_4iomodule_c5_index: 6gpio_index: 441

+io_4iomodule_c5_index: 50gpio_index: 30

+io_4iomodule_c5_index: 35gpio_index: 437

+io_4iomodule_c5_index: 7gpio_index: 35

+io_4iomodule_c5_index: 53gpio_index: 433

+io_4iomodule_c5_index: 12gpio_index: 38

+io_4iomodule_c5_index: 1gpio_index: 429

+io_4iomodule_c5_index: 22gpio_index: 43

+io_4iomodule_c5_index: 8gpio_index: 425

+io_4iomodule_c5_index: 20gpio_index: 46

+io_4iomodule_c5_index: 30gpio_index: 421

+io_4iomodule_c5_index: 2gpio_index: 51

+io_4iomodule_c5_index: 31gpio_index: 417

+io_4iomodule_c5_index: 39gpio_index: 54

+io_4iomodule_c5_index: 18gpio_index: 413

+io_4iomodule_c5_index: 10gpio_index: 59

+io_4iomodule_c5_index: 42gpio_index: 409

+io_4iomodule_c5_index: 5gpio_index: 62

+io_4iomodule_c5_index: 24gpio_index: 405

+io_4iomodule_c5_index: 37gpio_index: 67

+io_4iomodule_c5_index: 13gpio_index: 401

+io_4iomodule_c5_index: 0gpio_index: 70

+io_4iomodule_c5_index: 44gpio_index: 397

+io_4iomodule_c5_index: 38gpio_index: 75

+io_4iomodule_c5_index: 52gpio_index: 393

+io_4iomodule_c5_index: 32gpio_index: 78

+io_4iomodule_c5_index: 56gpio_index: 389

+io_4iomodule_a_index: 13gpio_index: 385

+io_4iomodule_c5_index: 4gpio_index: 83

+io_4iomodule_c5_index: 23gpio_index: 86

+io_4iomodule_a_index: 15gpio_index: 381

+io_4iomodule_a_index: 8gpio_index: 377

+io_4iomodule_c5_index: 46gpio_index: 91

+io_4iomodule_a_index: 5gpio_index: 373

+io_4iomodule_a_index: 11gpio_index: 369

+io_4iomodule_c5_index: 41gpio_index: 94

+io_4iomodule_a_index: 3gpio_index: 365

+io_4iomodule_c5_index: 25gpio_index: 99

+io_4iomodule_a_index: 7gpio_index: 361

+io_4iomodule_c5_index: 9gpio_index: 102

+io_4iomodule_a_index: 0gpio_index: 357

+io_4iomodule_c5_index: 14gpio_index: 107

+io_4iomodule_a_index: 12gpio_index: 353

+io_4iomodule_c5_index: 45gpio_index: 110

+io_4iomodule_c5_index: 17gpio_index: 115

+io_4iomodule_a_index: 4gpio_index: 349

+io_4iomodule_c5_index: 36gpio_index: 118

+io_4iomodule_a_index: 10gpio_index: 345

+io_4iomodule_a_index: 16gpio_index: 341

+io_4iomodule_c5_index: 15gpio_index: 123

+io_4iomodule_a_index: 14gpio_index: 337

+io_4iomodule_c5_index: 43gpio_index: 126

+io_4iomodule_c5_index: 19gpio_index: 131

+io_4iomodule_a_index: 1gpio_index: 333

+io_4iomodule_c5_index: 59gpio_index: 134

+io_4iomodule_a_index: 2gpio_index: 329

+io_4iomodule_a_index: 9gpio_index: 325

+io_4iomodule_c5_index: 48gpio_index: 139

+io_4iomodule_a_index: 6gpio_index: 321

+io_4iomodule_a_index: 17gpio_index: 317

+io_4iomodule_c5_index: 40gpio_index: 142

+io_4iomodule_c5_index: 11gpio_index: 147

+io_4iomodule_c5_index: 58gpio_index: 150

+io_4iomodule_c5_index: 21gpio_index: 155

+io_4iomodule_c5_index: 49gpio_index: 158

+io_4iomodule_h_c5_index: 0gpio_index: 161

+io_4iomodule_h_c5_index: 6gpio_index: 165

+io_4iomodule_h_c5_index: 10gpio_index: 169

+io_4iomodule_h_c5_index: 3gpio_index: 173

+io_4iomodule_h_c5_index: 8gpio_index: 176

+io_4iomodule_h_c5_index: 11gpio_index: 180

+io_4iomodule_h_c5_index: 7gpio_index: 184

+io_4iomodule_h_c5_index: 5gpio_index: 188

+io_4iomodule_h_c5_index: 1gpio_index: 192

+io_4iomodule_h_c5_index: 2gpio_index: 196

+io_4iomodule_h_c5_index: 9gpio_index: 200

+io_4iomodule_h_c5_index: 4gpio_index: 204

+io_4iomodule_h_index: 15gpio_index: 208

+io_4iomodule_h_index: 1gpio_index: 212

+io_4iomodule_h_index: 3gpio_index: 216

+io_4iomodule_h_index: 2gpio_index: 220

+io_4iomodule_h_index: 11gpio_index: 224

+io_4iomodule_vref_h_index: 1gpio_index: 228

+io_4iomodule_h_index: 20gpio_index: 231

+io_4iomodule_h_index: 8gpio_index: 235

+io_4iomodule_h_index: 6gpio_index: 239

+io_4iomodule_h_index: 10gpio_index: 243

+io_4iomodule_h_index: 23gpio_index: 247

+io_4iomodule_h_index: 7gpio_index: 251

+io_4iomodule_h_index: 22gpio_index: 255

+io_4iomodule_h_index: 5gpio_index: 259

+io_4iomodule_h_index: 24gpio_index: 263

+io_4iomodule_h_index: 0gpio_index: 267

+io_4iomodule_h_index: 13gpio_index: 271

+io_4iomodule_h_index: 21gpio_index: 275

+io_4iomodule_h_index: 16gpio_index: 279

+io_4iomodule_vref_h_index: 0gpio_index: 283

+io_4iomodule_h_index: 12gpio_index: 286

+io_4iomodule_h_index: 4gpio_index: 290

+io_4iomodule_h_index: 19gpio_index: 294

+io_4iomodule_h_index: 18gpio_index: 298

+io_4iomodule_h_index: 17gpio_index: 302

+io_4iomodule_h_index: 25gpio_index: 306

+io_4iomodule_h_index: 14gpio_index: 310

+io_4iomodule_h_index: 9gpio_index: 314

diff --git a/part_2/ex6/db/.cmp.kpt b/part_2/ex6/db/.cmp.kpt
new file mode 100755
index 0000000..38aa87b
--- /dev/null
+++ b/part_2/ex6/db/.cmp.kpt
diff --git a/part_2/ex6/db/ex6.(0).cnf.cdb b/part_2/ex6/db/ex6.(0).cnf.cdb
new file mode 100755
index 0000000..e44f8a1
--- /dev/null
+++ b/part_2/ex6/db/ex6.(0).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(0).cnf.hdb b/part_2/ex6/db/ex6.(0).cnf.hdb
new file mode 100755
index 0000000..de77324
--- /dev/null
+++ b/part_2/ex6/db/ex6.(0).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(1).cnf.cdb b/part_2/ex6/db/ex6.(1).cnf.cdb
new file mode 100755
index 0000000..4079d9b
--- /dev/null
+++ b/part_2/ex6/db/ex6.(1).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(1).cnf.hdb b/part_2/ex6/db/ex6.(1).cnf.hdb
new file mode 100755
index 0000000..39c74f3
--- /dev/null
+++ b/part_2/ex6/db/ex6.(1).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(2).cnf.cdb b/part_2/ex6/db/ex6.(2).cnf.cdb
new file mode 100755
index 0000000..c1f3aaf
--- /dev/null
+++ b/part_2/ex6/db/ex6.(2).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(2).cnf.hdb b/part_2/ex6/db/ex6.(2).cnf.hdb
new file mode 100755
index 0000000..ebbfbca
--- /dev/null
+++ b/part_2/ex6/db/ex6.(2).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(3).cnf.cdb b/part_2/ex6/db/ex6.(3).cnf.cdb
new file mode 100755
index 0000000..adf12ca
--- /dev/null
+++ b/part_2/ex6/db/ex6.(3).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(3).cnf.hdb b/part_2/ex6/db/ex6.(3).cnf.hdb
new file mode 100755
index 0000000..3d54105
--- /dev/null
+++ b/part_2/ex6/db/ex6.(3).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(4).cnf.cdb b/part_2/ex6/db/ex6.(4).cnf.cdb
new file mode 100755
index 0000000..9bd5391
--- /dev/null
+++ b/part_2/ex6/db/ex6.(4).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(4).cnf.hdb b/part_2/ex6/db/ex6.(4).cnf.hdb
new file mode 100755
index 0000000..88032e3
--- /dev/null
+++ b/part_2/ex6/db/ex6.(4).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(5).cnf.cdb b/part_2/ex6/db/ex6.(5).cnf.cdb
new file mode 100755
index 0000000..7e272ba
--- /dev/null
+++ b/part_2/ex6/db/ex6.(5).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(5).cnf.hdb b/part_2/ex6/db/ex6.(5).cnf.hdb
new file mode 100755
index 0000000..74844fd
--- /dev/null
+++ b/part_2/ex6/db/ex6.(5).cnf.hdb
diff --git a/part_2/ex6/db/ex6.ae.hdb b/part_2/ex6/db/ex6.ae.hdb
new file mode 100755
index 0000000..b847279
--- /dev/null
+++ b/part_2/ex6/db/ex6.ae.hdb
diff --git a/part_2/ex6/db/ex6.analyze_file.qmsg b/part_2/ex6/db/ex6.analyze_file.qmsg
new file mode 100755
index 0000000..44ee136
--- /dev/null
+++ b/part_2/ex6/db/ex6.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479812643770 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:04:03 2016 " "Processing started: Tue Nov 22 11:04:03 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 --analyze_file=\"C:/New folder/ex6/ex6.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 --analyze_file=\"C:/New folder/ex6/ex6.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479812643772 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479812644221 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479812644221 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "832 " "Peak virtual memory: 832 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:04:12 2016 " "Processing ended: Tue Nov 22 11:04:12 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479812652563 ""}

diff --git a/part_2/ex6/db/ex6.asm.qmsg b/part_2/ex6/db/ex6.asm.qmsg
new file mode 100755
index 0000000..f23ddd0
--- /dev/null
+++ b/part_2/ex6/db/ex6.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479815014816 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479815014818 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:43:34 2016 " "Processing started: Tue Nov 22 11:43:34 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479815014818 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479815014818 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479815014818 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479815015570 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479815020100 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:40 2016 " "Processing ended: Tue Nov 22 11:43:40 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479815020437 ""}

diff --git a/part_2/ex6/db/ex6.asm.rdb b/part_2/ex6/db/ex6.asm.rdb
new file mode 100755
index 0000000..0ef85b8
--- /dev/null
+++ b/part_2/ex6/db/ex6.asm.rdb
diff --git a/part_2/ex6/db/ex6.cbx.xml b/part_2/ex6/db/ex6.cbx.xml
new file mode 100755
index 0000000..8b16f5b
--- /dev/null
+++ b/part_2/ex6/db/ex6.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex6">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex6/db/ex6.cmp.ammdb b/part_2/ex6/db/ex6.cmp.ammdb
new file mode 100755
index 0000000..14e19ae
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.ammdb
diff --git a/part_2/ex6/db/ex6.cmp.bpm b/part_2/ex6/db/ex6.cmp.bpm
new file mode 100755
index 0000000..9fc0368
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.bpm
diff --git a/part_2/ex6/db/ex6.cmp.cdb b/part_2/ex6/db/ex6.cmp.cdb
new file mode 100755
index 0000000..f2b998b
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.cdb
diff --git a/part_2/ex6/db/ex6.cmp.hdb b/part_2/ex6/db/ex6.cmp.hdb
new file mode 100755
index 0000000..4c3f7f7
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.hdb
diff --git a/part_2/ex6/db/ex6.cmp.idb b/part_2/ex6/db/ex6.cmp.idb
new file mode 100755
index 0000000..08a2505
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.idb
diff --git a/part_2/ex6/db/ex6.cmp.logdb b/part_2/ex6/db/ex6.cmp.logdb
new file mode 100755
index 0000000..b26a4d2
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.logdb
@@ -0,0 +1,77 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,38;0;38;0;0;38;38;0;38;38;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,0;38;0;38;38;0;0;38;0;0;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex6/db/ex6.cmp.rdb b/part_2/ex6/db/ex6.cmp.rdb
new file mode 100755
index 0000000..2650c4f
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.rdb
diff --git a/part_2/ex6/db/ex6.cmp_merge.kpt b/part_2/ex6/db/ex6.cmp_merge.kpt
new file mode 100755
index 0000000..ee1a16d
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp_merge.kpt
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..5b115d6
--- /dev/null
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..dce4f6b
--- /dev/null
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex6/db/ex6.db_info b/part_2/ex6/db/ex6.db_info
new file mode 100755
index 0000000..d880372
--- /dev/null
+++ b/part_2/ex6/db/ex6.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Tue Nov 22 11:44:41 2016

diff --git a/part_2/ex6/db/ex6.fit.qmsg b/part_2/ex6/db/ex6.fit.qmsg
new file mode 100755
index 0000000..520ed32
--- /dev/null
+++ b/part_2/ex6/db/ex6.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479814984340 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479814984340 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479814984583 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814984640 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814984640 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479814985024 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479814985159 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479814995125 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479814995207 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479814995207 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814995207 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479814995209 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814995210 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814995210 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479814995211 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479814995211 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479814995211 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479814995211 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479814995211 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479814995211 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479814995247 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814995249 ""}

+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1479815000743 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815000745 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1479815000745 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479815000746 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479815000747 ""}

+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1479815000747 ""}

+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1479815000747 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479815000751 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479815000837 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815001449 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479815002122 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479815002452 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815002452 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479815003554 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479815008086 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479815008086 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479815008384 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479815008384 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479815008384 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815008388 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479815009521 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479815009559 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479815009945 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479815009945 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479815010330 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815012667 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479815012909 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479815012966 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 48 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 48 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2591 " "Peak virtual memory: 2591 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:33 2016 " "Processing ended: Tue Nov 22 11:43:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:53 " "Total CPU time (on all processors): 00:00:53" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479815013395 ""}

diff --git a/part_2/ex6/db/ex6.hier_info b/part_2/ex6/db/ex6.hier_info
new file mode 100755
index 0000000..df23cf1
--- /dev/null
+++ b/part_2/ex6/db/ex6.hier_info
@@ -0,0 +1,557 @@
+|ex6

+CLOCK_50 => CLOCK_50.IN1

+KEY[0] => _.IN1

+KEY[1] => _.IN1

+HEX0[0] <= hex_to_7seg:SEG0.port0

+HEX0[1] <= hex_to_7seg:SEG0.port0

+HEX0[2] <= hex_to_7seg:SEG0.port0

+HEX0[3] <= hex_to_7seg:SEG0.port0

+HEX0[4] <= hex_to_7seg:SEG0.port0

+HEX0[5] <= hex_to_7seg:SEG0.port0

+HEX0[6] <= hex_to_7seg:SEG0.port0

+HEX1[0] <= hex_to_7seg:SEG1.port0

+HEX1[1] <= hex_to_7seg:SEG1.port0

+HEX1[2] <= hex_to_7seg:SEG1.port0

+HEX1[3] <= hex_to_7seg:SEG1.port0

+HEX1[4] <= hex_to_7seg:SEG1.port0

+HEX1[5] <= hex_to_7seg:SEG1.port0

+HEX1[6] <= hex_to_7seg:SEG1.port0

+HEX2[0] <= hex_to_7seg:SEG2.port0

+HEX2[1] <= hex_to_7seg:SEG2.port0

+HEX2[2] <= hex_to_7seg:SEG2.port0

+HEX2[3] <= hex_to_7seg:SEG2.port0

+HEX2[4] <= hex_to_7seg:SEG2.port0

+HEX2[5] <= hex_to_7seg:SEG2.port0

+HEX2[6] <= hex_to_7seg:SEG2.port0

+HEX3[0] <= hex_to_7seg:SEG3.port0

+HEX3[1] <= hex_to_7seg:SEG3.port0

+HEX3[2] <= hex_to_7seg:SEG3.port0

+HEX3[3] <= hex_to_7seg:SEG3.port0

+HEX3[4] <= hex_to_7seg:SEG3.port0

+HEX3[5] <= hex_to_7seg:SEG3.port0

+HEX3[6] <= hex_to_7seg:SEG3.port0

+HEX4[0] <= hex_to_7seg:SEG4.port0

+HEX4[1] <= hex_to_7seg:SEG4.port0

+HEX4[2] <= hex_to_7seg:SEG4.port0

+HEX4[3] <= hex_to_7seg:SEG4.port0

+HEX4[4] <= hex_to_7seg:SEG4.port0

+HEX4[5] <= hex_to_7seg:SEG4.port0

+HEX4[6] <= hex_to_7seg:SEG4.port0

+

+

+|ex6|tick_50000:tck

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => count[12].CLK

+CLOCK_IN => count[13].CLK

+CLOCK_IN => count[14].CLK

+CLOCK_IN => count[15].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|counter_16:C

+clock => count[0]~reg0.CLK

+clock => count[1]~reg0.CLK

+clock => count[2]~reg0.CLK

+clock => count[3]~reg0.CLK

+clock => count[4]~reg0.CLK

+clock => count[5]~reg0.CLK

+clock => count[6]~reg0.CLK

+clock => count[7]~reg0.CLK

+clock => count[8]~reg0.CLK

+clock => count[9]~reg0.CLK

+clock => count[10]~reg0.CLK

+clock => count[11]~reg0.CLK

+clock => count[12]~reg0.CLK

+clock => count[13]~reg0.CLK

+clock => count[14]~reg0.CLK

+clock => count[15]~reg0.CLK

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+enable => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+reset => count.OUTPUTSELECT

+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B

+B[0] => BCD_0[0].DATAIN

+B[1] => w29[0].IN1

+B[2] => w25[0].IN1

+B[3] => w21[0].IN1

+B[4] => w17[0].IN1

+B[5] => w14[0].IN1

+B[6] => w11[0].IN1

+B[7] => w8[0].IN1

+B[8] => w6[0].IN1

+B[9] => w4[0].IN1

+B[10] => w2[0].IN1

+B[11] => w1[0].IN1

+B[12] => w1[1].IN1

+B[13] => w1[2].IN1

+B[14] => w1[3].IN1

+B[15] => w3[2].IN1

+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE

+BCD_0[1] <= add3_ge5:A29.port1

+BCD_0[2] <= add3_ge5:A29.port1

+BCD_0[3] <= add3_ge5:A29.port1

+BCD_1[0] <= add3_ge5:A29.port1

+BCD_1[1] <= add3_ge5:A28.port1

+BCD_1[2] <= add3_ge5:A28.port1

+BCD_1[3] <= add3_ge5:A28.port1

+BCD_2[0] <= add3_ge5:A28.port1

+BCD_2[1] <= add3_ge5:A27.port1

+BCD_2[2] <= add3_ge5:A27.port1

+BCD_2[3] <= add3_ge5:A27.port1

+BCD_3[0] <= add3_ge5:A27.port1

+BCD_3[1] <= add3_ge5:A26.port1

+BCD_3[2] <= add3_ge5:A26.port1

+BCD_3[3] <= add3_ge5:A26.port1

+BCD_4[0] <= add3_ge5:A26.port1

+BCD_4[1] <= add3_ge5:A22.port1

+BCD_4[2] <= add3_ge5:A18.port1

+BCD_4[3] <= <GND>

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A1

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A2

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A3

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A4

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A5

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A6

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A7

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A8

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A9

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A10

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A11

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A12

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A13

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A14

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A15

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A16

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A17

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A18

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A19

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A20

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A21

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A22

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A23

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A24

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A25

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A26

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A27

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A28

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|bin2bcd_16:B|add3_ge5:A29

+w[0] => Decoder0.IN3

+w[1] => Decoder0.IN2

+w[2] => Decoder0.IN1

+w[3] => Decoder0.IN0

+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex6|hex_to_7seg:SEG0

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex6|hex_to_7seg:SEG1

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex6|hex_to_7seg:SEG2

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex6|hex_to_7seg:SEG3

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex6|hex_to_7seg:SEG4

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

diff --git a/part_2/ex6/db/ex6.hif b/part_2/ex6/db/ex6.hif
new file mode 100755
index 0000000..922b5ce
--- /dev/null
+++ b/part_2/ex6/db/ex6.hif
diff --git a/part_2/ex6/db/ex6.lpc.html b/part_2/ex6/db/ex6.lpc.html
new file mode 100755
index 0000000..86c7f81
--- /dev/null
+++ b/part_2/ex6/db/ex6.lpc.html
@@ -0,0 +1,610 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+<TR >

+<TD >SEG4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG3</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG1</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A29</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A28</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A27</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A26</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A25</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A24</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A23</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A22</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A21</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A20</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A19</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A18</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A17</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A16</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A15</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A14</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A13</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A12</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A11</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A10</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A9</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A8</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A7</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A6</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A5</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A3</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B|A1</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >B</TD>

+<TD >16</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >20</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >C</TD>

+<TD >3</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >16</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >tck</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+</TABLE>

diff --git a/part_2/ex6/db/ex6.lpc.rdb b/part_2/ex6/db/ex6.lpc.rdb
new file mode 100755
index 0000000..0635761
--- /dev/null
+++ b/part_2/ex6/db/ex6.lpc.rdb
diff --git a/part_2/ex6/db/ex6.lpc.txt b/part_2/ex6/db/ex6.lpc.txt
new file mode 100755
index 0000000..f2fb5a2
--- /dev/null
+++ b/part_2/ex6/db/ex6.lpc.txt
@@ -0,0 +1,43 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A29     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A28     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A27     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A26     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A25     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A24     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A23     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A22     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A21     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A20     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A19     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A18     ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A17     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A16     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A15     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A14     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A13     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A12     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A11     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A10     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A9      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A8      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A7      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A6      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A5      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A4      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A3      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A2      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B|A1      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; B         ; 16    ; 1              ; 0            ; 1              ; 20     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; C         ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; tck       ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex6/db/ex6.map.ammdb b/part_2/ex6/db/ex6.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.ammdb
diff --git a/part_2/ex6/db/ex6.map.bpm b/part_2/ex6/db/ex6.map.bpm
new file mode 100755
index 0000000..bb857d4
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.bpm
diff --git a/part_2/ex6/db/ex6.map.cdb b/part_2/ex6/db/ex6.map.cdb
new file mode 100755
index 0000000..728c972
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.cdb
diff --git a/part_2/ex6/db/ex6.map.hdb b/part_2/ex6/db/ex6.map.hdb
new file mode 100755
index 0000000..774cef6
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.hdb
diff --git a/part_2/ex6/db/ex6.map.kpt b/part_2/ex6/db/ex6.map.kpt
new file mode 100755
index 0000000..4c58c4c
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.kpt
diff --git a/part_2/ex6/db/ex6.map.logdb b/part_2/ex6/db/ex6.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex6/db/ex6.map.qmsg b/part_2/ex6/db/ex6.map.qmsg
new file mode 100755
index 0000000..591b373
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.qmsg
@@ -0,0 +1,51 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479814972603 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814972605 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:42:52 2016 " "Processing started: Tue Nov 22 11:42:52 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814972605 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814972605 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814972605 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479814973084 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479814973084 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981494 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981494 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981496 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex6/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981498 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981498 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex6/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981500 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981500 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" {  } { { "ex6.v" "" { Text "C:/New folder/ex6/ex6.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981503 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981503 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex6/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981504 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981504 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479814981532 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" {  } { { "ex6.v" "tck" { Text "C:/New folder/ex6/ex6.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981539 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" {  } { { "ex6.v" "C" { Text "C:/New folder/ex6/ex6.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981540 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" {  } { { "ex6.v" "B" { Text "C:/New folder/ex6/ex6.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981541 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981542 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex6.v" "SEG0" { Text "C:/New folder/ex6/ex6.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981546 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479814982201 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.map.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814982507 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479814982587 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814982587 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479814982622 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479814982622 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479814982622 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479814982622 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "897 " "Peak virtual memory: 897 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:02 2016 " "Processing ended: Tue Nov 22 11:43:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814982634 ""}

diff --git a/part_2/ex6/db/ex6.map.rdb b/part_2/ex6/db/ex6.map.rdb
new file mode 100755
index 0000000..8b9a683
--- /dev/null
+++ b/part_2/ex6/db/ex6.map.rdb
diff --git a/part_2/ex6/db/ex6.map_bb.cdb b/part_2/ex6/db/ex6.map_bb.cdb
new file mode 100755
index 0000000..b4b07ef
--- /dev/null
+++ b/part_2/ex6/db/ex6.map_bb.cdb
diff --git a/part_2/ex6/db/ex6.map_bb.hdb b/part_2/ex6/db/ex6.map_bb.hdb
new file mode 100755
index 0000000..d29fcef
--- /dev/null
+++ b/part_2/ex6/db/ex6.map_bb.hdb
diff --git a/part_2/ex6/db/ex6.map_bb.logdb b/part_2/ex6/db/ex6.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex6/db/ex6.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex6/db/ex6.pre_map.cdb b/part_2/ex6/db/ex6.pre_map.cdb
new file mode 100755
index 0000000..b754542
--- /dev/null
+++ b/part_2/ex6/db/ex6.pre_map.cdb
diff --git a/part_2/ex6/db/ex6.pre_map.hdb b/part_2/ex6/db/ex6.pre_map.hdb
new file mode 100755
index 0000000..8df99d8
--- /dev/null
+++ b/part_2/ex6/db/ex6.pre_map.hdb
diff --git a/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb b/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..62aaf66
--- /dev/null
+++ b/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
diff --git a/part_2/ex6/db/ex6.routing.rdb b/part_2/ex6/db/ex6.routing.rdb
new file mode 100755
index 0000000..3790313
--- /dev/null
+++ b/part_2/ex6/db/ex6.routing.rdb
diff --git a/part_2/ex6/db/ex6.rtlv.hdb b/part_2/ex6/db/ex6.rtlv.hdb
new file mode 100755
index 0000000..ba7fb52
--- /dev/null
+++ b/part_2/ex6/db/ex6.rtlv.hdb
diff --git a/part_2/ex6/db/ex6.rtlv_sg.cdb b/part_2/ex6/db/ex6.rtlv_sg.cdb
new file mode 100755
index 0000000..ca2154e
--- /dev/null
+++ b/part_2/ex6/db/ex6.rtlv_sg.cdb
diff --git a/part_2/ex6/db/ex6.rtlv_sg_swap.cdb b/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..69494b0
--- /dev/null
+++ b/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
diff --git a/part_2/ex6/db/ex6.sld_design_entry.sci b/part_2/ex6/db/ex6.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex6/db/ex6.sld_design_entry.sci
diff --git a/part_2/ex6/db/ex6.sld_design_entry_dsc.sci b/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
diff --git a/part_2/ex6/db/ex6.smart_action.txt b/part_2/ex6/db/ex6.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex6/db/ex6.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex6/db/ex6.sta.qmsg b/part_2/ex6/db/ex6.sta.qmsg
new file mode 100755
index 0000000..c1af911
--- /dev/null
+++ b/part_2/ex6/db/ex6.sta.qmsg
@@ -0,0 +1,50 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479815021994 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479815021995 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:43:41 2016 " "Processing started: Tue Nov 22 11:43:41 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479815021995 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815021995 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815021995 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815022120 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022663 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022663 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022709 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022709 ""}

+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023227 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815023230 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023230 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023231 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023231 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023232 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023239 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.377 " "Worst-case setup slack is 15.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.377               0.000 CLOCK_50  " "   15.377               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023245 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.388 " "Worst-case hold slack is 0.388" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.388               0.000 CLOCK_50  " "    0.388               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023247 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023248 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023250 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.900 " "Worst-case minimum pulse width slack is 8.900" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.900               0.000 CLOCK_50  " "    8.900               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023251 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023260 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023294 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024133 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815024176 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024176 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024176 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.286 " "Worst-case setup slack is 15.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.286               0.000 CLOCK_50  " "   15.286               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024181 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.385 " "Worst-case hold slack is 0.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024183 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024184 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024186 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.899 " "Worst-case minimum pulse width slack is 8.899" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.899               0.000 CLOCK_50  " "    8.899               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024188 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815024196 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024344 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025047 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815025091 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025091 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025091 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.068 " "Worst-case setup slack is 17.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.068               0.000 CLOCK_50  " "   17.068               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025094 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.204               0.000 CLOCK_50  " "    0.204               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025095 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025097 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025098 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.836 " "Worst-case minimum pulse width slack is 8.836" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.836               0.000 CLOCK_50  " "    8.836               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025100 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815025108 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815025253 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025253 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025253 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.237 " "Worst-case setup slack is 17.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.237               0.000 CLOCK_50  " "   17.237               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025256 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.194               0.000 CLOCK_50  " "    0.194               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025258 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025259 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025261 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.806 " "Worst-case minimum pulse width slack is 8.806" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.806               0.000 CLOCK_50  " "    8.806               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025262 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026650 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026651 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1209 " "Peak virtual memory: 1209 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:46 2016 " "Processing ended: Tue Nov 22 11:43:46 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026692 ""}

diff --git a/part_2/ex6/db/ex6.sta.rdb b/part_2/ex6/db/ex6.sta.rdb
new file mode 100755
index 0000000..ee18610
--- /dev/null
+++ b/part_2/ex6/db/ex6.sta.rdb
diff --git a/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..8e7dea4
--- /dev/null
+++ b/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex6/db/ex6.tis_db_list.ddb b/part_2/ex6/db/ex6.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_2/ex6/db/ex6.tis_db_list.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..ff58cae
--- /dev/null
+++ b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..c8bf679
--- /dev/null
+++ b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..6e31afe
--- /dev/null
+++ b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..9ed3347
--- /dev/null
+++ b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex6/db/ex6.tmw_info b/part_2/ex6/db/ex6.tmw_info
new file mode 100755
index 0000000..7f48734
--- /dev/null
+++ b/part_2/ex6/db/ex6.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s

+start_analysis_synthesis:s-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s-start_full_compilation

+start_assembler:s-start_full_compilation

+start_timing_analyzer:s-start_full_compilation

diff --git a/part_2/ex6/db/ex6.vpr.ammdb b/part_2/ex6/db/ex6.vpr.ammdb
new file mode 100755
index 0000000..b265f17
--- /dev/null
+++ b/part_2/ex6/db/ex6.vpr.ammdb
diff --git a/part_2/ex6/db/ex6_partition_pins.json b/part_2/ex6/db/ex6_partition_pins.json
new file mode 100755
index 0000000..1a004e3
--- /dev/null
+++ b/part_2/ex6/db/ex6_partition_pins.json
@@ -0,0 +1,161 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "HEX0[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[6]",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[1]",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[0]",

+					"strict" : false

+				},

+				{

+					"name" : "CLOCK_50",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex6/db/prev_cmp_ex6.qmsg b/part_2/ex6/db/prev_cmp_ex6.qmsg
new file mode 100755
index 0000000..3ef48ff
--- /dev/null
+++ b/part_2/ex6/db/prev_cmp_ex6.qmsg
@@ -0,0 +1,160 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479814855590 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814855591 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:40:55 2016 " "Processing started: Tue Nov 22 11:40:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814855591 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814855591 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814855592 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479814856068 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479814856068 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864502 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864502 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864505 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864505 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex6/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864506 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864506 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex6/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864507 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864507 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" {  } { { "ex6.v" "" { Text "C:/New folder/ex6/ex6.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864509 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864509 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex6/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864512 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864512 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479814864538 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" {  } { { "ex6.v" "tck" { Text "C:/New folder/ex6/ex6.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864541 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" {  } { { "ex6.v" "C" { Text "C:/New folder/ex6/ex6.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864547 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" {  } { { "ex6.v" "B" { Text "C:/New folder/ex6/ex6.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864547 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864548 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex6.v" "SEG0" { Text "C:/New folder/ex6/ex6.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864552 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479814865202 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.map.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814865495 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479814865576 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814865576 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479814865610 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479814865610 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479814865610 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479814865610 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "899 " "Peak virtual memory: 899 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:05 2016 " "Processing ended: Tue Nov 22 11:41:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814865623 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1479814867084 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814867085 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:06 2016 " "Processing started: Tue Nov 22 11:41:06 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814867085 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1479814867085 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1479814867085 ""}

+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1479814867201 ""}

+{ "Info" "0" "" "Project  = ex6" {  } {  } 0 0 "Project  = ex6" 0 0 "Fitter" 0 0 1479814867202 ""}

+{ "Info" "0" "" "Revision = ex6" {  } {  } 0 0 "Revision = ex6" 0 0 "Fitter" 0 0 1479814867202 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479814867313 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479814867314 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479814867575 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814867638 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814867638 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479814868022 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479814868156 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479814878204 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479814878285 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479814878285 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814878285 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479814878288 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814878288 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814878288 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479814878289 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479814878289 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479814878289 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479814878289 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479814878290 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479814878290 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479814878324 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814878326 ""}

+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1479814883778 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814883780 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1479814883780 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479814883781 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479814883781 ""}

+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1479814883782 ""}

+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1479814883782 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479814883786 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479814883871 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814884487 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479814885162 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479814885489 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814885489 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479814886599 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479814891026 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479814891026 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479814891312 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479814891312 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479814891312 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814891315 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479814892475 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479814892512 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479814892890 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479814892891 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479814893257 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814895619 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479814895860 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479814895916 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 48 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 48 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2589 " "Peak virtual memory: 2589 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:36 2016 " "Processing ended: Tue Nov 22 11:41:36 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:53 " "Total CPU time (on all processors): 00:00:53" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479814896340 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1479814897635 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814897638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:37 2016 " "Processing started: Tue Nov 22 11:41:37 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814897638 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479814897638 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479814897638 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479814898389 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479814902980 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:43 2016 " "Processing ended: Tue Nov 22 11:41:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479814903314 ""}

+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1479814903979 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1479814904803 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814904804 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:44 2016 " "Processing started: Tue Nov 22 11:41:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814904804 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814904804 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814904804 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814904930 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905472 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905472 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905519 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905519 ""}

+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906037 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814906040 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906040 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906041 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906041 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906042 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906049 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.377 " "Worst-case setup slack is 15.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.377               0.000 CLOCK_50  " "   15.377               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906055 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.388 " "Worst-case hold slack is 0.388" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.388               0.000 CLOCK_50  " "    0.388               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906057 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906058 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906060 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.900 " "Worst-case minimum pulse width slack is 8.900" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.900               0.000 CLOCK_50  " "    8.900               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906061 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906070 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906104 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906927 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814906969 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906969 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906969 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.286 " "Worst-case setup slack is 15.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.286               0.000 CLOCK_50  " "   15.286               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906974 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.385 " "Worst-case hold slack is 0.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906976 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906977 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906979 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.899 " "Worst-case minimum pulse width slack is 8.899" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.899               0.000 CLOCK_50  " "    8.899               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906980 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906989 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907132 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907832 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814907877 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907877 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907877 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.068 " "Worst-case setup slack is 17.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.068               0.000 CLOCK_50  " "   17.068               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907880 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.204               0.000 CLOCK_50  " "    0.204               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907883 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907885 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907887 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.836 " "Worst-case minimum pulse width slack is 8.836" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.836               0.000 CLOCK_50  " "    8.836               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907888 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814907897 ""}

+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814908038 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908038 "|ex6|tick_50000:tck|CLK_OUT"}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908039 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.237 " "Worst-case setup slack is 17.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.237               0.000 CLOCK_50  " "   17.237               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908041 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.194               0.000 CLOCK_50  " "    0.194               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908043 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908045 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908046 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.806 " "Worst-case minimum pulse width slack is 8.806" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.806               0.000 CLOCK_50  " "    8.806               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908048 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909430 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909431 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1207 " "Peak virtual memory: 1207 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:49 2016 " "Processing ended: Tue Nov 22 11:41:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909471 ""}

+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 55 s " "Quartus Prime Full Compilation was successful. 0 errors, 55 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814910195 ""}

diff --git a/part_2/ex6/ex6.qpf b/part_2/ex6/ex6.qpf
new file mode 100755
index 0000000..cefe719
--- /dev/null
+++ b/part_2/ex6/ex6.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 09:55:22  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "16.0"

+DATE = "09:55:22  November 22, 2016"

+

+# Revisions

+

+PROJECT_REVISION = "ex6"

diff --git a/part_2/ex6/ex6.qsf b/part_2/ex6/ex6.qsf
new file mode 100755
index 0000000..1352d53
--- /dev/null
+++ b/part_2/ex6/ex6.qsf
@@ -0,0 +1,273 @@
+#============================================================

+# CLOCK

+#============================================================

+set_location_assignment PIN_AF14 -to CLOCK_50

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50

+

+#============================================================

+# Add-on Card Interface Pins

+#============================================================

+set_location_assignment PIN_AJ20 -to PWM_OUT

+set_location_assignment PIN_AK21 -to DAC_LD

+set_location_assignment PIN_AD20 -to DAC_CS

+set_location_assignment PIN_AF20 -to DAC_SCK

+set_location_assignment PIN_AF21 -to ADC_SCK

+set_location_assignment PIN_AG21 -to ADC_SDI

+set_location_assignment PIN_AG20 -to ADC_CS

+set_location_assignment PIN_AG18 -to DAC_SDI

+set_location_assignment PIN_AJ21 -to ADC_SDO

+set_location_assignment PIN_Y17 -to OLED_CS

+set_location_assignment PIN_Y18 -to OLED_RST

+set_location_assignment PIN_AK18 -to OLED_DC

+set_location_assignment PIN_AJ19 -to OLED_CLK

+set_location_assignment PIN_AJ16 -to OLED_DATA

+

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO

+

+

+#============================================================

+# HEX0

+#============================================================

+set_location_assignment PIN_AE26 -to HEX0[0]

+set_location_assignment PIN_AE27 -to HEX0[1]

+set_location_assignment PIN_AE28 -to HEX0[2]

+set_location_assignment PIN_AG27 -to HEX0[3]

+set_location_assignment PIN_AF28 -to HEX0[4]

+set_location_assignment PIN_AG28 -to HEX0[5]

+set_location_assignment PIN_AH28 -to HEX0[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]

+

+#============================================================

+# HEX1

+#============================================================

+set_location_assignment PIN_AJ29 -to HEX1[0]

+set_location_assignment PIN_AH29 -to HEX1[1]

+set_location_assignment PIN_AH30 -to HEX1[2]

+set_location_assignment PIN_AG30 -to HEX1[3]

+set_location_assignment PIN_AF29 -to HEX1[4]

+set_location_assignment PIN_AF30 -to HEX1[5]

+set_location_assignment PIN_AD27 -to HEX1[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]

+

+#============================================================

+# HEX2

+#============================================================

+set_location_assignment PIN_AB23 -to HEX2[0]

+set_location_assignment PIN_AE29 -to HEX2[1]

+set_location_assignment PIN_AD29 -to HEX2[2]

+set_location_assignment PIN_AC28 -to HEX2[3]

+set_location_assignment PIN_AD30 -to HEX2[4]

+set_location_assignment PIN_AC29 -to HEX2[5]

+set_location_assignment PIN_AC30 -to HEX2[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]

+

+#============================================================

+# HEX3

+#============================================================

+set_location_assignment PIN_AD26 -to HEX3[0]

+set_location_assignment PIN_AC27 -to HEX3[1]

+set_location_assignment PIN_AD25 -to HEX3[2]

+set_location_assignment PIN_AC25 -to HEX3[3]

+set_location_assignment PIN_AB28 -to HEX3[4]

+set_location_assignment PIN_AB25 -to HEX3[5]

+set_location_assignment PIN_AB22 -to HEX3[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]

+

+#============================================================

+# HEX4

+#============================================================

+set_location_assignment PIN_AA24 -to HEX4[0]

+set_location_assignment PIN_Y23 -to HEX4[1]

+set_location_assignment PIN_Y24 -to HEX4[2]

+set_location_assignment PIN_W22 -to HEX4[3]

+set_location_assignment PIN_W24 -to HEX4[4]

+set_location_assignment PIN_V23 -to HEX4[5]

+set_location_assignment PIN_W25 -to HEX4[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]

+

+#============================================================

+# HEX5

+#============================================================

+set_location_assignment PIN_V25 -to HEX5[0]

+set_location_assignment PIN_AA28 -to HEX5[1]

+set_location_assignment PIN_Y27 -to HEX5[2]

+set_location_assignment PIN_AB27 -to HEX5[3]

+set_location_assignment PIN_AB26 -to HEX5[4]

+set_location_assignment PIN_AA26 -to HEX5[5]

+set_location_assignment PIN_AA25 -to HEX5[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]

+

+#============================================================

+# KEY

+#============================================================

+set_location_assignment PIN_AA14 -to KEY[0]

+set_location_assignment PIN_AA15 -to KEY[1]

+set_location_assignment PIN_W15 -to KEY[2]

+set_location_assignment PIN_Y16 -to KEY[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]

+

+#============================================================

+# LEDR

+#============================================================

+set_location_assignment PIN_V16 -to LEDR[0]

+set_location_assignment PIN_W16 -to LEDR[1]

+set_location_assignment PIN_V17 -to LEDR[2]

+set_location_assignment PIN_V18 -to LEDR[3]

+set_location_assignment PIN_W17 -to LEDR[4]

+set_location_assignment PIN_W19 -to LEDR[5]

+set_location_assignment PIN_Y19 -to LEDR[6]

+set_location_assignment PIN_W20 -to LEDR[7]

+set_location_assignment PIN_W21 -to LEDR[8]

+set_location_assignment PIN_Y21 -to LEDR[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]

+

+#============================================================

+# SW

+#============================================================

+set_location_assignment PIN_AB12 -to SW[0]

+set_location_assignment PIN_AC12 -to SW[1]

+set_location_assignment PIN_AF9 -to SW[2]

+set_location_assignment PIN_AF10 -to SW[3]

+set_location_assignment PIN_AD11 -to SW[4]

+set_location_assignment PIN_AD12 -to SW[5]

+set_location_assignment PIN_AE11 -to SW[6]

+set_location_assignment PIN_AC9 -to SW[7]

+set_location_assignment PIN_AD10 -to SW[8]

+set_location_assignment PIN_AE12 -to SW[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]

+

+#============================================================

+# End of pin and io_standard assignments

+#============================================================# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 09:55:22  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex6_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex6

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:55:22  NOVEMBER 22, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE ex6.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_global_assignment -name SDC_FILE ex6.sdc

+set_global_assignment -name CDF_FILE output_files/Chain2.cdf

+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex6/ex6.qsf.bak b/part_2/ex6/ex6.qsf.bak
new file mode 100755
index 0000000..e5c9659
--- /dev/null
+++ b/part_2/ex6/ex6.qsf.bak
@@ -0,0 +1,60 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 09:55:22  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex6_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex6

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:55:22  NOVEMBER 22, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE ex6.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex6/ex6.qws b/part_2/ex6/ex6.qws
new file mode 100755
index 0000000..63563b7
--- /dev/null
+++ b/part_2/ex6/ex6.qws
diff --git a/part_2/ex6/ex6.sdc b/part_2/ex6/ex6.sdc
new file mode 100755
index 0000000..f902c4a
--- /dev/null
+++ b/part_2/ex6/ex6.sdc
@@ -0,0 +1 @@
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
\ No newline at end of file
diff --git a/part_2/ex6/ex6.sdc.bak b/part_2/ex6/ex6.sdc.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex6/ex6.sdc.bak
diff --git a/part_2/ex6/ex6.v b/part_2/ex6/ex6.v
new file mode 100755
index 0000000..a891bd6
--- /dev/null
+++ b/part_2/ex6/ex6.v
@@ -0,0 +1,38 @@
+module ex6(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4);

+	

+	input CLOCK_50;

+	input [1:0] KEY;

+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;

+	

+	wire [15:0] count;

+	wire tick;

+	wire [3:0] b0, b1, b2, b3, b4;

+	

+	tick_50000 tck(CLOCK_50, tick);

+	

+	counter_16 C(tick, ~KEY[0], ~KEY[1], count);

+	

+	bin2bcd_16 B(count, b0, b1, b2, b3, b4);

+	

+	hex_to_7seg SEG0(HEX0, b0);

+	hex_to_7seg SEG1(HEX1, b1);

+	hex_to_7seg SEG2(HEX2, b2);

+	hex_to_7seg SEG3(HEX3, b3);

+	hex_to_7seg SEG4(HEX4, b4);

+	

+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+

+	

+	

diff --git a/part_2/ex6/ex6.v.bak b/part_2/ex6/ex6.v.bak
new file mode 100755
index 0000000..8b708a8
--- /dev/null
+++ b/part_2/ex6/ex6.v.bak
@@ -0,0 +1,20 @@
+module ex6(clock, KEY, HEX0, HEX1, HEX2, HEX3, HEX4);

+	

+	input clock;

+	input [1:0] KEY;

+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;

+	

+	wire [15:0] count;

+	wire [3:0] b0, b1, b2, b3, b4;

+	

+	counter_16(clock, KEY[0], KEY[1], count);

+	bin2bcd_16(count, b0, b1, b2, b3, b4);

+	hex_to_7seg(HEX0, b0);

+	hex_to_7seg(HEX1, b1);

+	hex_to_7seg(HEX2, b2);

+	hex_to_7seg(HEX3, b3);

+	hex_to_7seg(HEX4, b4);

+	

+endmodule

+	

+	

diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info b/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
new file mode 100755
index 0000000..41f92fa
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Tue Nov 22 10:11:38 2016

diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
new file mode 100755
index 0000000..ab3bea2
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
new file mode 100755
index 0000000..dae0e0b
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.dfp b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.dfp
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..21a86b2
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..8907c68
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.sig b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
new file mode 100755
index 0000000..26f78b7
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..cd9fac3
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
new file mode 100755
index 0000000..3b77930
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
new file mode 100755
index 0000000..10da539
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..5b4ee25
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hb_info b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..0cd555d
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.sig b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
new file mode 100755
index 0000000..9c8db47
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
new file mode 100755
index 0000000..722be46
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb
new file mode 100755
index 0000000..1f45a5a
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb
new file mode 100755
index 0000000..6e951b6
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb
new file mode 100755
index 0000000..c78c5d1
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb
new file mode 100755
index 0000000..1f45a5a
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb
new file mode 100755
index 0000000..d995b24
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb
new file mode 100755
index 0000000..450e420
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb
new file mode 100755
index 0000000..3b77930
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..5b4ee25
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..0cd555d
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb
new file mode 100755
index 0000000..9c8db47
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.kpt b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.kpt
new file mode 100755
index 0000000..722be46
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.kpt
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
new file mode 100755
index 0000000..88368d0
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
new file mode 100755
index 0000000..971696d
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
diff --git a/part_2/ex6/output_files/Chain2.cdf b/part_2/ex6/output_files/Chain2.cdf
new file mode 100755
index 0000000..005e0d3
--- /dev/null
+++ b/part_2/ex6/output_files/Chain2.cdf
@@ -0,0 +1,15 @@
+/* Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition */

+JedecChain;

+	FileRevision(JESD32A);

+	DefaultMfr(6E);

+

+	P ActionCode(Ign)

+		Device PartName(5CSEMA5F31) MfrSpec(OpMask(0) FullPath("C:/New folder/ex6/output_files/ex6.sof"));

+	P ActionCode(Cfg)

+		Device PartName(5CSEMA5F31) Path("C:/New folder/ex6/output_files/") File("ex6.sof") MfrSpec(OpMask(1));

+

+ChainEnd;

+

+AlteraBegin;

+	ChainType(JTAG);

+AlteraEnd;

diff --git a/part_2/ex6/output_files/ex6.asm.rpt b/part_2/ex6/output_files/ex6.asm.rpt
new file mode 100755
index 0000000..c99b821
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex6

+Tue Nov 22 11:43:40 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Assembler Summary

+  3. Assembler Settings

+  4. Assembler Generated Files

+  5. Assembler Device Options: C:/New folder/ex6/output_files/ex6.sof

+  6. Assembler Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------+

+; Assembler Summary                                             ;

++-----------------------+---------------------------------------+

+; Assembler Status      ; Successful - Tue Nov 22 11:43:40 2016 ;

+; Revision Name         ; ex6                                   ;

+; Top-level Entity Name ; ex6                                   ;

+; Family                ; Cyclone V                             ;

+; Device                ; 5CSEMA5F31C6                          ;

++-----------------------+---------------------------------------+

+

+

++----------------------------------+

+; Assembler Settings               ;

++--------+---------+---------------+

+; Option ; Setting ; Default Value ;

++--------+---------+---------------+

+

+

++----------------------------------------+

+; Assembler Generated Files              ;

++----------------------------------------+

+; File Name                              ;

++----------------------------------------+

+; C:/New folder/ex6/output_files/ex6.sof ;

++----------------------------------------+

+

+

++------------------------------------------------------------------+

+; Assembler Device Options: C:/New folder/ex6/output_files/ex6.sof ;

++----------------+-------------------------------------------------+

+; Option         ; Setting                                         ;

++----------------+-------------------------------------------------+

+; Device         ; 5CSEMA5F31C6                                    ;

+; JTAG usercode  ; 0x00B27652                                      ;

+; Checksum       ; 0x00B27652                                      ;

++----------------+-------------------------------------------------+

+

+

++--------------------+

+; Assembler Messages ;

++--------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Assembler

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Tue Nov 22 11:43:34 2016

+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (115030): Assembler is generating device programming files

+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 893 megabytes

+    Info: Processing ended: Tue Nov 22 11:43:40 2016

+    Info: Elapsed time: 00:00:06

+    Info: Total CPU time (on all processors): 00:00:06

+

+

diff --git a/part_2/ex6/output_files/ex6.done b/part_2/ex6/output_files/ex6.done
new file mode 100755
index 0000000..33dea98
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.done
@@ -0,0 +1 @@
+Tue Nov 22 11:43:47 2016

diff --git a/part_2/ex6/output_files/ex6.fit.rpt b/part_2/ex6/output_files/ex6.fit.rpt
new file mode 100755
index 0000000..b0a72b2
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.fit.rpt
@@ -0,0 +1,2034 @@
+Fitter report for ex6

+Tue Nov 22 11:43:32 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Fitter Summary

+  3. Fitter Settings

+  4. Parallel Compilation

+  5. I/O Assignment Warnings

+  6. Fitter Netlist Optimizations

+  7. Ignored Assignments

+  8. Incremental Compilation Preservation Summary

+  9. Incremental Compilation Partition Settings

+ 10. Incremental Compilation Placement Preservation

+ 11. Pin-Out File

+ 12. Fitter Resource Usage Summary

+ 13. Fitter Partition Statistics

+ 14. Input Pins

+ 15. Output Pins

+ 16. I/O Bank Usage

+ 17. All Package Pins

+ 18. Fitter Resource Utilization by Entity

+ 19. Delay Chain Summary

+ 20. Pad To Core Delay Chain Fanout

+ 21. Control Signals

+ 22. Global & Other Fast Signals

+ 23. Routing Usage Summary

+ 24. I/O Rules Summary

+ 25. I/O Rules Details

+ 26. I/O Rules Matrix

+ 27. Fitter Device Options

+ 28. Operating Settings and Conditions

+ 29. Estimated Delay Added for Hold Timing Summary

+ 30. Estimated Delay Added for Hold Timing Details

+ 31. Fitter Messages

+ 32. Fitter Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Fitter Summary                                                                    ;

++---------------------------------+-------------------------------------------------+

+; Fitter Status                   ; Successful - Tue Nov 22 11:43:32 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex6                                             ;

+; Top-level Entity Name           ; ex6                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 99 / 32,070 ( < 1 % )                           ;

+; Total registers                 ; 35                                              ;

+; Total pins                      ; 38 / 457 ( 8 % )                                ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Settings                                                                                                                                            ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Option                                                                     ; Setting                               ; Default Value                         ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;

+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;

+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;

+; Use smart compilation                                                      ; Off                                   ; Off                                   ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;

+; Enable compact report table                                                ; Off                                   ; Off                                   ;

+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;

+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;

+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;

+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;

+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;

+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;

+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;

+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;

+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;

+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;

+; SSN Optimization                                                           ; Off                                   ; Off                                   ;

+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;

+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;

+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;

+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;

+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;

+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;

+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;

+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;

+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;

+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;

+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;

+; Auto Delay Chains                                                          ; On                                    ; On                                    ;

+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;

+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;

+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;

+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;

+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;

+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;

+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;

+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;

+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;

+; Auto Global Clock                                                          ; On                                    ; On                                    ;

+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;

+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;

+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;

+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;

+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;

+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;

+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;

+; Clamping Diode                                                             ; Off                                   ; Off                                   ;

+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;

+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.01        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.5%      ;

+;     Processor 3            ;   0.5%      ;

+;     Processor 4            ;   0.4%      ;

++----------------------------+-------------+

+

+

++-------------------------------------------------+

+; I/O Assignment Warnings                         ;

++----------+--------------------------------------+

+; Pin Name ; Reason                               ;

++----------+--------------------------------------+

+; HEX0[0]  ; Missing drive strength and slew rate ;

+; HEX0[1]  ; Missing drive strength and slew rate ;

+; HEX0[2]  ; Missing drive strength and slew rate ;

+; HEX0[3]  ; Missing drive strength and slew rate ;

+; HEX0[4]  ; Missing drive strength and slew rate ;

+; HEX0[5]  ; Missing drive strength and slew rate ;

+; HEX0[6]  ; Missing drive strength and slew rate ;

+; HEX1[0]  ; Missing drive strength and slew rate ;

+; HEX1[1]  ; Missing drive strength and slew rate ;

+; HEX1[2]  ; Missing drive strength and slew rate ;

+; HEX1[3]  ; Missing drive strength and slew rate ;

+; HEX1[4]  ; Missing drive strength and slew rate ;

+; HEX1[5]  ; Missing drive strength and slew rate ;

+; HEX1[6]  ; Missing drive strength and slew rate ;

+; HEX2[0]  ; Missing drive strength and slew rate ;

+; HEX2[1]  ; Missing drive strength and slew rate ;

+; HEX2[2]  ; Missing drive strength and slew rate ;

+; HEX2[3]  ; Missing drive strength and slew rate ;

+; HEX2[4]  ; Missing drive strength and slew rate ;

+; HEX2[5]  ; Missing drive strength and slew rate ;

+; HEX2[6]  ; Missing drive strength and slew rate ;

+; HEX3[0]  ; Missing drive strength and slew rate ;

+; HEX3[1]  ; Missing drive strength and slew rate ;

+; HEX3[2]  ; Missing drive strength and slew rate ;

+; HEX3[3]  ; Missing drive strength and slew rate ;

+; HEX3[4]  ; Missing drive strength and slew rate ;

+; HEX3[5]  ; Missing drive strength and slew rate ;

+; HEX3[6]  ; Missing drive strength and slew rate ;

+; HEX4[0]  ; Missing drive strength and slew rate ;

+; HEX4[1]  ; Missing drive strength and slew rate ;

+; HEX4[2]  ; Missing drive strength and slew rate ;

+; HEX4[3]  ; Missing drive strength and slew rate ;

+; HEX4[4]  ; Missing drive strength and slew rate ;

+; HEX4[5]  ; Missing drive strength and slew rate ;

+; HEX4[6]  ; Missing drive strength and slew rate ;

++----------+--------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Netlist Optimizations                                                                                                                                                                                                      ;

++-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+

+; Node                    ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                  ; Destination Port ; Destination Port Name ;

++-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+

+; CLOCK_50~inputCLKENA0   ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                   ;                  ;                       ;

+; tick_50000:tck|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:tck|count[1]~DUPLICATE ;                  ;                       ;

+; tick_50000:tck|count[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:tck|count[5]~DUPLICATE ;                  ;                       ;

++-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+

+

+

++--------------------------------------------------------------------------------------------+

+; Ignored Assignments                                                                        ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;

+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;

+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;

+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;

+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex6            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;

++--------------+----------------+--------------+------------+---------------+----------------+

+

+

++--------------------------------------------------------------------------------------------------+

+; Incremental Compilation Preservation Summary                                                     ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Placement (by node) ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 )         ; 0.00 % ( 0 / 298 )       ;

+;     -- Achieved     ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 )         ; 0.00 % ( 0 / 298 )       ;

+;                     ;                    ;                            ;                          ;

+; Routing (by net)    ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

++---------------------+--------------------+----------------------------+--------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Partition Settings                                                                                                                                             ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;

+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Placement Preservation                                                                                     ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Top                            ; 0.00 % ( 0 / 298 )    ; N/A                     ; Source File       ; N/A                 ;       ;

+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+

+

++--------------+

+; Pin-Out File ;

++--------------+

+The pin-out file can be found in C:/New folder/ex6/output_files/ex6.pin.

+

+

++------------------------------------------------------------------------------------------+

+; Fitter Resource Usage Summary                                                            ;

++-------------------------------------------------------------+--------------------+-------+

+; Resource                                                    ; Usage              ; %     ;

++-------------------------------------------------------------+--------------------+-------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32,070        ; < 1 % ;

+; ALMs needed [=A-B+C]                                        ; 99                 ;       ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 100 / 32,070       ; < 1 % ;

+;         [a] ALMs used for LUT logic and registers           ; 16                 ;       ;

+;         [b] ALMs used for LUT logic                         ; 83                 ;       ;

+;         [c] ALMs used for registers                         ; 1                  ;       ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32,070         ; < 1 % ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;

+;         [a] Due to location constrained logic               ; 0                  ;       ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;

+;         [c] Due to LAB input limits                         ; 0                  ;       ;

+;         [d] Due to virtual I/Os                             ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Difficulty packing design                                   ; Low                ;       ;

+;                                                             ;                    ;       ;

+; Total LABs:  partially or completely used                   ; 17 / 3,207         ; < 1 % ;

+;     -- Logic LABs                                           ; 17                 ;       ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Combinational ALUT usage for logic                          ; 188                ;       ;

+;     -- 7 input functions                                    ; 0                  ;       ;

+;     -- 6 input functions                                    ; 9                  ;       ;

+;     -- 5 input functions                                    ; 3                  ;       ;

+;     -- 4 input functions                                    ; 124                ;       ;

+;     -- <=3 input functions                                  ; 52                 ;       ;

+; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;

+; Dedicated logic registers                                   ; 35                 ;       ;

+;     -- By type:                                             ;                    ;       ;

+;         -- Primary logic registers                          ; 33 / 64,140        ; < 1 % ;

+;         -- Secondary logic registers                        ; 2 / 64,140         ; < 1 % ;

+;     -- By function:                                         ;                    ;       ;

+;         -- Design implementation registers                  ; 33                 ;       ;

+;         -- Routing optimization registers                   ; 2                  ;       ;

+;                                                             ;                    ;       ;

+; Virtual pins                                                ; 0                  ;       ;

+; I/O pins                                                    ; 38 / 457           ; 8 %   ;

+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;

+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Hard processor system peripheral utilization                ;                    ;       ;

+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;

+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;

+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;

+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;

+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;

+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;

+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;

+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;

+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;

+;                                                             ;                    ;       ;

+; Global signals                                              ; 1                  ;       ;

+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;

+; Total MLAB memory bits                                      ; 0                  ;       ;

+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;

+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;

+;                                                             ;                    ;       ;

+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;

+; Global clocks                                               ; 1 / 16             ; 6 %   ;

+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;

+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;

+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;

+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;

+; JTAGs                                                       ; 0 / 1              ; 0 %   ;

+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;

+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;

+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;

+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;

+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;

+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;

+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;

+; Peak interconnect usage (total/H/V)                         ; 0.9% / 0.9% / 1.0% ;       ;

+; Maximum fan-out                                             ; 18                 ;       ;

+; Highest non-global fan-out                                  ; 17                 ;       ;

+; Total fan-out                                               ; 852                ;       ;

+; Average fan-out                                             ; 2.83               ;       ;

++-------------------------------------------------------------+--------------------+-------+

+

+

++----------------------------------------------------------------------------------------------------------------------+

+; Fitter Partition Statistics                                                                                          ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;

+; ALMs needed [=A-B+C]                                        ; 99                    ; 0                              ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 100 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+;         [a] ALMs used for LUT logic and registers           ; 16                    ; 0                              ;

+;         [b] ALMs used for LUT logic                         ; 83                    ; 0                              ;

+;         [c] ALMs used for registers                         ; 1                     ; 0                              ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;

+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;

+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;

+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Difficulty packing design                                   ; Low                   ; Low                            ;

+;                                                             ;                       ;                                ;

+; Total LABs:  partially or completely used                   ; 17 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;

+;     -- Logic LABs                                           ; 17                    ; 0                              ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Combinational ALUT usage for logic                          ; 188                   ; 0                              ;

+;     -- 7 input functions                                    ; 0                     ; 0                              ;

+;     -- 6 input functions                                    ; 9                     ; 0                              ;

+;     -- 5 input functions                                    ; 3                     ; 0                              ;

+;     -- 4 input functions                                    ; 124                   ; 0                              ;

+;     -- <=3 input functions                                  ; 52                    ; 0                              ;

+; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;

+; Memory ALUT usage                                           ; 0                     ; 0                              ;

+;     -- 64-address deep                                      ; 0                     ; 0                              ;

+;     -- 32-address deep                                      ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Dedicated logic registers                                   ; 0                     ; 0                              ;

+;     -- By type:                                             ;                       ;                                ;

+;         -- Primary logic registers                          ; 33 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;         -- Secondary logic registers                        ; 2 / 64140 ( < 1 % )   ; 0 / 64140 ( 0 % )              ;

+;     -- By function:                                         ;                       ;                                ;

+;         -- Design implementation registers                  ; 33                    ; 0                              ;

+;         -- Routing optimization registers                   ; 2                     ; 0                              ;

+;                                                             ;                       ;                                ;

+;                                                             ;                       ;                                ;

+; Virtual pins                                                ; 0                     ; 0                              ;

+; I/O pins                                                    ; 38                    ; 0                              ;

+; I/O registers                                               ; 0                     ; 0                              ;

+; Total block memory bits                                     ; 0                     ; 0                              ;

+; Total block memory implementation bits                      ; 0                     ; 0                              ;

+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;

+;                                                             ;                       ;                                ;

+; Connections                                                 ;                       ;                                ;

+;     -- Input Connections                                    ; 0                     ; 0                              ;

+;     -- Registered Input Connections                         ; 0                     ; 0                              ;

+;     -- Output Connections                                   ; 0                     ; 0                              ;

+;     -- Registered Output Connections                        ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Internal Connections                                        ;                       ;                                ;

+;     -- Total Connections                                    ; 852                   ; 0                              ;

+;     -- Registered Connections                               ; 139                   ; 0                              ;

+;                                                             ;                       ;                                ;

+; External Connections                                        ;                       ;                                ;

+;     -- Top                                                  ; 0                     ; 0                              ;

+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Partition Interface                                         ;                       ;                                ;

+;     -- Input Ports                                          ; 3                     ; 0                              ;

+;     -- Output Ports                                         ; 35                    ; 0                              ;

+;     -- Bidir Ports                                          ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Registered Ports                                            ;                       ;                                ;

+;     -- Registered Input Ports                               ; 0                     ; 0                              ;

+;     -- Registered Output Ports                              ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Port Connectivity                                           ;                       ;                                ;

+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;

+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;

+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;

+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;

+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;

+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;

+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;

+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Input Pins                                                                                                                                                                                                                                                                              ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 19                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 17                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+

+

++----------------------------------------------------------------------------+

+; I/O Bank Usage                                                             ;

++----------+------------------+---------------+--------------+---------------+

+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;

++----------+------------------+---------------+--------------+---------------+

+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 3B       ; 3 / 48 ( 6 % )   ; 3.3V          ; --           ; 3.3V          ;

+; 4A       ; 0 / 80 ( 0 % )   ; 3.3V          ; --           ; 3.3V          ;

+; 5A       ; 27 / 32 ( 84 % ) ; 3.3V          ; --           ; 3.3V          ;

+; 5B       ; 8 / 16 ( 50 % )  ; 3.3V          ; --           ; 3.3V          ;

+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

++----------+------------------+---------------+--------------+---------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; All Package Pins                                                                                                                                                                  ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;

+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;

+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+Note: Pin directions (input, output or bidir) are based on device operating in user mode.

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                             ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Entity Name ; Library Name ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+

+; |ex6                       ; 98.5 (0.5)           ; 99.5 (0.5)                       ; 1.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 188 (1)             ; 35 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 38   ; 0            ; |ex6                           ; ex6         ; work         ;

+;    |bin2bcd_16:B|          ; 57.0 (0.0)           ; 57.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 106 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A1|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A1  ; add3_ge5    ; work         ;

+;       |add3_ge5:A10|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5    ; work         ;

+;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5    ; work         ;

+;       |add3_ge5:A12|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5    ; work         ;

+;       |add3_ge5:A13|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5    ; work         ;

+;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5    ; work         ;

+;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5    ; work         ;

+;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5    ; work         ;

+;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5    ; work         ;

+;       |add3_ge5:A18|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5    ; work         ;

+;       |add3_ge5:A19|       ; 1.5 (1.5)            ; 1.5 (1.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5    ; work         ;

+;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A2  ; add3_ge5    ; work         ;

+;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5    ; work         ;

+;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5    ; work         ;

+;       |add3_ge5:A22|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A23|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5    ; work         ;

+;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5    ; work         ;

+;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5    ; work         ;

+;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5    ; work         ;

+;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5    ; work         ;

+;       |add3_ge5:A3|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A3  ; add3_ge5    ; work         ;

+;       |add3_ge5:A4|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A4  ; add3_ge5    ; work         ;

+;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A5  ; add3_ge5    ; work         ;

+;       |add3_ge5:A6|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A6  ; add3_ge5    ; work         ;

+;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A7  ; add3_ge5    ; work         ;

+;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A8  ; add3_ge5    ; work         ;

+;       |add3_ge5:A9|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A9  ; add3_ge5    ; work         ;

+;    |counter_16:C|          ; 8.5 (8.5)            ; 8.5 (8.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 16 (16)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|counter_16:C              ; counter_16  ; work         ;

+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG0          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG1          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG2          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG3          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG4|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG4          ; hex_to_7seg ; work         ;

+;    |tick_50000:tck|        ; 15.0 (15.0)          ; 16.0 (16.0)                      ; 1.0 (1.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 29 (29)             ; 19 (19)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|tick_50000:tck            ; tick_50000  ; work         ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Delay Chain Summary                                                                                                     ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; KEY[1]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; KEY[0]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+

+

++---------------------------------------------------------------+

+; Pad To Core Delay Chain Fanout                                ;

++---------------------------------+-------------------+---------+

+; Source Pin / Fanout             ; Pad To Core Index ; Setting ;

++---------------------------------+-------------------+---------+

+; KEY[1]                          ;                   ;         ;

+;      - counter_16:C|count[14]   ; 0                 ; 0       ;

+;      - counter_16:C|count[15]   ; 0                 ; 0       ;

+;      - counter_16:C|count[0]    ; 0                 ; 0       ;

+;      - counter_16:C|count[1]    ; 0                 ; 0       ;

+;      - counter_16:C|count[2]    ; 0                 ; 0       ;

+;      - counter_16:C|count[3]    ; 0                 ; 0       ;

+;      - counter_16:C|count[4]    ; 0                 ; 0       ;

+;      - counter_16:C|count[5]    ; 0                 ; 0       ;

+;      - counter_16:C|count[6]    ; 0                 ; 0       ;

+;      - counter_16:C|count[7]    ; 0                 ; 0       ;

+;      - counter_16:C|count[8]    ; 0                 ; 0       ;

+;      - counter_16:C|count[9]    ; 0                 ; 0       ;

+;      - counter_16:C|count[10]   ; 0                 ; 0       ;

+;      - counter_16:C|count[11]   ; 0                 ; 0       ;

+;      - counter_16:C|count[12]   ; 0                 ; 0       ;

+;      - counter_16:C|count[13]   ; 0                 ; 0       ;

+;      - counter_16:C|count[14]~0 ; 0                 ; 0       ;

+; KEY[0]                          ;                   ;         ;

+;      - counter_16:C|count[14]~0 ; 0                 ; 0       ;

+; CLOCK_50                        ;                   ;         ;

+;      - tick_50000:tck|CLK_OUT   ; 0                 ; 0       ;

++---------------------------------+-------------------+---------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Control Signals                                                                                                                                       ;

++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+

+; Name                     ; Location           ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+

+; CLOCK_50                 ; PIN_AF14           ; 2       ; Clock        ; no     ; --                   ; --               ; --                        ;

+; CLOCK_50                 ; PIN_AF14           ; 18      ; Clock        ; yes    ; Global Clock         ; GCLK6            ; --                        ;

+; KEY[1]                   ; PIN_AA15           ; 17      ; Sync. clear  ; no     ; --                   ; --               ; --                        ;

+; counter_16:C|count[14]~0 ; LABCELL_X46_Y1_N30 ; 16      ; Clock enable ; no     ; --                   ; --               ; --                        ;

+; tick_50000:tck|CLK_OUT   ; FF_X33_Y1_N20      ; 17      ; Clock        ; no     ; --                   ; --               ; --                        ;

+; tick_50000:tck|Equal0~3  ; LABCELL_X33_Y1_N48 ; 8       ; Sync. clear  ; no     ; --                   ; --               ; --                        ;

++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Global & Other Fast Signals                                                                         ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; CLOCK_50 ; PIN_AF14 ; 18      ; Global Clock         ; GCLK6            ; --                        ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------+

+; Routing Usage Summary                                                 ;

++---------------------------------------------+-------------------------+

+; Routing Resource Type                       ; Usage                   ;

++---------------------------------------------+-------------------------+

+; Block interconnects                         ; 179 / 289,320 ( < 1 % ) ;

+; C12 interconnects                           ; 5 / 13,420 ( < 1 % )    ;

+; C2 interconnects                            ; 61 / 119,108 ( < 1 % )  ;

+; C4 interconnects                            ; 56 / 56,300 ( < 1 % )   ;

+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;

+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;

+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;

+; Direct links                                ; 45 / 289,320 ( < 1 % )  ;

+; Global clocks                               ; 1 / 16 ( 6 % )          ;

+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;

+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;

+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;

+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;

+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;

+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;

+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;

+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;

+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;

+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;

+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;

+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;

+; Local interconnects                         ; 81 / 84,580 ( < 1 % )   ;

+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;

+; R14 interconnects                           ; 7 / 12,676 ( < 1 % )    ;

+; R14/C12 interconnect drivers                ; 12 / 20,720 ( < 1 % )   ;

+; R3 interconnects                            ; 80 / 130,992 ( < 1 % )  ;

+; R6 interconnects                            ; 160 / 266,960 ( < 1 % ) ;

+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;

+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;

++---------------------------------------------+-------------------------+

+

+

++------------------------------------------+

+; I/O Rules Summary                        ;

++----------------------------------+-------+

+; I/O Rules Statistic              ; Total ;

++----------------------------------+-------+

+; Total I/O Rules                  ; 28    ;

+; Number of I/O Rules Passed       ; 6     ;

+; Number of I/O Rules Failed       ; 0     ;

+; Number of I/O Rules Unchecked    ; 0     ;

+; Number of I/O Rules Inapplicable ; 22    ;

++----------------------------------+-------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Details                                                                                                                                                                                                                                                  ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;

+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;

+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;

+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;

+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;

+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Total Pass         ; 38        ; 0            ; 38        ; 0            ; 0            ; 38        ; 38        ; 0            ; 38        ; 38        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Inapplicable ; 0         ; 38           ; 0         ; 38           ; 38           ; 0         ; 0         ; 38           ; 0         ; 0         ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ;

+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+

+

++------------------------------------------------------------------------------------------------+

+; Fitter Device Options                                                                          ;

++------------------------------------------------------------------+-----------------------------+

+; Option                                                           ; Setting                     ;

++------------------------------------------------------------------+-----------------------------+

+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;

+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;

+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;

+; Enable INIT_DONE output                                          ; Off                         ;

+; Configuration scheme                                             ; Passive Serial              ;

+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;

+; Enable CvP_CONFDONE pin                                          ; Off                         ;

+; Enable open drain on CRC_ERROR pin                               ; On                          ;

+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;

+; Enable open drain on INIT_DONE pin                               ; On                          ;

+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;

+; Enable open drain on nCEO pin                                    ; On                          ;

+; Enable Partial Reconfiguration pins                              ; Off                         ;

+; Enable input tri-state on active configuration pins in user mode ; Off                         ;

+; Enable internal scrubbing                                        ; Off                         ;

+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;

+; Device initialization clock source                               ; Internal Oscillator         ;

+; Configuration via Protocol                                       ; Off                         ;

+; Configuration Voltage Level                                      ; Auto                        ;

+; Force Configuration Voltage Level                                ; Off                         ;

+; Enable nCEO output                                               ; Off                         ;

+; Data[15..8]                                                      ; Unreserved                  ;

+; Data[7..5]                                                       ; Unreserved                  ;

+; Base pin-out file on sameframe device                            ; Off                         ;

++------------------------------------------------------------------+-----------------------------+

+

+

++------------------------------------+

+; Operating Settings and Conditions  ;

++---------------------------+--------+

+; Setting                   ; Value  ;

++---------------------------+--------+

+; Nominal Core Voltage      ; 1.10 V ;

+; Low Junction Temperature  ; 0 °C   ;

+; High Junction Temperature ; 85 °C  ;

++---------------------------+--------+

+

+

++------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Summary              ;

++-----------------+----------------------+-------------------+

+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;

++-----------------+----------------------+-------------------+

+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.

+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.

+

+

++-----------------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Details                         ;

++--------------------------+------------------------+-------------------+

+; Source Register          ; Destination Register   ; Delay Added in ns ;

++--------------------------+------------------------+-------------------+

+; tick_50000:tck|count[14] ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[13] ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[12] ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[11] ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[10] ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[9]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[8]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[15] ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[5]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[4]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[3]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[2]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[1]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[0]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[7]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|count[6]  ; tick_50000:tck|CLK_OUT ; 0.948             ;

+; tick_50000:tck|CLK_OUT   ; tick_50000:tck|CLK_OUT ; 0.948             ;

++--------------------------+------------------------+-------------------+

+Note: This table only shows the top 17 path(s) that have the largest delay added for hold.

+

+

++-----------------+

+; Fitter Messages ;

++-----------------+

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (119006): Selected device 5CSEMA5F31C6 for design "ex6"

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

+Info (184020): Starting Fitter periphery placement operations

+Info (11191): Automatically promoted 1 clock (1 global)

+    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6

+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

+Info (176233): Starting register packing

+Info (176235): Finished register packing

+    Extra Info (176219): No registers were packed into other blocks

+Warning (15705): Ignored locations or region assignments to the following nodes

+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design

+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10

+Info (332104): Reading SDC File: 'ex6.sdc'

+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.

+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements

+Info (332111): Found 1 clocks

+    Info (332111):   Period   Clock Name

+    Info (332111): ======== ============

+    Info (332111):   20.000     CLOCK_50

+Info (170189): Fitter placement preparation operations beginning

+Info (14951): The Fitter is using Advanced Physical Optimization.

+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01

+Info (170191): Fitter placement operations beginning

+Info (170137): Fitter placement was successful

+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01

+Info (170193): Fitter routing operations beginning

+Info (170195): Router estimated average interconnect usage is 0% of the available device resources

+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10

+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.

+    Info (170201): Optimizations that may affect the design's routability were skipped

+    Info (170200): Optimizations that may affect the design's timing were skipped

+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01

+Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03

+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

+Info (144001): Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg

+Info: Quartus Prime Fitter was successful. 0 errors, 48 warnings

+    Info: Peak virtual memory: 2591 megabytes

+    Info: Processing ended: Tue Nov 22 11:43:33 2016

+    Info: Elapsed time: 00:00:30

+    Info: Total CPU time (on all processors): 00:00:53

+

+

++----------------------------+

+; Fitter Suppressed Messages ;

++----------------------------+

+The suppressed messages can be found in C:/New folder/ex6/output_files/ex6.fit.smsg.

+

+

diff --git a/part_2/ex6/output_files/ex6.fit.smsg b/part_2/ex6/output_files/ex6.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing

+Extra Info (176237): Finished Fast Input/Output/OE register processing

+Extra Info (176238): Start inferring scan chains for DSP blocks

+Extra Info (176239): Inferring scan chains for DSP blocks is complete

+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density

+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

diff --git a/part_2/ex6/output_files/ex6.fit.summary b/part_2/ex6/output_files/ex6.fit.summary
new file mode 100755
index 0000000..bc14ca7
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Nov 22 11:43:32 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex6

+Top-level Entity Name : ex6

+Family : Cyclone V

+Device : 5CSEMA5F31C6

+Timing Models : Final

+Logic utilization (in ALMs) : 99 / 32,070 ( < 1 % )

+Total registers : 35

+Total pins : 38 / 457 ( 8 % )

+Total virtual pins : 0

+Total block memory bits : 0 / 4,065,280 ( 0 % )

+Total RAM Blocks : 0 / 397 ( 0 % )

+Total DSP Blocks : 0 / 87 ( 0 % )

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0 / 6 ( 0 % )

+Total DLLs : 0 / 4 ( 0 % )

diff --git a/part_2/ex6/output_files/ex6.flow.rpt b/part_2/ex6/output_files/ex6.flow.rpt
new file mode 100755
index 0000000..1e44f79
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.flow.rpt
@@ -0,0 +1,128 @@
+Flow report for ex6

+Tue Nov 22 11:43:46 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Flow Summary

+  3. Flow Settings

+  4. Flow Non-Default Global Settings

+  5. Flow Elapsed Time

+  6. Flow OS Summary

+  7. Flow Log

+  8. Flow Messages

+  9. Flow Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Flow Summary                                                                      ;

++---------------------------------+-------------------------------------------------+

+; Flow Status                     ; Successful - Tue Nov 22 11:43:40 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex6                                             ;

+; Top-level Entity Name           ; ex6                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 99 / 32,070 ( < 1 % )                           ;

+; Total registers                 ; 35                                              ;

+; Total pins                      ; 38 / 457 ( 8 % )                                ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++-----------------------------------------+

+; Flow Settings                           ;

++-------------------+---------------------+

+; Option            ; Setting             ;

++-------------------+---------------------+

+; Start date & time ; 11/22/2016 11:42:53 ;

+; Main task         ; Compilation         ;

+; Revision Name     ; ex6                 ;

++-------------------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------+

+; Flow Non-Default Global Settings                                                                                       ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; COMPILER_SIGNATURE_ID               ; 260248564170200.147981497204968       ; --            ; --          ; --         ;

+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;

+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;

+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;

+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;

+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;

+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;

+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;

+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------+

+; Flow Elapsed Time                                                                                                             ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 897 MB              ; 00:00:21                           ;

+; Fitter                    ; 00:00:29     ; 1.0                     ; 2591 MB             ; 00:00:53                           ;

+; Assembler                 ; 00:00:06     ; 1.0                     ; 892 MB              ; 00:00:06                           ;

+; TimeQuest Timing Analyzer ; 00:00:05     ; 1.1                     ; 1209 MB             ; 00:00:05                           ;

+; Total                     ; 00:00:50     ; --                      ; --                  ; 00:01:25                           ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+

+

++----------------------------------------------------------------------------------------+

+; Flow OS Summary                                                                        ;

++---------------------------+------------------+-----------+------------+----------------+

+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;

++---------------------------+------------------+-----------+------------+----------------+

+; Analysis & Synthesis      ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

+; Fitter                    ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

+; Assembler                 ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

+; TimeQuest Timing Analyzer ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

++---------------------------+------------------+-----------+------------+----------------+

+

+

+------------

+; Flow Log ;

+------------

+quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6

+quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6

+quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6

+quartus_sta ex6 -c ex6

+

+

+

diff --git a/part_2/ex6/output_files/ex6.jdi b/part_2/ex6/output_files/ex6.jdi
new file mode 100755
index 0000000..30e9a8a
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>

+  <project>

+    <hash md5_digest_80b="baef6963dc4d960fc697"/>

+  </project>

+  <file_info>

+    <file device="5CSEMA5F31C6" path="ex6.sof" usercode="0xFFFFFFFF"/>

+  </file_info>

+</sld_project_info>

diff --git a/part_2/ex6/output_files/ex6.map.rpt b/part_2/ex6/output_files/ex6.map.rpt
new file mode 100755
index 0000000..a381799
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.map.rpt
@@ -0,0 +1,438 @@
+Analysis & Synthesis report for ex6

+Tue Nov 22 11:43:02 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Analysis & Synthesis Summary

+  3. Analysis & Synthesis Settings

+  4. Parallel Compilation

+  5. Analysis & Synthesis Source Files Read

+  6. Analysis & Synthesis Resource Usage Summary

+  7. Analysis & Synthesis Resource Utilization by Entity

+  8. General Register Statistics

+  9. Inverted Register Statistics

+ 10. Multiplexer Restructuring Statistics (Restructuring Performed)

+ 11. Parameter Settings for User Entity Instance: tick_50000:tck

+ 12. Parameter Settings for User Entity Instance: counter_16:C

+ 13. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18"

+ 14. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9"

+ 15. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3"

+ 16. Post-Synthesis Netlist Statistics for Top Partition

+ 17. Elapsed Time Per Partition

+ 18. Analysis & Synthesis Messages

+ 19. Analysis & Synthesis Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Analysis & Synthesis Summary                                                      ;

++---------------------------------+-------------------------------------------------+

+; Analysis & Synthesis Status     ; Successful - Tue Nov 22 11:43:02 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex6                                             ;

+; Top-level Entity Name           ; ex6                                             ;

+; Family                          ; Cyclone V                                       ;

+; Logic utilization (in ALMs)     ; N/A                                             ;

+; Total registers                 ; 33                                              ;

+; Total pins                      ; 38                                              ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0                                               ;

+; Total DSP Blocks                ; 0                                               ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0                                               ;

+; Total DLLs                      ; 0                                               ;

++---------------------------------+-------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Settings                                                                                             ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Option                                                                          ; Setting            ; Default Value      ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;

+; Top-level entity name                                                           ; ex6                ; ex6                ;

+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;

+; Use smart compilation                                                           ; Off                ; Off                ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;

+; Enable compact report table                                                     ; Off                ; Off                ;

+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;

+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;

+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;

+; Preserve fewer node names                                                       ; On                 ; On                 ;

+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;

+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;

+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;

+; State Machine Processing                                                        ; Auto               ; Auto               ;

+; Safe State Machine                                                              ; Off                ; Off                ;

+; Extract Verilog State Machines                                                  ; On                 ; On                 ;

+; Extract VHDL State Machines                                                     ; On                 ; On                 ;

+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;

+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;

+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;

+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;

+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;

+; Parallel Synthesis                                                              ; On                 ; On                 ;

+; DSP Block Balancing                                                             ; Auto               ; Auto               ;

+; NOT Gate Push-Back                                                              ; On                 ; On                 ;

+; Power-Up Don't Care                                                             ; On                 ; On                 ;

+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;

+; Remove Duplicate Registers                                                      ; On                 ; On                 ;

+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;

+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;

+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;

+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;

+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;

+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;

+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;

+; Optimization Technique                                                          ; Balanced           ; Balanced           ;

+; Carry Chain Length                                                              ; 70                 ; 70                 ;

+; Auto Carry Chains                                                               ; On                 ; On                 ;

+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;

+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;

+; Auto ROM Replacement                                                            ; On                 ; On                 ;

+; Auto RAM Replacement                                                            ; On                 ; On                 ;

+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;

+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;

+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;

+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;

+; Strict RAM Replacement                                                          ; Off                ; Off                ;

+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;

+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;

+; Auto Resource Sharing                                                           ; Off                ; Off                ;

+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;

+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;

+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;

+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;

+; Report Parameter Settings                                                       ; On                 ; On                 ;

+; Report Source Assignments                                                       ; On                 ; On                 ;

+; Report Connectivity Checks                                                      ; On                 ; On                 ;

+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;

+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;

+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;

+; HDL message level                                                               ; Level2             ; Level2             ;

+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;

+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;

+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;

+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;

+; Clock MUX Protection                                                            ; On                 ; On                 ;

+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;

+; Block Design Naming                                                             ; Auto               ; Auto               ;

+; SDC constraint protection                                                       ; Off                ; Off                ;

+; Synthesis Effort                                                                ; Auto               ; Auto               ;

+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;

+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;

+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;

+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;

+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;

+; Synthesis Seed                                                                  ; 1                  ; 1                  ;

+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;

+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processors 2-4         ;   0.0%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Source Files Read                                                                                                ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ; Library ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/hex_to_7seg.v ;         ;

+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/bin2bcd_16.v  ;         ;

+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/add3_ge5.v    ;         ;

+; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/counter_16.v  ;         ;

+; ex6.v                            ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/ex6.v                       ;         ;

+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/tick_50000.v  ;         ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+

+

++----------------------------------------------------------------------+

+; Analysis & Synthesis Resource Usage Summary                          ;

++---------------------------------------------+------------------------+

+; Resource                                    ; Usage                  ;

++---------------------------------------------+------------------------+

+; Estimate of Logic utilization (ALMs needed) ; 98                     ;

+;                                             ;                        ;

+; Combinational ALUT usage for logic          ; 187                    ;

+;     -- 7 input functions                    ; 0                      ;

+;     -- 6 input functions                    ; 9                      ;

+;     -- 5 input functions                    ; 3                      ;

+;     -- 4 input functions                    ; 124                    ;

+;     -- <=3 input functions                  ; 51                     ;

+;                                             ;                        ;

+; Dedicated logic registers                   ; 33                     ;

+;                                             ;                        ;

+; I/O pins                                    ; 38                     ;

+;                                             ;                        ;

+; Total DSP Blocks                            ; 0                      ;

+;                                             ;                        ;

+; Maximum fan-out node                        ; tick_50000:tck|CLK_OUT ;

+; Maximum fan-out                             ; 17                     ;

+; Total fan-out                               ; 846                    ;

+; Average fan-out                             ; 2.86                   ;

++---------------------------------------------+------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Entity Name ; Library Name ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+

+; |ex6                       ; 187 (0)           ; 33 (0)       ; 0                 ; 0          ; 38   ; 0            ; |ex6                           ; ex6         ; work         ;

+;    |bin2bcd_16:B|          ; 106 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A10|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5    ; work         ;

+;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5    ; work         ;

+;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5    ; work         ;

+;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5    ; work         ;

+;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5    ; work         ;

+;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5    ; work         ;

+;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5    ; work         ;

+;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5    ; work         ;

+;       |add3_ge5:A18|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5    ; work         ;

+;       |add3_ge5:A19|       ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5    ; work         ;

+;       |add3_ge5:A1|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A1  ; add3_ge5    ; work         ;

+;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5    ; work         ;

+;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5    ; work         ;

+;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5    ; work         ;

+;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5    ; work         ;

+;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5    ; work         ;

+;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5    ; work         ;

+;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5    ; work         ;

+;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A2  ; add3_ge5    ; work         ;

+;       |add3_ge5:A3|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A3  ; add3_ge5    ; work         ;

+;       |add3_ge5:A4|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A4  ; add3_ge5    ; work         ;

+;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A5  ; add3_ge5    ; work         ;

+;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A6  ; add3_ge5    ; work         ;

+;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A7  ; add3_ge5    ; work         ;

+;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A8  ; add3_ge5    ; work         ;

+;       |add3_ge5:A9|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A9  ; add3_ge5    ; work         ;

+;    |counter_16:C|          ; 17 (17)           ; 16 (16)      ; 0                 ; 0          ; 0    ; 0            ; |ex6|counter_16:C              ; counter_16  ; work         ;

+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG0          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG1          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG2          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG3          ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG4|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG4          ; hex_to_7seg ; work         ;

+;    |tick_50000:tck|        ; 29 (29)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex6|tick_50000:tck            ; tick_50000  ; work         ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++------------------------------------------------------+

+; General Register Statistics                          ;

++----------------------------------------------+-------+

+; Statistic                                    ; Value ;

++----------------------------------------------+-------+

+; Total registers                              ; 33    ;

+; Number of registers using Synchronous Clear  ; 24    ;

+; Number of registers using Synchronous Load   ; 0     ;

+; Number of registers using Asynchronous Clear ; 0     ;

+; Number of registers using Asynchronous Load  ; 0     ;

+; Number of registers using Clock Enable       ; 16    ;

+; Number of registers using Preset             ; 0     ;

++----------------------------------------------+-------+

+

+

++--------------------------------------------------+

+; Inverted Register Statistics                     ;

++----------------------------------------+---------+

+; Inverted Register                      ; Fan out ;

++----------------------------------------+---------+

+; tick_50000:tck|count[8]                ; 3       ;

+; tick_50000:tck|count[0]                ; 2       ;

+; tick_50000:tck|count[1]                ; 2       ;

+; tick_50000:tck|count[2]                ; 2       ;

+; tick_50000:tck|count[5]                ; 2       ;

+; tick_50000:tck|count[7]                ; 2       ;

+; tick_50000:tck|count[13]               ; 2       ;

+; tick_50000:tck|count[14]               ; 2       ;

+; Total number of inverted registers = 8 ;         ;

++----------------------------------------+---------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------------------+

+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+

+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+

+; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex6|counter_16:C|count[14] ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+

+

+

++-------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: tick_50000:tck ;

++----------------+-------+------------------------------------+

+; Parameter Name ; Value ; Type                               ;

++----------------+-------+------------------------------------+

+; NBIT           ; 16    ; Signed Integer                     ;

++----------------+-------+------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++-----------------------------------------------------------+

+; Parameter Settings for User Entity Instance: counter_16:C ;

++----------------+-------+----------------------------------+

+; Parameter Name ; Value ; Type                             ;

++----------------+-------+----------------------------------+

+; BIT_SZ         ; 16    ; Signed Integer                   ;

++----------------+-------+----------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++-------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18" ;

++------+-------+----------+-----------------------------+

+; Port ; Type  ; Severity ; Details                     ;

++------+-------+----------+-----------------------------+

+; w[3] ; Input ; Info     ; Stuck at GND                ;

++------+-------+----------+-----------------------------+

+

+

++------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9" ;

++------+-------+----------+----------------------------+

+; Port ; Type  ; Severity ; Details                    ;

++------+-------+----------+----------------------------+

+; w[3] ; Input ; Info     ; Stuck at GND               ;

++------+-------+----------+----------------------------+

+

+

++------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3" ;

++------+-------+----------+----------------------------+

+; Port ; Type  ; Severity ; Details                    ;

++------+-------+----------+----------------------------+

+; w[3] ; Input ; Info     ; Stuck at GND               ;

++------+-------+----------+----------------------------+

+

+

++-----------------------------------------------------+

+; Post-Synthesis Netlist Statistics for Top Partition ;

++-----------------------+-----------------------------+

+; Type                  ; Count                       ;

++-----------------------+-----------------------------+

+; arriav_ff             ; 33                          ;

+;     ENA SCLR          ; 16                          ;

+;     SCLR              ; 8                           ;

+;     plain             ; 9                           ;

+; arriav_lcell_comb     ; 204                         ;

+;     arith             ; 32                          ;

+;         1 data inputs ; 32                          ;

+;     normal            ; 172                         ;

+;         1 data inputs ; 25                          ;

+;         2 data inputs ; 1                           ;

+;         3 data inputs ; 10                          ;

+;         4 data inputs ; 124                         ;

+;         5 data inputs ; 3                           ;

+;         6 data inputs ; 9                           ;

+; boundary_port         ; 38                          ;

+;                       ;                             ;

+; Max LUT depth         ; 13.00                       ;

+; Average LUT depth     ; 8.75                        ;

++-----------------------+-----------------------------+

+

+

++-------------------------------+

+; Elapsed Time Per Partition    ;

++----------------+--------------+

+; Partition Name ; Elapsed Time ;

++----------------+--------------+

+; Top            ; 00:00:00     ;

++----------------+--------------+

+

+

++-------------------------------+

+; Analysis & Synthesis Messages ;

++-------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Analysis & Synthesis

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Tue Nov 22 11:42:52 2016

+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v

+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex6/verilog_files/hex_to_7seg.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v

+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 12

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v

+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex6/verilog_files/add3_ge5.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v

+    Info (12023): Found entity 1: counter_16 File: C:/New folder/ex6/verilog_files/counter_16.v Line: 3

+Info (12021): Found 1 design units, including 1 entities, in source file ex6.v

+    Info (12023): Found entity 1: ex6 File: C:/New folder/ex6/ex6.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v

+    Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex6/verilog_files/tick_50000.v Line: 1

+Info (12127): Elaborating entity "ex6" for the top level hierarchy

+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:tck" File: C:/New folder/ex6/ex6.v Line: 11

+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:C" File: C:/New folder/ex6/ex6.v Line: 13

+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:B" File: C:/New folder/ex6/ex6.v Line: 15

+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:B|add3_ge5:A1" File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 26

+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex6/ex6.v Line: 17

+Info (286030): Timing-Driven Synthesis is running

+Info (144001): Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg

+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

+Info (21057): Implemented 225 device resources after synthesis - the final resource count might be different

+    Info (21058): Implemented 3 input pins

+    Info (21059): Implemented 35 output pins

+    Info (21061): Implemented 187 logic cells

+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 897 megabytes

+    Info: Processing ended: Tue Nov 22 11:43:02 2016

+    Info: Elapsed time: 00:00:10

+    Info: Total CPU time (on all processors): 00:00:21

+

+

++------------------------------------------+

+; Analysis & Synthesis Suppressed Messages ;

++------------------------------------------+

+The suppressed messages can be found in C:/New folder/ex6/output_files/ex6.map.smsg.

+

+

diff --git a/part_2/ex6/output_files/ex6.map.smsg b/part_2/ex6/output_files/ex6.map.smsg
new file mode 100755
index 0000000..e49d2c0
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.map.smsg
@@ -0,0 +1,29 @@
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 22

diff --git a/part_2/ex6/output_files/ex6.map.summary b/part_2/ex6/output_files/ex6.map.summary
new file mode 100755
index 0000000..c25655f
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Nov 22 11:43:02 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex6

+Top-level Entity Name : ex6

+Family : Cyclone V

+Logic utilization (in ALMs) : N/A

+Total registers : 33

+Total pins : 38

+Total virtual pins : 0

+Total block memory bits : 0

+Total DSP Blocks : 0

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0

+Total DLLs : 0

diff --git a/part_2/ex6/output_files/ex6.pin b/part_2/ex6/output_files/ex6.pin
new file mode 100755
index 0000000..c13fc33
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+ -- Your use of Altera Corporation's design tools, logic functions 

+ -- and other software and tools, and its AMPP partner logic 

+ -- functions, and any output files from any of the foregoing 

+ -- (including device programming or simulation files), and any 

+ -- associated documentation or information are expressly subject 

+ -- to the terms and conditions of the Altera Program License 

+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,

+ -- the Altera MegaCore Function License Agreement, or other 

+ -- applicable license agreement, including, without limitation, 

+ -- that your use is for the sole purpose of programming logic 

+ -- devices manufactured by Altera and sold by Altera or its 

+ -- authorized distributors.  Please refer to the applicable 

+ -- agreement for further details.

+ -- 

+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is

+ -- not intended for use as a Quartus Prime input file. This file cannot be used

+ -- to make Quartus Prime pin assignments - for instructions on how to make pin

+ -- assignments, please see Quartus Prime help.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- NC            : No Connect. This pin has no internal connection to the device.

+ -- DNU           : Do Not Use. This pin MUST NOT be connected.

+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.

+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).

+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC

+ --                 of its bank.

+ --                  Bank 3A:       2.5V

+ --                  Bank 3B:       3.3V

+ --                  Bank 4A:       3.3V

+ --                  Bank 5A:       3.3V

+ --                  Bank 5B:       3.3V

+ --                  Bank 6B:       2.5V

+ --                  Bank 6A:  2.5V

+ --                  Bank 7A:  2.5V

+ --                  Bank 7B:  2.5V

+ --                  Bank 7C:  2.5V

+ --                  Bank 7D:  2.5V

+ --                  Bank 8A:  2.5V

+ -- RREF          : External reference resistor for the quad, MUST be connected to

+ --                 GND via a 2k Ohm resistor.

+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.

+ --                  It can also be used to report unused dedicated pins. The connection

+ --                  on the board for unused dedicated pins depends on whether this will

+ --                  be used in a future design. One example is device migration. When

+ --                  using device migration, refer to the device pin-tables. If it is a

+ --                  GND pin in the pin table or if it will not be used in a future design

+ --                  for another purpose the it MUST be connected to GND. If it is an unused

+ --                  dedicated pin, then it can be connected to a valid signal on the board

+ --                  (low, high, or toggling) if that signal is required for a different

+ --                  revision of the design.

+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.

+ --                  This pin should be connected to GND. It may also be connected  to a

+ --                  valid signal  on the board  (low, high, or toggling)  if that signal

+ --                  is required for a different revision of the design.

+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND

+ --                  or leave it unconnected.

+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.

+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.

+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.

+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.

+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.

+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin

+ --                 must not be connected.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- Pin directions (input, output or bidir) are based on device operating in user mode.

+ ---------------------------------------------------------------------------------

+

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+CHIP  "ex6"  ASSIGNED TO AN: 5CSEMA5F31C6

+

+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

+-------------------------------------------------------------------------------------------------------------

+GND                          : A2        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                

+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                

+GND                          : A12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                

+GND                          : A17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                

+GND                          : A22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                

+GND                          : A26       :        :                   :         : 7A        :                

+GND                          : A27       : gnd    :                   :         :           :                

+HPS_TRST                     : A28       :        :                   :         : 7A        :                

+HPS_TMS                      : A29       :        :                   :         : 7A        :                

+GND                          : AA1       : gnd    :                   :         :           :                

+GND                          : AA2       : gnd    :                   :         :           :                

+GND                          : AA3       : gnd    :                   :         :           :                

+GND                          : AA4       : gnd    :                   :         :           :                

+VCC                          : AA5       : power  :                   : 1.1V    :           :                

+GND                          : AA6       : gnd    :                   :         :           :                

+DNU                          : AA7       :        :                   :         :           :                

+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                

+GND                          : AA9       : gnd    :                   :         :           :                

+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                

+GND                          : AA11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                

+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                

+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                

+GND                          : AA22      : gnd    :                   :         :           :                

+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                

+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                

+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                

+GND                          : AB1       : gnd    :                   :         :           :                

+GND                          : AB2       : gnd    :                   :         :           :                

+DNU                          : AB3       :        :                   :         :           :                

+DNU                          : AB4       :        :                   :         :           :                

+GND                          : AB5       : gnd    :                   :         :           :                

+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                

+GND                          : AB7       : gnd    :                   :         :           :                

+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                

+TDO                          : AB9       : output :                   :         : 3A        :                

+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                

+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                

+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AB19      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                

+HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                

+HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                

+HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AB29      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                

+GND                          : AC1       : gnd    :                   :         :           :                

+GND                          : AC2       : gnd    :                   :         :           :                

+GND                          : AC3       : gnd    :                   :         :           :                

+GND                          : AC4       : gnd    :                   :         :           :                

+TCK                          : AC5       : input  :                   :         : 3A        :                

+GND                          : AC6       : gnd    :                   :         :           :                

+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                

+GND                          : AC8       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                

+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                

+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                

+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                

+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AC16      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                

+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                

+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                

+HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AC26      : gnd    :                   :         :           :                

+HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AD1       : gnd    :                   :         :           :                

+GND                          : AD2       : gnd    :                   :         :           :                

+DNU                          : AD3       :        :                   :         :           :                

+DNU                          : AD4       :        :                   :         :           :                

+GND                          : AD5       : gnd    :                   :         :           :                

+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                

+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                

+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                

+DNU                          : AD15      :        :                   :         :           :                

+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                

+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                

+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                

+GND                          : AD23      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                

+HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                

+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AE1       : gnd    :                   :         :           :                

+GND                          : AE2       : gnd    :                   :         :           :                

+GND                          : AE3       : gnd    :                   :         :           :                

+GND                          : AE4       : gnd    :                   :         :           :                

+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                

+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                

+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                

+GND                          : AE10      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                

+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                

+GND                          : AE20      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                

+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                

+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                

+GND                          : AF1       : gnd    :                   :         :           :                

+GND                          : AF2       : gnd    :                   :         :           :                

+GND                          : AF3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                

+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                

+GND                          : AF12      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                

+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                

+GND                          : AF17      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                

+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                

+GND                          : AF27      : gnd    :                   :         :           :                

+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                

+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                

+GND                          : AG9       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                

+GND                          : AG14      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                

+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                

+GND                          : AG24      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                

+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                

+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AH1       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                

+GND                          : AH6       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                

+GND                          : AH11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                

+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                

+GND                          : AH21      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                

+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                

+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                

+GND                          : AJ3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                

+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                

+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                

+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                

+GND                          : AJ18      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                

+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                

+GND                          : AJ28      : gnd    :                   :         :           :                

+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AJ30      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                

+GND                          : AK5       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                

+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                

+GND                          : AK15      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                

+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                

+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                

+GND                          : AK25      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                

+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                

+GND                          : B9        : gnd    :                   :         :           :                

+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                

+GND                          : B14       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                

+GND                          : B19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                

+GND                          : B24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                

+HPS_TDI                      : B27       :        :                   :         : 7A        :                

+HPS_TDO                      : B28       :        :                   :         : 7A        :                

+GND                          : B29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                

+GND                          : C1        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                

+GND                          : C6        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                

+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                

+GND                          : C16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                

+GND                          : C21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                

+GND                          : C26       : gnd    :                   :         :           :                

+HPS_nRST                     : C27       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                

+GND                          : D3        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                

+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                

+GND                          : D13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                

+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                

+GND                          : D23       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                

+HPS_CLK1                     : D25       :        :                   :         : 7A        :                

+GND                          : D26       :        :                   :         : 7A        :                

+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                

+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                

+GND                          : E10       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                

+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                

+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                

+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                

+GND                          : E25       : gnd    :                   :         :           :                

+DNU                          : E26       :        :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                

+GND                          : E30       : gnd    :                   :         :           :                

+DNU                          : F1        :        :                   :         :           :                

+GND                          : F2        : gnd    :                   :         :           :                

+CONF_DONE                    : F3        :        :                   :         : 9A        :                

+nSTATUS                      : F4        :        :                   :         : 9A        :                

+GND                          : F5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                

+GND                          : F7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                

+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                

+GND                          : F17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                

+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                

+HPS_nPOR                     : F23       :        :                   :         : 7A        :                

+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                

+HPS_CLK2                     : F25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                

+GND                          : F27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                

+GND                          : G1        :        :                   :         :           :                

+DNU                          : G2        :        :                   :         :           :                

+GND                          : G3        : gnd    :                   :         :           :                

+GND                          : G4        : gnd    :                   :         :           :                

+nCE                          : G5        :        :                   :         : 9A        :                

+MSEL2                        : G6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                

+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                

+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                

+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                

+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                

+GND                          : G24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                

+GND                          : H1        : gnd    :                   :         :           :                

+GND                          : H2        : gnd    :                   :         :           :                

+DNU                          : H3        :        :                   :         :           :                

+DNU                          : H4        :        :                   :         :           :                

+GND                          : H5        : gnd    :                   :         :           :                

+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                

+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                

+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                

+GND                          : H11       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                

+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                

+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                

+HPS_TCK                      : H22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                

+GND                          : J1        : gnd    :                   :         :           :                

+GND                          : J2        : gnd    :                   :         :           :                

+GND                          : J3        : gnd    :                   :         :           :                

+GND                          : J4        : gnd    :                   :         :           :                

+nCONFIG                      : J5        :        :                   :         : 9A        :                

+GND                          : J6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                

+GND                          : J8        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                

+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                

+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                

+DNU                          : J15       :        :                   :         :           :                

+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                

+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                

+GND                          : J18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                

+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                

+GND                          : J22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                

+GND                          : J28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                

+GND                          : K1        : gnd    :                   :         :           :                

+GND                          : K2        : gnd    :                   :         :           :                

+DNU                          : K3        :        :                   :         :           :                

+DNU                          : K4        :        :                   :         :           :                

+GND                          : K5        : gnd    :                   :         :           :                

+MSEL1                        : K6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                

+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                

+GND                          : K10       : gnd    :                   :         :           :                

+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                

+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                

+GND                          : K15       : gnd    :                   :         :           :                

+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                

+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                

+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                

+GND                          : K20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                

+GND                          : K25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                

+GND                          : L1        : gnd    :                   :         :           :                

+GND                          : L2        : gnd    :                   :         :           :                

+GND                          : L3        : gnd    :                   :         :           :                

+GND                          : L4        : gnd    :                   :         :           :                

+VCC                          : L5        : power  :                   : 1.1V    :           :                

+GND                          : L6        : gnd    :                   :         :           :                

+MSEL3                        : L7        :        :                   :         : 9A        :                

+MSEL0                        : L8        :        :                   :         : 9A        :                

+MSEL4                        : L9        :        :                   :         : 9A        :                

+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                

+GND                          : L11       : gnd    :                   :         :           :                

+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                

+GND                          : L13       : gnd    :                   :         :           :                

+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                

+GND                          : L15       : gnd    :                   :         :           :                

+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                

+GND                          : L17       : gnd    :                   :         :           :                

+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                

+GND                          : L19       : gnd    :                   :         :           :                

+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                

+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                

+GND                          : L22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                

+GND                          : M1        : gnd    :                   :         :           :                

+GND                          : M2        : gnd    :                   :         :           :                

+DNU                          : M3        :        :                   :         :           :                

+DNU                          : M4        :        :                   :         :           :                

+GND                          : M5        : gnd    :                   :         :           :                

+VCC                          : M6        : power  :                   : 1.1V    :           :                

+GND                          : M7        : gnd    :                   :         :           :                

+GND                          : M8        : gnd    :                   :         :           :                

+VCC                          : M9        : power  :                   : 1.1V    :           :                

+GND                          : M10       : gnd    :                   :         :           :                

+VCC                          : M11       : power  :                   : 1.1V    :           :                

+GND                          : M12       : gnd    :                   :         :           :                

+VCC                          : M13       : power  :                   : 1.1V    :           :                

+GND                          : M14       : gnd    :                   :         :           :                

+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                

+GND                          : M16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                

+GND                          : M18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                

+GND                          : M20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                

+GND                          : M29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                

+GND                          : N1        : gnd    :                   :         :           :                

+GND                          : N2        : gnd    :                   :         :           :                

+GND                          : N3        : gnd    :                   :         :           :                

+GND                          : N4        : gnd    :                   :         :           :                

+VCC                          : N5        : power  :                   : 1.1V    :           :                

+GND                          : N6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                

+GND                          : N8        : gnd    :                   :         :           :                

+GND                          : N9        : gnd    :                   :         :           :                

+VCC                          : N10       : power  :                   : 1.1V    :           :                

+GND                          : N11       : gnd    :                   :         :           :                

+VCC                          : N12       : power  :                   : 1.1V    :           :                

+GND                          : N13       : gnd    :                   :         :           :                

+VCC                          : N14       : power  :                   : 1.1V    :           :                

+GND                          : N15       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                

+GND                          : N17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                

+GND                          : N19       : gnd    :                   :         :           :                

+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                

+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                

+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                

+GND                          : N26       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                

+GND                          : P1        : gnd    :                   :         :           :                

+GND                          : P2        : gnd    :                   :         :           :                

+DNU                          : P3        :        :                   :         :           :                

+DNU                          : P4        :        :                   :         :           :                

+GND                          : P5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                

+GND                          : P7        : gnd    :                   :         :           :                

+GND                          : P8        : gnd    :                   :         :           :                

+GND                          : P9        : gnd    :                   :         :           :                

+GND                          : P10       : gnd    :                   :         :           :                

+VCC                          : P11       : power  :                   : 1.1V    :           :                

+GND                          : P12       : gnd    :                   :         :           :                

+VCC                          : P13       : power  :                   : 1.1V    :           :                

+GND                          : P14       : gnd    :                   :         :           :                

+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                

+GND                          : P16       : gnd    :                   :         :           :                

+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                

+GND                          : P18       : gnd    :                   :         :           :                

+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                

+GND                          : P20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                

+GND                          : R1        : gnd    :                   :         :           :                

+GND                          : R2        : gnd    :                   :         :           :                

+GND                          : R3        : gnd    :                   :         :           :                

+GND                          : R4        : gnd    :                   :         :           :                

+VCC                          : R5        : power  :                   : 1.1V    :           :                

+GND                          : R6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                

+GND                          : R8        : gnd    :                   :         :           :                

+GND                          : R9        : gnd    :                   :         :           :                

+VCC                          : R10       : power  :                   : 1.1V    :           :                

+GND                          : R11       : gnd    :                   :         :           :                

+VCC                          : R12       : power  :                   : 1.1V    :           :                

+GND                          : R13       : gnd    :                   :         :           :                

+VCC                          : R14       : power  :                   : 1.1V    :           :                

+GND                          : R15       : gnd    :                   :         :           :                

+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                

+GND                          : R17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                

+GND                          : R30       : gnd    :                   :         :           :                

+GND                          : T1        : gnd    :                   :         :           :                

+GND                          : T2        : gnd    :                   :         :           :                

+DNU                          : T3        :        :                   :         :           :                

+DNU                          : T4        :        :                   :         :           :                

+GND                          : T5        : gnd    :                   :         :           :                

+VCC                          : T6        : power  :                   : 1.1V    :           :                

+GND                          : T7        : gnd    :                   :         :           :                

+GND                          : T8        : gnd    :                   :         :           :                

+GND                          : T9        : gnd    :                   :         :           :                

+GND                          : T10       : gnd    :                   :         :           :                

+VCC                          : T11       : power  :                   : 1.1V    :           :                

+GND                          : T12       : gnd    :                   :         :           :                

+VCC                          : T13       : power  :                   : 1.1V    :           :                

+GND                          : T14       : gnd    :                   :         :           :                

+GND                          : T15       : gnd    :                   :         :           :                

+GND                          : T16       : gnd    :                   :         :           :                

+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                

+GND                          : T18       : gnd    :                   :         :           :                

+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                

+GND                          : T20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                

+GND                          : T27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                

+GND                          : U1        : gnd    :                   :         :           :                

+GND                          : U2        : gnd    :                   :         :           :                

+GND                          : U3        : gnd    :                   :         :           :                

+GND                          : U4        : gnd    :                   :         :           :                

+VCC                          : U5        : power  :                   : 1.1V    :           :                

+GND                          : U6        : gnd    :                   :         :           :                

+DCLK                         : U7        :        :                   :         : 3A        :                

+TDI                          : U8        : input  :                   :         : 3A        :                

+GND                          : U9        : gnd    :                   :         :           :                

+VCC                          : U10       : power  :                   : 1.1V    :           :                

+GND                          : U11       : gnd    :                   :         :           :                

+VCC                          : U12       : power  :                   : 1.1V    :           :                

+GND                          : U13       : gnd    :                   :         :           :                

+VCC                          : U14       : power  :                   : 1.1V    :           :                

+GND                          : U15       : gnd    :                   :         :           :                

+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                

+GND                          : U17       : gnd    :                   :         :           :                

+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                

+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                

+VCC                          : U21       : power  :                   : 1.1V    :           :                

+GND                          : U22       : gnd    :                   :         :           :                

+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                

+GND                          : U24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                

+GND                          : U29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                

+GND                          : V1        : gnd    :                   :         :           :                

+GND                          : V2        : gnd    :                   :         :           :                

+DNU                          : V3        :        :                   :         :           :                

+DNU                          : V4        :        :                   :         :           :                

+GND                          : V5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                

+GND                          : V7        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                

+TMS                          : V9        : input  :                   :         : 3A        :                

+GND                          : V10       : gnd    :                   :         :           :                

+VCC                          : V11       : power  :                   : 1.1V    :           :                

+GND                          : V12       : gnd    :                   :         :           :                

+VCC                          : V13       : power  :                   : 1.1V    :           :                

+GND                          : V14       : gnd    :                   :         :           :                

+VCC                          : V15       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                

+GND                          : V19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                

+GND                          : V21       : gnd    :                   :         :           :                

+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                

+HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                

+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                

+GND                          : W1        : gnd    :                   :         :           :                

+GND                          : W2        : gnd    :                   :         :           :                

+GND                          : W3        : gnd    :                   :         :           :                

+GND                          : W4        : gnd    :                   :         :           :                

+VCC                          : W5        : power  :                   : 1.1V    :           :                

+GND                          : W6        : gnd    :                   :         :           :                

+GND                          : W7        : gnd    :                   :         :           :                

+GND                          : W8        : gnd    :                   :         :           :                

+GND                          : W9        : gnd    :                   :         :           :                

+VCC                          : W10       : power  :                   : 1.1V    :           :                

+GND                          : W11       : gnd    :                   :         :           :                

+VCC                          : W12       : power  :                   : 1.1V    :           :                

+GND                          : W13       : gnd    :                   :         :           :                

+VCC                          : W14       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                

+GND                          : W18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                

+HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                

+HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                

+GND                          : W28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                

+GND                          : Y1        : gnd    :                   :         :           :                

+GND                          : Y2        : gnd    :                   :         :           :                

+DNU                          : Y3        :        :                   :         :           :                

+DNU                          : Y4        :        :                   :         :           :                

+GND                          : Y5        : gnd    :                   :         :           :                

+VCC                          : Y6        : power  :                   : 1.1V    :           :                

+GND                          : Y7        : gnd    :                   :         :           :                

+GND                          : Y8        : gnd    :                   :         :           :                

+VCC                          : Y9        : power  :                   : 1.1V    :           :                

+GND                          : Y10       : gnd    :                   :         :           :                

+VCC                          : Y11       : power  :                   : 1.1V    :           :                

+GND                          : Y12       : gnd    :                   :         :           :                

+VCC                          : Y13       : power  :                   : 1.1V    :           :                

+GND                          : Y14       : gnd    :                   :         :           :                

+GND                          : Y15       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                

+GND                          : Y20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                

+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                

+HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : Y25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                

+GND                          : Y30       : gnd    :                   :         :           :                

diff --git a/part_2/ex6/output_files/ex6.sld b/part_2/ex6/output_files/ex6.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.sld
@@ -0,0 +1 @@
+<sld_project_info/>

diff --git a/part_2/ex6/output_files/ex6.sof b/part_2/ex6/output_files/ex6.sof
new file mode 100755
index 0000000..596fc0b
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.sof
diff --git a/part_2/ex6/output_files/ex6.sta.rpt b/part_2/ex6/output_files/ex6.sta.rpt
new file mode 100755
index 0000000..48220e4
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.sta.rpt
@@ -0,0 +1,839 @@
+TimeQuest Timing Analyzer report for ex6

+Tue Nov 22 11:43:46 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. TimeQuest Timing Analyzer Summary

+  3. Parallel Compilation

+  4. SDC File List

+  5. Clocks

+  6. Slow 1100mV 85C Model Fmax Summary

+  7. Timing Closure Recommendations

+  8. Slow 1100mV 85C Model Setup Summary

+  9. Slow 1100mV 85C Model Hold Summary

+ 10. Slow 1100mV 85C Model Recovery Summary

+ 11. Slow 1100mV 85C Model Removal Summary

+ 12. Slow 1100mV 85C Model Minimum Pulse Width Summary

+ 13. Slow 1100mV 85C Model Metastability Summary

+ 14. Slow 1100mV 0C Model Fmax Summary

+ 15. Slow 1100mV 0C Model Setup Summary

+ 16. Slow 1100mV 0C Model Hold Summary

+ 17. Slow 1100mV 0C Model Recovery Summary

+ 18. Slow 1100mV 0C Model Removal Summary

+ 19. Slow 1100mV 0C Model Minimum Pulse Width Summary

+ 20. Slow 1100mV 0C Model Metastability Summary

+ 21. Fast 1100mV 85C Model Setup Summary

+ 22. Fast 1100mV 85C Model Hold Summary

+ 23. Fast 1100mV 85C Model Recovery Summary

+ 24. Fast 1100mV 85C Model Removal Summary

+ 25. Fast 1100mV 85C Model Minimum Pulse Width Summary

+ 26. Fast 1100mV 85C Model Metastability Summary

+ 27. Fast 1100mV 0C Model Setup Summary

+ 28. Fast 1100mV 0C Model Hold Summary

+ 29. Fast 1100mV 0C Model Recovery Summary

+ 30. Fast 1100mV 0C Model Removal Summary

+ 31. Fast 1100mV 0C Model Minimum Pulse Width Summary

+ 32. Fast 1100mV 0C Model Metastability Summary

+ 33. Multicorner Timing Analysis Summary

+ 34. Board Trace Model Assignments

+ 35. Input Transition Times

+ 36. Signal Integrity Metrics (Slow 1100mv 0c Model)

+ 37. Signal Integrity Metrics (Slow 1100mv 85c Model)

+ 38. Signal Integrity Metrics (Fast 1100mv 0c Model)

+ 39. Signal Integrity Metrics (Fast 1100mv 85c Model)

+ 40. Setup Transfers

+ 41. Hold Transfers

+ 42. Report TCCS

+ 43. Report RSKM

+ 44. Unconstrained Paths Summary

+ 45. Clock Status Summary

+ 46. Unconstrained Input Ports

+ 47. Unconstrained Output Ports

+ 48. Unconstrained Input Ports

+ 49. Unconstrained Output Ports

+ 50. TimeQuest Timing Analyzer Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------------------------+

+; TimeQuest Timing Analyzer Summary                                               ;

++-----------------------+---------------------------------------------------------+

+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Timing Analyzer       ; TimeQuest                                               ;

+; Revision Name         ; ex6                                                     ;

+; Device Family         ; Cyclone V                                               ;

+; Device Name           ; 5CSEMA5F31C6                                            ;

+; Timing Models         ; Final                                                   ;

+; Delay Model           ; Combined                                                ;

+; Rise/Fall Delays      ; Enabled                                                 ;

++-----------------------+---------------------------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.10        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   3.2%      ;

+;     Processor 3            ;   3.2%      ;

+;     Processor 4            ;   3.2%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------+

+; SDC File List                                     ;

++---------------+--------+--------------------------+

+; SDC File Path ; Status ; Read at                  ;

++---------------+--------+--------------------------+

+; ex6.sdc       ; OK     ; Tue Nov 22 11:43:43 2016 ;

++---------------+--------+--------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Clocks                                                                                                                                                                               ;

++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+

+; Clock Name ; Type ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets      ;

++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+

+; CLOCK_50   ; Base ; 20.000 ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 } ;

++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+

+

+

++--------------------------------------------------+

+; Slow 1100mV 85C Model Fmax Summary               ;

++------------+-----------------+------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;

++------------+-----------------+------------+------+

+; 216.31 MHz ; 216.31 MHz      ; CLOCK_50   ;      ;

++------------+-----------------+------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

+----------------------------------

+; Timing Closure Recommendations ;

+----------------------------------

+HTML report is unavailable in plain text report export.

+

+

++-------------------------------------+

+; Slow 1100mV 85C Model Setup Summary ;

++----------+--------+-----------------+

+; Clock    ; Slack  ; End Point TNS   ;

++----------+--------+-----------------+

+; CLOCK_50 ; 15.377 ; 0.000           ;

++----------+--------+-----------------+

+

+

++------------------------------------+

+; Slow 1100mV 85C Model Hold Summary ;

++----------+-------+-----------------+

+; Clock    ; Slack ; End Point TNS   ;

++----------+-------+-----------------+

+; CLOCK_50 ; 0.388 ; 0.000           ;

++----------+-------+-----------------+

+

+

+------------------------------------------

+; Slow 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Slow 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++---------------------------------------------------+

+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;

++----------+-------+--------------------------------+

+; Clock    ; Slack ; End Point TNS                  ;

++----------+-------+--------------------------------+

+; CLOCK_50 ; 8.900 ; 0.000                          ;

++----------+-------+--------------------------------+

+

+

+-----------------------------------------------

+; Slow 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------+

+; Slow 1100mV 0C Model Fmax Summary                ;

++------------+-----------------+------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;

++------------+-----------------+------------+------+

+; 212.13 MHz ; 212.13 MHz      ; CLOCK_50   ;      ;

++------------+-----------------+------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

++------------------------------------+

+; Slow 1100mV 0C Model Setup Summary ;

++----------+--------+----------------+

+; Clock    ; Slack  ; End Point TNS  ;

++----------+--------+----------------+

+; CLOCK_50 ; 15.286 ; 0.000          ;

++----------+--------+----------------+

+

+

++-----------------------------------+

+; Slow 1100mV 0C Model Hold Summary ;

++----------+-------+----------------+

+; Clock    ; Slack ; End Point TNS  ;

++----------+-------+----------------+

+; CLOCK_50 ; 0.385 ; 0.000          ;

++----------+-------+----------------+

+

+

+-----------------------------------------

+; Slow 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Slow 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------+

+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;

++----------+-------+-------------------------------+

+; Clock    ; Slack ; End Point TNS                 ;

++----------+-------+-------------------------------+

+; CLOCK_50 ; 8.899 ; 0.000                         ;

++----------+-------+-------------------------------+

+

+

+----------------------------------------------

+; Slow 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++-------------------------------------+

+; Fast 1100mV 85C Model Setup Summary ;

++----------+--------+-----------------+

+; Clock    ; Slack  ; End Point TNS   ;

++----------+--------+-----------------+

+; CLOCK_50 ; 17.068 ; 0.000           ;

++----------+--------+-----------------+

+

+

++------------------------------------+

+; Fast 1100mV 85C Model Hold Summary ;

++----------+-------+-----------------+

+; Clock    ; Slack ; End Point TNS   ;

++----------+-------+-----------------+

+; CLOCK_50 ; 0.204 ; 0.000           ;

++----------+-------+-----------------+

+

+

+------------------------------------------

+; Fast 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Fast 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++---------------------------------------------------+

+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;

++----------+-------+--------------------------------+

+; Clock    ; Slack ; End Point TNS                  ;

++----------+-------+--------------------------------+

+; CLOCK_50 ; 8.836 ; 0.000                          ;

++----------+-------+--------------------------------+

+

+

+-----------------------------------------------

+; Fast 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++------------------------------------+

+; Fast 1100mV 0C Model Setup Summary ;

++----------+--------+----------------+

+; Clock    ; Slack  ; End Point TNS  ;

++----------+--------+----------------+

+; CLOCK_50 ; 17.237 ; 0.000          ;

++----------+--------+----------------+

+

+

++-----------------------------------+

+; Fast 1100mV 0C Model Hold Summary ;

++----------+-------+----------------+

+; Clock    ; Slack ; End Point TNS  ;

++----------+-------+----------------+

+; CLOCK_50 ; 0.194 ; 0.000          ;

++----------+-------+----------------+

+

+

+-----------------------------------------

+; Fast 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Fast 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------+

+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;

++----------+-------+-------------------------------+

+; Clock    ; Slack ; End Point TNS                 ;

++----------+-------+-------------------------------+

+; CLOCK_50 ; 8.806 ; 0.000                         ;

++----------+-------+-------------------------------+

+

+

+----------------------------------------------

+; Fast 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++------------------------------------------------------------------------------+

+; Multicorner Timing Analysis Summary                                          ;

++------------------+--------+-------+----------+---------+---------------------+

+; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;

++------------------+--------+-------+----------+---------+---------------------+

+; Worst-case Slack ; 15.286 ; 0.194 ; N/A      ; N/A     ; 8.806               ;

+;  CLOCK_50        ; 15.286 ; 0.194 ; N/A      ; N/A     ; 8.806               ;

+; Design-wide TNS  ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;

+;  CLOCK_50        ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;

++------------------+--------+-------+----------+---------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+

+

++-------------------------------------------------------------+

+; Input Transition Times                                      ;

++----------+--------------+-----------------+-----------------+

+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;

++----------+--------------+-----------------+-----------------+

+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

++----------+--------------+-----------------+-----------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++-------------------------------------------------------------------+

+; Setup Transfers                                                   ;

++------------+----------+----------+----------+----------+----------+

+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++------------+----------+----------+----------+----------+----------+

+; CLOCK_50   ; CLOCK_50 ; 289      ; 0        ; 0        ; 0        ;

++------------+----------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

++-------------------------------------------------------------------+

+; Hold Transfers                                                    ;

++------------+----------+----------+----------+----------+----------+

+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++------------+----------+----------+----------+----------+----------+

+; CLOCK_50   ; CLOCK_50 ; 289      ; 0        ; 0        ; 0        ;

++------------+----------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

+---------------

+; Report TCCS ;

+---------------

+No dedicated SERDES Transmitter circuitry present in device or used in design

+

+

+---------------

+; Report RSKM ;

+---------------

+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design

+

+

++------------------------------------------------+

+; Unconstrained Paths Summary                    ;

++---------------------------------+-------+------+

+; Property                        ; Setup ; Hold ;

++---------------------------------+-------+------+

+; Illegal Clocks                  ; 0     ; 0    ;

+; Unconstrained Clocks            ; 1     ; 1    ;

+; Unconstrained Input Ports       ; 2     ; 2    ;

+; Unconstrained Input Port Paths  ; 32    ; 32   ;

+; Unconstrained Output Ports      ; 35    ; 35   ;

+; Unconstrained Output Port Paths ; 483   ; 483  ;

++---------------------------------+-------+------+

+

+

++----------------------------------------------------------+

+; Clock Status Summary                                     ;

++------------------------+----------+------+---------------+

+; Target                 ; Clock    ; Type ; Status        ;

++------------------------+----------+------+---------------+

+; CLOCK_50               ; CLOCK_50 ; Base ; Constrained   ;

+; tick_50000:tck|CLK_OUT ;          ; Base ; Unconstrained ;

++------------------------+----------+------+---------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; KEY[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; KEY[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++------------------------------------+

+; TimeQuest Timing Analyzer Messages ;

++------------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime TimeQuest Timing Analyzer

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Tue Nov 22 11:43:41 2016

+Info: Command: quartus_sta ex6 -c ex6

+Info: qsta_default_script.tcl version: #1

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Info (332104): Reading SDC File: 'ex6.sdc'

+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.

+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON

+Info: Analyzing Slow 1100mV 85C Model

+Info (332146): Worst-case setup slack is 15.377

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    15.377               0.000 CLOCK_50 

+Info (332146): Worst-case hold slack is 0.388

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.388               0.000 CLOCK_50 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is 8.900

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     8.900               0.000 CLOCK_50 

+Info: Analyzing Slow 1100mV 0C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.

+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332146): Worst-case setup slack is 15.286

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    15.286               0.000 CLOCK_50 

+Info (332146): Worst-case hold slack is 0.385

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.385               0.000 CLOCK_50 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is 8.899

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     8.899               0.000 CLOCK_50 

+Info: Analyzing Fast 1100mV 85C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.

+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332146): Worst-case setup slack is 17.068

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    17.068               0.000 CLOCK_50 

+Info (332146): Worst-case hold slack is 0.204

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.204               0.000 CLOCK_50 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is 8.836

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     8.836               0.000 CLOCK_50 

+Info: Analyzing Fast 1100mV 0C Model

+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.

+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332146): Worst-case setup slack is 17.237

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    17.237               0.000 CLOCK_50 

+Info (332146): Worst-case hold slack is 0.194

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.194               0.000 CLOCK_50 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is 8.806

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     8.806               0.000 CLOCK_50 

+Info (332102): Design is not fully constrained for setup requirements

+Info (332102): Design is not fully constrained for hold requirements

+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings

+    Info: Peak virtual memory: 1209 megabytes

+    Info: Processing ended: Tue Nov 22 11:43:46 2016

+    Info: Elapsed time: 00:00:05

+    Info: Total CPU time (on all processors): 00:00:05

+

+

diff --git a/part_2/ex6/output_files/ex6.sta.summary b/part_2/ex6/output_files/ex6.sta.summary
new file mode 100755
index 0000000..d09b990
--- /dev/null
+++ b/part_2/ex6/output_files/ex6.sta.summary
@@ -0,0 +1,53 @@
+------------------------------------------------------------

+TimeQuest Timing Analyzer Summary

+------------------------------------------------------------

+

+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'

+Slack : 15.377

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'

+Slack : 0.388

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : 8.900

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'

+Slack : 15.286

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'

+Slack : 0.385

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : 8.899

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'

+Slack : 17.068

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'

+Slack : 0.204

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : 8.836

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'

+Slack : 17.237

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'

+Slack : 0.194

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : 8.806

+TNS   : 0.000

+

+------------------------------------------------------------

diff --git a/part_2/ex6/verilog_files/add3_ge5.v b/part_2/ex6/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..65a561d
--- /dev/null
+++ b/part_2/ex6/verilog_files/add3_ge5.v
@@ -0,0 +1,25 @@
+module add3_ge5(w,a);

+	output [3:0] a;

+	input [3:0] w;

+	

+	reg [3:0] a;

+	

+	always @ (w)

+		case(w)

+			4'b0000: a <= 4'b0000;

+			4'b0001: a <= 4'b0001;

+			4'b0010: a <= 4'b0010;

+			4'b0011: a <= 4'b0011;

+			4'b0100: a <= 4'b0100;

+			4'b0101: a <= 4'b1000;

+			4'b0110: a <= 4'b1001;

+			4'b0111: a <= 4'b1010;

+			4'b1000: a <= 4'b1011;

+			4'b1001: a <= 4'b1100;

+			4'b1010: a <= 4'b1101;

+			4'b1011: a <= 4'b1110;

+			4'b1100: a <= 4'b1111;

+			

+			default: a <= 4'b0000;

+		endcase

+endmodule

diff --git a/part_2/ex6/verilog_files/bin2bcd_16.v b/part_2/ex6/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..fdfb655
--- /dev/null
+++ b/part_2/ex6/verilog_files/bin2bcd_16.v
@@ -0,0 +1,97 @@
+//------------------------------

+// Module name: bin2bcd_16

+// Function: Converts a 16-bit binary number to 5 digits BCD

+//            .... it uses a shift-and-add3 algorithm

+// Creator:  Peter Cheung

+// Version:  1.0

+// Date:     18 Sept 2016

+//------------------------------

+//   For more explanation of how this work, see 

+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment

+

+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+

+	input [15:0]	B;		// binary input number

+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD

+	

+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;

+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;

+	wire [3:0]	w26,w27,w28,w29;

+	wire [3:0]	a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;

+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;

+	wire [3:0]	a26,a27,a28,a29;

+

+	// Instantiate a tree of add3-if-greater than or equal to 5 cells

+	//  ... input is w_n, and output is a_n

+	add3_ge5 A1 (w1,a1);

+	add3_ge5 A2 (w2,a2);

+	add3_ge5 A3 (w3,a3);

+	add3_ge5 A4 (w4,a4);

+	add3_ge5 A5 (w5,a5);

+	add3_ge5 A6 (w6,a6);

+	add3_ge5 A7 (w7,a7);

+	add3_ge5 A8 (w8,a8);

+	add3_ge5 A9 (w9,a9);

+	add3_ge5 A10 (w10,a10);

+	add3_ge5 A11 (w11,a11);

+	add3_ge5 A12 (w12,a12);

+	add3_ge5 A13 (w13,a13);

+	add3_ge5 A14 (w14,a14);

+	add3_ge5 A15 (w15,a15);

+	add3_ge5 A16 (w16,a16);

+	add3_ge5 A17 (w17,a17);

+	add3_ge5 A18 (w18,a18);

+	add3_ge5 A19 (w19,a19);

+	add3_ge5 A20 (w20,a20);

+	add3_ge5 A21 (w21,a21);

+	add3_ge5 A22 (w22,a22);

+	add3_ge5 A23 (w23,a23);

+	add3_ge5 A24 (w24,a24);

+	add3_ge5 A25 (w25,a25);

+	add3_ge5 A26 (w26,a26);

+	add3_ge5 A27 (w27,a27);

+	add3_ge5 A28 (w28,a28);

+	add3_ge5 A29 (w29,a29);

+		

+	// wire the tree of add3 modules together

+	assign  w1 = {B[14:11]};		// wn is the input port to module An

+	assign  w2 = {a1[2:0], B[10]};

+	assign  w3 = {1'b0, B[15], a1[3], a2[3]};

+	assign  w4 = {a2[2:0], B[9]};

+	assign  w5 = {a3[2:0], a4[3]};

+	assign  w6 = {a4[2:0], B[8]};

+	assign  w7 = {a5[2:0], a6[3]};

+	assign  w8 = {a6[2:0], B[7]};

+	assign  w9 = {1'b0, a3[3], a5[3], a7[3]};

+	assign  w10 = {a7[2:0], a8[3]};

+	assign  w11 = {a8[2:0], B[6]};

+	assign  w12 = {a9[2:0], a10[3]};

+	assign  w13 = {a10[2:0], a11[3]};

+	assign  w14 = {a11[2:0], B[5]};

+	assign  w15 = {a12[2:0], a13[3]};

+	assign  w16 = {a13[2:0], a14[3]};

+	assign  w17 = {a14[2:0], B[4]};

+	assign  w18 = {1'b0, a9[3], a12[3], a15[3]};

+	assign  w19 = {a15[2:0], a16[3]};

+	assign  w20 = {a16[2:0], a17[3]};

+	assign  w21 = {a17[2:0], B[3]};

+	assign  w22 = {a18[2:0], a19[3]};

+	assign  w23 = {a19[2:0], a20[3]};

+	assign  w24 = {a20[2:0], a21[3]};

+	assign  w25 = {a21[2:0], B[2]};

+	assign  w26 = {a22[2:0], a23[3]};

+	assign  w27 = {a23[2:0], a24[3]};

+	assign  w28 = {a24[2:0], a25[3]};

+	assign  w29 = {a25[2:0], B[1]};

+	

+	// connect up to four BCD digit outputs	

+	assign BCD_0 = {a29[2:0],B[0]};

+	assign BCD_1 = {a28[2:0],a29[3]};

+	assign BCD_2 = {a27[2:0],a28[3]};

+	assign BCD_3 = {a26[2:0],a27[3]};

+	assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};	

+endmodule

+

+	

+	

+

diff --git a/part_2/ex6/verilog_files/counter_16.v b/part_2/ex6/verilog_files/counter_16.v
new file mode 100755
index 0000000..c0ec549
--- /dev/null
+++ b/part_2/ex6/verilog_files/counter_16.v
@@ -0,0 +1,21 @@
+`timescale 1ns / 100ps

+

+module counter_16(clock,enable,reset,count);

+

+	parameter BIT_SZ = 16;

+	input clock, enable, reset;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		begin

+			if(enable == 1'b1)

+				count <= count + 1'b1;

+			if(reset == 1'b1)

+				count <= 16'b0;

+		end

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex6/verilog_files/counter_16.v.bak b/part_2/ex6/verilog_files/counter_16.v.bak
new file mode 100755
index 0000000..61bc861
--- /dev/null
+++ b/part_2/ex6/verilog_files/counter_16.v.bak
@@ -0,0 +1,18 @@
+`timescale 1ns / 100ps

+

+module counter_8(clock,enable,count);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex6/verilog_files/hex_to_7seg.v b/part_2/ex6/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/ex6/verilog_files/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/ex6/verilog_files/tick_50000.v b/part_2/ex6/verilog_files/tick_50000.v
new file mode 100755
index 0000000..45c4166
--- /dev/null
+++ b/part_2/ex6/verilog_files/tick_50000.v
@@ -0,0 +1,31 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd24999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= ~CLK_OUT;

+					count <= 16'd24999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex6/verilog_files/tick_50000.v.bak b/part_2/ex6/verilog_files/tick_50000.v.bak
new file mode 100755
index 0000000..8856c69
--- /dev/null
+++ b/part_2/ex6/verilog_files/tick_50000.v.bak
@@ -0,0 +1,32 @@
+module tick_50000(CLOCK_50, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_50;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd49999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_50)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= 1'b1;

+					count <= 1'd49999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+					CLK_OUT <= 1'b0;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex7/c5_pin_model_dump.txt b/part_2/ex7/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_2/ex7/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2

+io_4iomodule_c5_index: 54gpio_index: 465

+io_4iomodule_c5_index: 33gpio_index: 6

+io_4iomodule_c5_index: 51gpio_index: 461

+io_4iomodule_c5_index: 27gpio_index: 10

+io_4iomodule_c5_index: 57gpio_index: 457

+io_4iomodule_c5_index: 34gpio_index: 14

+io_4iomodule_c5_index: 28gpio_index: 453

+io_4iomodule_c5_index: 26gpio_index: 19

+io_4iomodule_c5_index: 47gpio_index: 449

+io_4iomodule_c5_index: 29gpio_index: 22

+io_4iomodule_c5_index: 3gpio_index: 445

+io_4iomodule_c5_index: 16gpio_index: 27

+io_4iomodule_c5_index: 6gpio_index: 441

+io_4iomodule_c5_index: 50gpio_index: 30

+io_4iomodule_c5_index: 35gpio_index: 437

+io_4iomodule_c5_index: 7gpio_index: 35

+io_4iomodule_c5_index: 53gpio_index: 433

+io_4iomodule_c5_index: 12gpio_index: 38

+io_4iomodule_c5_index: 1gpio_index: 429

+io_4iomodule_c5_index: 22gpio_index: 43

+io_4iomodule_c5_index: 8gpio_index: 425

+io_4iomodule_c5_index: 20gpio_index: 46

+io_4iomodule_c5_index: 30gpio_index: 421

+io_4iomodule_c5_index: 2gpio_index: 51

+io_4iomodule_c5_index: 31gpio_index: 417

+io_4iomodule_c5_index: 39gpio_index: 54

+io_4iomodule_c5_index: 18gpio_index: 413

+io_4iomodule_c5_index: 10gpio_index: 59

+io_4iomodule_c5_index: 42gpio_index: 409

+io_4iomodule_c5_index: 5gpio_index: 62

+io_4iomodule_c5_index: 24gpio_index: 405

+io_4iomodule_c5_index: 37gpio_index: 67

+io_4iomodule_c5_index: 13gpio_index: 401

+io_4iomodule_c5_index: 0gpio_index: 70

+io_4iomodule_c5_index: 44gpio_index: 397

+io_4iomodule_c5_index: 38gpio_index: 75

+io_4iomodule_c5_index: 52gpio_index: 393

+io_4iomodule_c5_index: 32gpio_index: 78

+io_4iomodule_c5_index: 56gpio_index: 389

+io_4iomodule_a_index: 13gpio_index: 385

+io_4iomodule_c5_index: 4gpio_index: 83

+io_4iomodule_c5_index: 23gpio_index: 86

+io_4iomodule_a_index: 15gpio_index: 381

+io_4iomodule_a_index: 8gpio_index: 377

+io_4iomodule_c5_index: 46gpio_index: 91

+io_4iomodule_a_index: 5gpio_index: 373

+io_4iomodule_a_index: 11gpio_index: 369

+io_4iomodule_c5_index: 41gpio_index: 94

+io_4iomodule_a_index: 3gpio_index: 365

+io_4iomodule_c5_index: 25gpio_index: 99

+io_4iomodule_a_index: 7gpio_index: 361

+io_4iomodule_c5_index: 9gpio_index: 102

+io_4iomodule_a_index: 0gpio_index: 357

+io_4iomodule_c5_index: 14gpio_index: 107

+io_4iomodule_a_index: 12gpio_index: 353

+io_4iomodule_c5_index: 45gpio_index: 110

+io_4iomodule_c5_index: 17gpio_index: 115

+io_4iomodule_a_index: 4gpio_index: 349

+io_4iomodule_c5_index: 36gpio_index: 118

+io_4iomodule_a_index: 10gpio_index: 345

+io_4iomodule_a_index: 16gpio_index: 341

+io_4iomodule_c5_index: 15gpio_index: 123

+io_4iomodule_a_index: 14gpio_index: 337

+io_4iomodule_c5_index: 43gpio_index: 126

+io_4iomodule_c5_index: 19gpio_index: 131

+io_4iomodule_a_index: 1gpio_index: 333

+io_4iomodule_c5_index: 59gpio_index: 134

+io_4iomodule_a_index: 2gpio_index: 329

+io_4iomodule_a_index: 9gpio_index: 325

+io_4iomodule_c5_index: 48gpio_index: 139

+io_4iomodule_a_index: 6gpio_index: 321

+io_4iomodule_a_index: 17gpio_index: 317

+io_4iomodule_c5_index: 40gpio_index: 142

+io_4iomodule_c5_index: 11gpio_index: 147

+io_4iomodule_c5_index: 58gpio_index: 150

+io_4iomodule_c5_index: 21gpio_index: 155

+io_4iomodule_c5_index: 49gpio_index: 158

+io_4iomodule_h_c5_index: 0gpio_index: 161

+io_4iomodule_h_c5_index: 6gpio_index: 165

+io_4iomodule_h_c5_index: 10gpio_index: 169

+io_4iomodule_h_c5_index: 3gpio_index: 173

+io_4iomodule_h_c5_index: 8gpio_index: 176

+io_4iomodule_h_c5_index: 11gpio_index: 180

+io_4iomodule_h_c5_index: 7gpio_index: 184

+io_4iomodule_h_c5_index: 5gpio_index: 188

+io_4iomodule_h_c5_index: 1gpio_index: 192

+io_4iomodule_h_c5_index: 2gpio_index: 196

+io_4iomodule_h_c5_index: 9gpio_index: 200

+io_4iomodule_h_c5_index: 4gpio_index: 204

+io_4iomodule_h_index: 15gpio_index: 208

+io_4iomodule_h_index: 1gpio_index: 212

+io_4iomodule_h_index: 3gpio_index: 216

+io_4iomodule_h_index: 2gpio_index: 220

+io_4iomodule_h_index: 11gpio_index: 224

+io_4iomodule_vref_h_index: 1gpio_index: 228

+io_4iomodule_h_index: 20gpio_index: 231

+io_4iomodule_h_index: 8gpio_index: 235

+io_4iomodule_h_index: 6gpio_index: 239

+io_4iomodule_h_index: 10gpio_index: 243

+io_4iomodule_h_index: 23gpio_index: 247

+io_4iomodule_h_index: 7gpio_index: 251

+io_4iomodule_h_index: 22gpio_index: 255

+io_4iomodule_h_index: 5gpio_index: 259

+io_4iomodule_h_index: 24gpio_index: 263

+io_4iomodule_h_index: 0gpio_index: 267

+io_4iomodule_h_index: 13gpio_index: 271

+io_4iomodule_h_index: 21gpio_index: 275

+io_4iomodule_h_index: 16gpio_index: 279

+io_4iomodule_vref_h_index: 0gpio_index: 283

+io_4iomodule_h_index: 12gpio_index: 286

+io_4iomodule_h_index: 4gpio_index: 290

+io_4iomodule_h_index: 19gpio_index: 294

+io_4iomodule_h_index: 18gpio_index: 298

+io_4iomodule_h_index: 17gpio_index: 302

+io_4iomodule_h_index: 25gpio_index: 306

+io_4iomodule_h_index: 14gpio_index: 310

+io_4iomodule_h_index: 9gpio_index: 314

diff --git a/part_2/ex7/db/.cmp.kpt b/part_2/ex7/db/.cmp.kpt
new file mode 100755
index 0000000..7fc2356
--- /dev/null
+++ b/part_2/ex7/db/.cmp.kpt
diff --git a/part_2/ex7/db/ex7.(0).cnf.cdb b/part_2/ex7/db/ex7.(0).cnf.cdb
new file mode 100755
index 0000000..d6688fc
--- /dev/null
+++ b/part_2/ex7/db/ex7.(0).cnf.cdb
diff --git a/part_2/ex7/db/ex7.(0).cnf.hdb b/part_2/ex7/db/ex7.(0).cnf.hdb
new file mode 100755
index 0000000..8d0c147
--- /dev/null
+++ b/part_2/ex7/db/ex7.(0).cnf.hdb
diff --git a/part_2/ex7/db/ex7.(1).cnf.cdb b/part_2/ex7/db/ex7.(1).cnf.cdb
new file mode 100755
index 0000000..b5d62e0
--- /dev/null
+++ b/part_2/ex7/db/ex7.(1).cnf.cdb
diff --git a/part_2/ex7/db/ex7.(1).cnf.hdb b/part_2/ex7/db/ex7.(1).cnf.hdb
new file mode 100755
index 0000000..6819743
--- /dev/null
+++ b/part_2/ex7/db/ex7.(1).cnf.hdb
diff --git a/part_2/ex7/db/ex7.(2).cnf.cdb b/part_2/ex7/db/ex7.(2).cnf.cdb
new file mode 100755
index 0000000..76f39c4
--- /dev/null
+++ b/part_2/ex7/db/ex7.(2).cnf.cdb
diff --git a/part_2/ex7/db/ex7.(2).cnf.hdb b/part_2/ex7/db/ex7.(2).cnf.hdb
new file mode 100755
index 0000000..389562b
--- /dev/null
+++ b/part_2/ex7/db/ex7.(2).cnf.hdb
diff --git a/part_2/ex7/db/ex7.asm.qmsg b/part_2/ex7/db/ex7.asm.qmsg
new file mode 100755
index 0000000..c2ecfc4
--- /dev/null
+++ b/part_2/ex7/db/ex7.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479819059071 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479819059073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 12:50:58 2016 " "Processing started: Tue Nov 22 12:50:58 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479819059073 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479819059073 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex7 -c ex7 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex7 -c ex7" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479819059073 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479819059806 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479819064272 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "892 " "Peak virtual memory: 892 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479819064603 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:51:04 2016 " "Processing ended: Tue Nov 22 12:51:04 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479819064603 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479819064603 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479819064603 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479819064603 ""}

diff --git a/part_2/ex7/db/ex7.asm.rdb b/part_2/ex7/db/ex7.asm.rdb
new file mode 100755
index 0000000..602f8f4
--- /dev/null
+++ b/part_2/ex7/db/ex7.asm.rdb
diff --git a/part_2/ex7/db/ex7.cmp.ammdb b/part_2/ex7/db/ex7.cmp.ammdb
new file mode 100755
index 0000000..7abf2d7
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp.ammdb
diff --git a/part_2/ex7/db/ex7.cmp.bpm b/part_2/ex7/db/ex7.cmp.bpm
new file mode 100755
index 0000000..c2f66db
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp.bpm
diff --git a/part_2/ex7/db/ex7.cmp.cdb b/part_2/ex7/db/ex7.cmp.cdb
new file mode 100755
index 0000000..c73071b
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp.cdb
diff --git a/part_2/ex7/db/ex7.cmp.hdb b/part_2/ex7/db/ex7.cmp.hdb
new file mode 100755
index 0000000..2b17dbc
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp.hdb
diff --git a/part_2/ex7/db/ex7.cmp.idb b/part_2/ex7/db/ex7.cmp.idb
new file mode 100755
index 0000000..3851dfd
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp.idb
diff --git a/part_2/ex7/db/ex7.cmp.logdb b/part_2/ex7/db/ex7.cmp.logdb
new file mode 100755
index 0000000..3f5fb66
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp.logdb
@@ -0,0 +1,54 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,15;0;15;0;0;15;15;0;15;15;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,0;15;0;15;15;0;0;15;0;0;15;15;15;15;15;15;15;15;15;15;15;15;15;15;15;15;15;15,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex7/db/ex7.cmp.rdb b/part_2/ex7/db/ex7.cmp.rdb
new file mode 100755
index 0000000..205da99
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp.rdb
diff --git a/part_2/ex7/db/ex7.cmp_merge.kpt b/part_2/ex7/db/ex7.cmp_merge.kpt
new file mode 100755
index 0000000..69cec94
--- /dev/null
+++ b/part_2/ex7/db/ex7.cmp_merge.kpt
diff --git a/part_2/ex7/db/ex7.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..da61997
--- /dev/null
+++ b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex7/db/ex7.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex7/db/ex7.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex7/db/ex7.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..acc52a8
--- /dev/null
+++ b/part_2/ex7/db/ex7.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex7/db/ex7.db_info b/part_2/ex7/db/ex7.db_info
new file mode 100755
index 0000000..fbc85b2
--- /dev/null
+++ b/part_2/ex7/db/ex7.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Tue Nov 22 11:46:43 2016

diff --git a/part_2/ex7/db/ex7.fit.qmsg b/part_2/ex7/db/ex7.fit.qmsg
new file mode 100755
index 0000000..47046cb
--- /dev/null
+++ b/part_2/ex7/db/ex7.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479819030818 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479819030819 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex7 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex7\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479819031075 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479819031136 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479819031136 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479819031522 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479819031658 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479819041587 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "KEY3~inputCLKENA0 7 global CLKCTRL_G6 " "KEY3~inputCLKENA0 with 7 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479819041640 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479819041640 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479819041640 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479819041641 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479819041642 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479819041642 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479819041642 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479819041642 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479819041642 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479819041643 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479819041643 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479819041643 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479819041662 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479819041662 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479819041664 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex7.sdc " "Synopsys Design Constraints File file not found: 'ex7.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479819047196 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479819047197 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479819047198 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479819047198 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479819047199 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479819047201 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479819047270 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479819047674 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479819048031 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479819048536 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479819048536 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479819049156 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex7/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479819053446 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479819053446 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479819053748 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479819053748 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479819053753 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479819054584 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479819054618 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479819054895 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479819054896 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479819055166 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479819057104 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479819057330 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex7/output_files/ex7.fit.smsg " "Generated suppressed messages file C:/New folder/ex7/output_files/ex7.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479819057378 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 71 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 71 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2552 " "Peak virtual memory: 2552 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479819057749 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:50:57 2016 " "Processing ended: Tue Nov 22 12:50:57 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479819057749 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479819057749 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479819057749 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479819057749 ""}

diff --git a/part_2/ex7/db/ex7.hier_info b/part_2/ex7/db/ex7.hier_info
new file mode 100755
index 0000000..0f3f3ef
--- /dev/null
+++ b/part_2/ex7/db/ex7.hier_info
@@ -0,0 +1,63 @@
+|ex7

+KEY3 => KEY3.IN1

+HEX0[0] << hex_to_7seg:h0.port0

+HEX0[1] << hex_to_7seg:h0.port0

+HEX0[2] << hex_to_7seg:h0.port0

+HEX0[3] << hex_to_7seg:h0.port0

+HEX0[4] << hex_to_7seg:h0.port0

+HEX0[5] << hex_to_7seg:h0.port0

+HEX0[6] << hex_to_7seg:h0.port0

+HEX1[0] << hex_to_7seg:h1.port0

+HEX1[1] << hex_to_7seg:h1.port0

+HEX1[2] << hex_to_7seg:h1.port0

+HEX1[3] << hex_to_7seg:h1.port0

+HEX1[4] << hex_to_7seg:h1.port0

+HEX1[5] << hex_to_7seg:h1.port0

+HEX1[6] << hex_to_7seg:h1.port0

+

+

+|ex7|LFSR:comb_3

+CLK => COUNT[1]~reg0.CLK

+CLK => COUNT[2]~reg0.CLK

+CLK => COUNT[3]~reg0.CLK

+CLK => COUNT[4]~reg0.CLK

+CLK => COUNT[5]~reg0.CLK

+CLK => COUNT[6]~reg0.CLK

+CLK => COUNT[7]~reg0.CLK

+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex7|hex_to_7seg:h0

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex7|hex_to_7seg:h1

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

diff --git a/part_2/ex7/db/ex7.hif b/part_2/ex7/db/ex7.hif
new file mode 100755
index 0000000..28f653f
--- /dev/null
+++ b/part_2/ex7/db/ex7.hif
diff --git a/part_2/ex7/db/ex7.lpc.html b/part_2/ex7/db/ex7.lpc.html
new file mode 100755
index 0000000..aac7d6f
--- /dev/null
+++ b/part_2/ex7/db/ex7.lpc.html
@@ -0,0 +1,66 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+<TR >

+<TD >h1</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >h0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >comb_3</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+</TABLE>

diff --git a/part_2/ex7/db/ex7.lpc.rdb b/part_2/ex7/db/ex7.lpc.rdb
new file mode 100755
index 0000000..4f7a9a7
--- /dev/null
+++ b/part_2/ex7/db/ex7.lpc.rdb
diff --git a/part_2/ex7/db/ex7.lpc.txt b/part_2/ex7/db/ex7.lpc.txt
new file mode 100755
index 0000000..8b24978
--- /dev/null
+++ b/part_2/ex7/db/ex7.lpc.txt
@@ -0,0 +1,9 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; h1        ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; h0        ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; comb_3    ; 1     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex7/db/ex7.map.ammdb b/part_2/ex7/db/ex7.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.ammdb
diff --git a/part_2/ex7/db/ex7.map.bpm b/part_2/ex7/db/ex7.map.bpm
new file mode 100755
index 0000000..9eb9d60
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.bpm
diff --git a/part_2/ex7/db/ex7.map.cdb b/part_2/ex7/db/ex7.map.cdb
new file mode 100755
index 0000000..05833b4
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.cdb
diff --git a/part_2/ex7/db/ex7.map.hdb b/part_2/ex7/db/ex7.map.hdb
new file mode 100755
index 0000000..7901d68
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.hdb
diff --git a/part_2/ex7/db/ex7.map.kpt b/part_2/ex7/db/ex7.map.kpt
new file mode 100755
index 0000000..0ccdbdc
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.kpt
diff --git a/part_2/ex7/db/ex7.map.logdb b/part_2/ex7/db/ex7.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex7/db/ex7.map.qmsg b/part_2/ex7/db/ex7.map.qmsg
new file mode 100755
index 0000000..42adf06
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.qmsg
@@ -0,0 +1,18 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479819019324 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479819019327 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 12:50:18 2016 " "Processing started: Tue Nov 22 12:50:18 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479819019327 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479819019327 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex7 -c ex7 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex7 -c ex7" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479819019327 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479819019804 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479819019804 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex7/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479819028330 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479819028330 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex7/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479819028333 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479819028333 ""}

+{ "Warning" "WSGN_SEARCH_FILE" "ex7.v 1 1 " "Using design file ex7.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ex7 " "Found entity 1: ex7" {  } { { "ex7.v" "" { Text "C:/New folder/ex7/ex7.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479819028369 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1479819028369 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex7.v(8) " "Verilog HDL Instantiation warning at ex7.v(8): instance has no name" {  } { { "ex7.v" "" { Text "C:/New folder/ex7/ex7.v" 8 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479819028370 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex7 " "Elaborating entity \"ex7\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479819028371 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:comb_3 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:comb_3\"" {  } { { "ex7.v" "comb_3" { Text "C:/New folder/ex7/ex7.v" 8 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479819028372 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:h0\"" {  } { { "ex7.v" "h0" { Text "C:/New folder/ex7/ex7.v" 10 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479819028377 ""}

+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "count\[7\] " "Net \"count\[7\]\" is missing source, defaulting to GND" {  } { { "ex7.v" "count\[7\]" { Text "C:/New folder/ex7/ex7.v" 6 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1479819028384 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1479819028384 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1479819028748 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479819028827 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479819029076 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479819029076 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "36 " "Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479819029101 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479819029101 ""} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Implemented 21 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479819029101 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479819029101 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479819029111 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:50:29 2016 " "Processing ended: Tue Nov 22 12:50:29 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479819029111 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479819029111 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479819029111 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479819029111 ""}

diff --git a/part_2/ex7/db/ex7.map.rdb b/part_2/ex7/db/ex7.map.rdb
new file mode 100755
index 0000000..8ebbd5a
--- /dev/null
+++ b/part_2/ex7/db/ex7.map.rdb
diff --git a/part_2/ex7/db/ex7.map_bb.cdb b/part_2/ex7/db/ex7.map_bb.cdb
new file mode 100755
index 0000000..9e6fed1
--- /dev/null
+++ b/part_2/ex7/db/ex7.map_bb.cdb
diff --git a/part_2/ex7/db/ex7.map_bb.hdb b/part_2/ex7/db/ex7.map_bb.hdb
new file mode 100755
index 0000000..0e81eb2
--- /dev/null
+++ b/part_2/ex7/db/ex7.map_bb.hdb
diff --git a/part_2/ex7/db/ex7.map_bb.logdb b/part_2/ex7/db/ex7.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex7/db/ex7.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex7/db/ex7.pre_map.hdb b/part_2/ex7/db/ex7.pre_map.hdb
new file mode 100755
index 0000000..8b7c1dc
--- /dev/null
+++ b/part_2/ex7/db/ex7.pre_map.hdb
diff --git a/part_2/ex7/db/ex7.root_partition.map.reg_db.cdb b/part_2/ex7/db/ex7.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..0aeb3f7
--- /dev/null
+++ b/part_2/ex7/db/ex7.root_partition.map.reg_db.cdb
diff --git a/part_2/ex7/db/ex7.routing.rdb b/part_2/ex7/db/ex7.routing.rdb
new file mode 100755
index 0000000..0b9dd7d
--- /dev/null
+++ b/part_2/ex7/db/ex7.routing.rdb
diff --git a/part_2/ex7/db/ex7.rtlv.hdb b/part_2/ex7/db/ex7.rtlv.hdb
new file mode 100755
index 0000000..4a9b032
--- /dev/null
+++ b/part_2/ex7/db/ex7.rtlv.hdb
diff --git a/part_2/ex7/db/ex7.rtlv_sg.cdb b/part_2/ex7/db/ex7.rtlv_sg.cdb
new file mode 100755
index 0000000..398ce4d
--- /dev/null
+++ b/part_2/ex7/db/ex7.rtlv_sg.cdb
diff --git a/part_2/ex7/db/ex7.rtlv_sg_swap.cdb b/part_2/ex7/db/ex7.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..3eaf494
--- /dev/null
+++ b/part_2/ex7/db/ex7.rtlv_sg_swap.cdb
diff --git a/part_2/ex7/db/ex7.sld_design_entry.sci b/part_2/ex7/db/ex7.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex7/db/ex7.sld_design_entry.sci
diff --git a/part_2/ex7/db/ex7.sld_design_entry_dsc.sci b/part_2/ex7/db/ex7.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex7/db/ex7.sld_design_entry_dsc.sci
diff --git a/part_2/ex7/db/ex7.smart_action.txt b/part_2/ex7/db/ex7.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex7/db/ex7.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex7/db/ex7.sta.qmsg b/part_2/ex7/db/ex7.sta.qmsg
new file mode 100755
index 0000000..2254c56
--- /dev/null
+++ b/part_2/ex7/db/ex7.sta.qmsg
@@ -0,0 +1,52 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479819066037 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479819066038 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 12:51:05 2016 " "Processing started: Tue Nov 22 12:51:05 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479819066038 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819066038 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex7 -c ex7 " "Command: quartus_sta ex7 -c ex7" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819066038 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479819066162 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819066676 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819066676 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819066724 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819066724 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex7.sdc " "Synopsys Design Constraints File file not found: 'ex7.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067226 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067226 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name KEY3 KEY3 " "create_clock -period 1.000 -name KEY3 KEY3" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1479819067227 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067227 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067227 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067227 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479819067228 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479819067235 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479819067240 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067240 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.082 " "Worst-case setup slack is -0.082" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.082              -0.115 KEY3  " "   -0.082              -0.115 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067241 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067241 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.347 " "Worst-case hold slack is 0.347" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.347               0.000 KEY3  " "    0.347               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067243 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067243 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067245 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067246 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.394 " "Worst-case minimum pulse width slack is -0.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.179 KEY3  " "   -0.394              -5.179 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067248 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067248 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479819067251 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067283 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067822 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067854 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479819067857 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067857 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.127 " "Worst-case setup slack is -0.127" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067858 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067858 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.127              -0.175 KEY3  " "   -0.127              -0.175 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067858 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067858 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.326 " "Worst-case hold slack is 0.326" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067860 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067860 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.326               0.000 KEY3  " "    0.326               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067860 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067860 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067862 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067863 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.394 " "Worst-case minimum pulse width slack is -0.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.505 KEY3  " "   -0.394              -5.505 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819067864 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067864 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479819067867 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819067998 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068432 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068465 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.377 " "Worst-case setup slack is 0.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068467 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068467 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.377               0.000 KEY3  " "    0.377               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068467 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068467 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.197 " "Worst-case hold slack is 0.197" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068469 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068469 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.197               0.000 KEY3  " "    0.197               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068469 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068469 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068470 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068472 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479819068472 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068472 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.085 " "Worst-case minimum pulse width slack is -0.085" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068473 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068473 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.085              -0.831 KEY3  " "   -0.085              -0.831 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068473 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068473 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479819068476 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068601 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.402 " "Worst-case setup slack is 0.402" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.402               0.000 KEY3  " "    0.402               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068603 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068603 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.178               0.000 KEY3  " "    0.178               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068605 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068605 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068607 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068609 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479819068609 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068609 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.085 " "Worst-case minimum pulse width slack is -0.085" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.085              -0.838 KEY3  " "   -0.085              -0.838 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479819068610 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819068610 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819069787 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819069787 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1179 " "Peak virtual memory: 1179 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479819069820 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:51:09 2016 " "Processing ended: Tue Nov 22 12:51:09 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479819069820 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479819069820 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479819069820 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479819069820 ""}

diff --git a/part_2/ex7/db/ex7.sta.rdb b/part_2/ex7/db/ex7.sta.rdb
new file mode 100755
index 0000000..5052c3a
--- /dev/null
+++ b/part_2/ex7/db/ex7.sta.rdb
diff --git a/part_2/ex7/db/ex7.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex7/db/ex7.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..06b883b
--- /dev/null
+++ b/part_2/ex7/db/ex7.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex7/db/ex7.tis_db_list.ddb b/part_2/ex7/db/ex7.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_2/ex7/db/ex7.tis_db_list.ddb
diff --git a/part_2/ex7/db/ex7.tiscmp.fast_1100mv_0c.ddb b/part_2/ex7/db/ex7.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..623d2cb
--- /dev/null
+++ b/part_2/ex7/db/ex7.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex7/db/ex7.tiscmp.fast_1100mv_85c.ddb b/part_2/ex7/db/ex7.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..ed9d21f
--- /dev/null
+++ b/part_2/ex7/db/ex7.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex7/db/ex7.tiscmp.slow_1100mv_0c.ddb b/part_2/ex7/db/ex7.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..93a4be4
--- /dev/null
+++ b/part_2/ex7/db/ex7.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex7/db/ex7.tiscmp.slow_1100mv_85c.ddb b/part_2/ex7/db/ex7.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..4016d4e
--- /dev/null
+++ b/part_2/ex7/db/ex7.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex7/db/ex7.tmw_info b/part_2/ex7/db/ex7.tmw_info
new file mode 100755
index 0000000..a665999
--- /dev/null
+++ b/part_2/ex7/db/ex7.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:52

+start_analysis_synthesis:s:00:00:11-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:00:29-start_full_compilation

+start_assembler:s:00:00:07-start_full_compilation

+start_timing_analyzer:s:00:00:05-start_full_compilation

diff --git a/part_2/ex7/db/ex7.vpr.ammdb b/part_2/ex7/db/ex7.vpr.ammdb
new file mode 100755
index 0000000..d286611
--- /dev/null
+++ b/part_2/ex7/db/ex7.vpr.ammdb
diff --git a/part_2/ex7/db/ex7_partition_pins.json b/part_2/ex7/db/ex7_partition_pins.json
new file mode 100755
index 0000000..c3662f5
--- /dev/null
+++ b/part_2/ex7/db/ex7_partition_pins.json
@@ -0,0 +1,69 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "HEX0[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[6]",

+					"strict" : false

+				},

+				{

+					"name" : "KEY3",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex7/db/prev_cmp_ex7.qmsg b/part_2/ex7/db/prev_cmp_ex7.qmsg
new file mode 100755
index 0000000..51c5028
--- /dev/null
+++ b/part_2/ex7/db/prev_cmp_ex7.qmsg
@@ -0,0 +1,128 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479818519233 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479818519235 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 12:41:58 2016 " "Processing started: Tue Nov 22 12:41:58 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479818519235 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479818519235 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex7 -c ex7 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex7 -c ex7" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479818519236 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479818519708 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479818519708 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex7/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479818528127 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479818528127 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex7/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479818528130 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479818528130 ""}

+{ "Warning" "WSGN_SEARCH_FILE" "ex7.v 1 1 " "Using design file ex7.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ex7 " "Found entity 1: ex7" {  } { { "ex7.v" "" { Text "C:/New folder/ex7/ex7.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479818528168 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1479818528168 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex7.v(8) " "Verilog HDL Instantiation warning at ex7.v(8): instance has no name" {  } { { "ex7.v" "" { Text "C:/New folder/ex7/ex7.v" 8 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1479818528168 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex7 " "Elaborating entity \"ex7\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479818528169 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:comb_3 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:comb_3\"" {  } { { "ex7.v" "comb_3" { Text "C:/New folder/ex7/ex7.v" 8 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479818528170 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:h0\"" {  } { { "ex7.v" "h0" { Text "C:/New folder/ex7/ex7.v" 10 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479818528175 ""}

+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "count\[7\] " "Net \"count\[7\]\" is missing source, defaulting to GND" {  } { { "ex7.v" "count\[7\]" { Text "C:/New folder/ex7/ex7.v" 6 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1479818528182 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1479818528182 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1479818528544 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479818528623 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479818528874 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479818528874 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "36 " "Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479818528899 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479818528899 ""} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Implemented 21 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479818528899 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479818528899 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479818528909 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:42:08 2016 " "Processing ended: Tue Nov 22 12:42:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479818528909 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479818528909 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479818528909 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479818528909 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1479818530359 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479818530359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 12:42:09 2016 " "Processing started: Tue Nov 22 12:42:09 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479818530359 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1479818530359 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex7 -c ex7 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex7 -c ex7" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1479818530360 ""}

+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1479818530476 ""}

+{ "Info" "0" "" "Project  = ex7" {  } {  } 0 0 "Project  = ex7" 0 0 "Fitter" 0 0 1479818530477 ""}

+{ "Info" "0" "" "Revision = ex7" {  } {  } 0 0 "Revision = ex7" 0 0 "Fitter" 0 0 1479818530477 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479818530585 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479818530585 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex7 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex7\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479818530852 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479818530919 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479818530919 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479818531298 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479818531430 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479818541384 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "KEY3~inputCLKENA0 7 global CLKCTRL_G6 " "KEY3~inputCLKENA0 with 7 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479818541436 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479818541436 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479818541436 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479818541438 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479818541438 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479818541438 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479818541438 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479818541438 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479818541439 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479818541439 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479818541439 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479818541439 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479818541458 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479818541458 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479818541460 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex7.sdc " "Synopsys Design Constraints File file not found: 'ex7.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479818546829 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479818546830 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479818546831 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479818546831 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479818546831 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479818546833 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479818546903 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479818547353 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479818547689 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479818548181 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479818548181 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479818548804 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex7/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479818553115 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479818553115 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479818553436 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479818553436 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479818553440 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479818554256 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479818554291 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479818554567 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479818554567 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479818554838 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479818556778 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479818557005 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex7/output_files/ex7.fit.smsg " "Generated suppressed messages file C:/New folder/ex7/output_files/ex7.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479818557053 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 71 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 71 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2546 " "Peak virtual memory: 2546 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479818557416 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:42:37 2016 " "Processing ended: Tue Nov 22 12:42:37 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479818557416 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479818557416 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479818557416 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479818557416 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1479818558737 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479818558739 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 12:42:38 2016 " "Processing started: Tue Nov 22 12:42:38 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479818558739 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479818558739 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex7 -c ex7 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex7 -c ex7" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479818558740 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479818559463 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479818563957 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479818564291 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:42:44 2016 " "Processing ended: Tue Nov 22 12:42:44 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479818564291 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479818564291 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479818564291 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479818564291 ""}

+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1479818564962 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1479818565770 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479818565771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 12:42:45 2016 " "Processing started: Tue Nov 22 12:42:45 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479818565771 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818565771 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex7 -c ex7 " "Command: quartus_sta ex7 -c ex7" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818565771 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479818565901 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566415 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566416 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566462 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566462 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex7.sdc " "Synopsys Design Constraints File file not found: 'ex7.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566964 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566964 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name KEY3 KEY3 " "create_clock -period 1.000 -name KEY3 KEY3" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1479818566965 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566965 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566965 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566966 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479818566966 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479818566973 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479818566977 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566977 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.161 " "Worst-case setup slack is -0.161" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.161              -0.319 KEY3  " "   -0.161              -0.319 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566979 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566979 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.239 " "Worst-case hold slack is 0.239" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566981 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566981 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.239               0.000 KEY3  " "    0.239               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566981 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566981 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566982 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566984 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.394 " "Worst-case minimum pulse width slack is -0.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.695 KEY3  " "   -0.394              -5.695 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818566985 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818566985 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479818566988 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567020 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567553 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567586 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479818567589 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567589 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.204 " "Worst-case setup slack is -0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567590 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567590 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.204              -0.403 KEY3  " "   -0.204              -0.403 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567590 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567590 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.222 " "Worst-case hold slack is 0.222" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567592 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567592 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.222               0.000 KEY3  " "    0.222               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567592 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567592 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567594 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567595 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.394 " "Worst-case minimum pulse width slack is -0.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -6.034 KEY3  " "   -0.394              -6.034 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818567596 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567596 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479818567599 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818567731 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568164 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568195 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.346 " "Worst-case setup slack is 0.346" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568198 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.346               0.000 KEY3  " "    0.346               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568198 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568198 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.138 " "Worst-case hold slack is 0.138" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.138               0.000 KEY3  " "    0.138               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568199 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568199 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568201 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568202 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479818568202 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568202 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.085 " "Worst-case minimum pulse width slack is -0.085" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568204 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568204 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.085              -0.922 KEY3  " "   -0.085              -0.922 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568204 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568204 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479818568206 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568329 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.363 " "Worst-case setup slack is 0.363" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568331 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568331 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.363               0.000 KEY3  " "    0.363               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568331 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568331 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.123 " "Worst-case hold slack is 0.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.123               0.000 KEY3  " "    0.123               0.000 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568333 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568333 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568335 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568337 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479818568337 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568337 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.085 " "Worst-case minimum pulse width slack is -0.085" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.085              -0.927 KEY3  " "   -0.085              -0.927 KEY3 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479818568338 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818568338 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818569515 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818569515 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1180 " "Peak virtual memory: 1180 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479818569549 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 12:42:49 2016 " "Processing ended: Tue Nov 22 12:42:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479818569549 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479818569549 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479818569549 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818569549 ""}

+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 84 s " "Quartus Prime Full Compilation was successful. 0 errors, 84 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479818570247 ""}

diff --git a/part_2/ex7/ex7.qpf b/part_2/ex7/ex7.qpf
new file mode 100755
index 0000000..462c633
--- /dev/null
+++ b/part_2/ex7/ex7.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 11:46:43  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "16.0"

+DATE = "11:46:43  November 22, 2016"

+

+# Revisions

+

+PROJECT_REVISION = "ex7"

diff --git a/part_2/ex7/ex7.qsf b/part_2/ex7/ex7.qsf
new file mode 100755
index 0000000..d7c3dcc
--- /dev/null
+++ b/part_2/ex7/ex7.qsf
@@ -0,0 +1,267 @@
+#============================================================

+# CLOCK

+#============================================================

+set_location_assignment PIN_AF14 -to CLOCK_50

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50

+

+#============================================================

+# Add-on Card Interface Pins

+#============================================================

+set_location_assignment PIN_AJ20 -to PWM_OUT

+set_location_assignment PIN_AK21 -to DAC_LD

+set_location_assignment PIN_AD20 -to DAC_CS

+set_location_assignment PIN_AF20 -to DAC_SCK

+set_location_assignment PIN_AF21 -to ADC_SCK

+set_location_assignment PIN_AG21 -to ADC_SDI

+set_location_assignment PIN_AG20 -to ADC_CS

+set_location_assignment PIN_AG18 -to DAC_SDI

+set_location_assignment PIN_AJ21 -to ADC_SDO

+set_location_assignment PIN_Y17 -to OLED_CS

+set_location_assignment PIN_Y18 -to OLED_RST

+set_location_assignment PIN_AK18 -to OLED_DC

+set_location_assignment PIN_AJ19 -to OLED_CLK

+set_location_assignment PIN_AJ16 -to OLED_DATA

+

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO

+

+

+#============================================================

+# HEX0

+#============================================================

+set_location_assignment PIN_AE26 -to HEX0[0]

+set_location_assignment PIN_AE27 -to HEX0[1]

+set_location_assignment PIN_AE28 -to HEX0[2]

+set_location_assignment PIN_AG27 -to HEX0[3]

+set_location_assignment PIN_AF28 -to HEX0[4]

+set_location_assignment PIN_AG28 -to HEX0[5]

+set_location_assignment PIN_AH28 -to HEX0[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]

+

+#============================================================

+# HEX1

+#============================================================

+set_location_assignment PIN_AJ29 -to HEX1[0]

+set_location_assignment PIN_AH29 -to HEX1[1]

+set_location_assignment PIN_AH30 -to HEX1[2]

+set_location_assignment PIN_AG30 -to HEX1[3]

+set_location_assignment PIN_AF29 -to HEX1[4]

+set_location_assignment PIN_AF30 -to HEX1[5]

+set_location_assignment PIN_AD27 -to HEX1[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]

+

+#============================================================

+# HEX2

+#============================================================

+set_location_assignment PIN_AB23 -to HEX2[0]

+set_location_assignment PIN_AE29 -to HEX2[1]

+set_location_assignment PIN_AD29 -to HEX2[2]

+set_location_assignment PIN_AC28 -to HEX2[3]

+set_location_assignment PIN_AD30 -to HEX2[4]

+set_location_assignment PIN_AC29 -to HEX2[5]

+set_location_assignment PIN_AC30 -to HEX2[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]

+

+#============================================================

+# HEX3

+#============================================================

+set_location_assignment PIN_AD26 -to HEX3[0]

+set_location_assignment PIN_AC27 -to HEX3[1]

+set_location_assignment PIN_AD25 -to HEX3[2]

+set_location_assignment PIN_AC25 -to HEX3[3]

+set_location_assignment PIN_AB28 -to HEX3[4]

+set_location_assignment PIN_AB25 -to HEX3[5]

+set_location_assignment PIN_AB22 -to HEX3[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]

+

+#============================================================

+# HEX4

+#============================================================

+set_location_assignment PIN_AA24 -to HEX4[0]

+set_location_assignment PIN_Y23 -to HEX4[1]

+set_location_assignment PIN_Y24 -to HEX4[2]

+set_location_assignment PIN_W22 -to HEX4[3]

+set_location_assignment PIN_W24 -to HEX4[4]

+set_location_assignment PIN_V23 -to HEX4[5]

+set_location_assignment PIN_W25 -to HEX4[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]

+

+#============================================================

+# HEX5

+#============================================================

+set_location_assignment PIN_V25 -to HEX5[0]

+set_location_assignment PIN_AA28 -to HEX5[1]

+set_location_assignment PIN_Y27 -to HEX5[2]

+set_location_assignment PIN_AB27 -to HEX5[3]

+set_location_assignment PIN_AB26 -to HEX5[4]

+set_location_assignment PIN_AA26 -to HEX5[5]

+set_location_assignment PIN_AA25 -to HEX5[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]

+

+#============================================================

+# KEY

+#============================================================

+set_location_assignment PIN_AA14 -to KEY[0]

+set_location_assignment PIN_AA15 -to KEY[1]

+set_location_assignment PIN_W15 -to KEY[2]

+set_location_assignment PIN_Y16 -to KEY3

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]

+

+#============================================================

+# LEDR

+#============================================================

+set_location_assignment PIN_V16 -to LEDR[0]

+set_location_assignment PIN_W16 -to LEDR[1]

+set_location_assignment PIN_V17 -to LEDR[2]

+set_location_assignment PIN_V18 -to LEDR[3]

+set_location_assignment PIN_W17 -to LEDR[4]

+set_location_assignment PIN_W19 -to LEDR[5]

+set_location_assignment PIN_Y19 -to LEDR[6]

+set_location_assignment PIN_W20 -to LEDR[7]

+set_location_assignment PIN_W21 -to LEDR[8]

+set_location_assignment PIN_Y21 -to LEDR[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]

+

+#============================================================

+# SW

+#============================================================

+set_location_assignment PIN_AB12 -to SW[0]

+set_location_assignment PIN_AC12 -to SW[1]

+set_location_assignment PIN_AF9 -to SW[2]

+set_location_assignment PIN_AF10 -to SW[3]

+set_location_assignment PIN_AD11 -to SW[4]

+set_location_assignment PIN_AD12 -to SW[5]

+set_location_assignment PIN_AE11 -to SW[6]

+set_location_assignment PIN_AC9 -to SW[7]

+set_location_assignment PIN_AD10 -to SW[8]

+set_location_assignment PIN_AE12 -to SW[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]

+

+#============================================================

+# End of pin and io_standard assignments

+#============================================================# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 11:46:43  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex7_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex7

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:46:43  NOVEMBER 22, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex7/ex7.qsf.bak b/part_2/ex7/ex7.qsf.bak
new file mode 100755
index 0000000..31e6c69
--- /dev/null
+++ b/part_2/ex7/ex7.qsf.bak
@@ -0,0 +1,53 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 11:46:43  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex7_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex7

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:46:43  NOVEMBER 22, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
\ No newline at end of file
diff --git a/part_2/ex7/ex7.qws b/part_2/ex7/ex7.qws
new file mode 100755
index 0000000..1d4f377
--- /dev/null
+++ b/part_2/ex7/ex7.qws
diff --git a/part_2/ex7/ex7.v b/part_2/ex7/ex7.v
new file mode 100755
index 0000000..079c34e
--- /dev/null
+++ b/part_2/ex7/ex7.v
@@ -0,0 +1,13 @@
+module ex7(KEY3, HEX0, HEX1);

+

+	input KEY3;

+	output [6:0] HEX0, HEX1;

+

+	wire [7:0] count;

+	

+	LFSR(KEY3, count);

+	

+	hex_to_7seg h0(HEX0, count[3:0]);

+	hex_to_7seg h1(HEX1, count[7:4]);

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex7/ex7.v.bak b/part_2/ex7/ex7.v.bak
new file mode 100755
index 0000000..11146ed
--- /dev/null
+++ b/part_2/ex7/ex7.v.bak
@@ -0,0 +1,13 @@
+module ex7(CLOCK_50, HEX0, HEX1);

+

+	input CLOCK_50;

+	output [3:0] HEX0, HEX1;

+

+	wire[7:0] count;

+	

+	LFSR(CLOCK_50, count);

+	

+	hex_to_7seg(HEX0, count[3:0]);

+	hex_to_7seg(HEX1, count[7:4]);

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex7/incremental_db/README b/part_2/ex7/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_2/ex7/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.

+

+The compiled_partitions sub-folder contains previous compilation results for each partition.

+As long as this folder is preserved, incremental compilation results from earlier compiles

+can be re-used.  To perform a clean compilation from source files for all partitions, both

+the db and incremental_db folder should be removed.

+

+The imported_partitions sub-folder contains the last imported QXP for each imported partition.

+As long as this folder is preserved, imported partitions will be automatically re-imported

+when the db or incremental_db/compiled_partitions folders are removed.

+

diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.db_info b/part_2/ex7/incremental_db/compiled_partitions/ex7.db_info
new file mode 100755
index 0000000..d58d85b
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Tue Nov 22 12:08:36 2016

diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.ammdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.ammdb
new file mode 100755
index 0000000..d43da80
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.ammdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.cdb
new file mode 100755
index 0000000..9579054
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.dfp b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.dfp
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..5589944
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.hdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..4541bd9
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.sig b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hdb
new file mode 100755
index 0000000..9a92d7f
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.hdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.logdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.rcfdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..7b19bd0
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.cmp.rcfdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.cdb
new file mode 100755
index 0000000..b0871e5
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.dpi b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.dpi
new file mode 100755
index 0000000..390476d
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.dpi
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..789057a
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.hb_info b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.hdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..ea7a8fe
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.hdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.sig b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hdb
new file mode 100755
index 0000000..7ee4705
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.hdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.kpt b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.kpt
new file mode 100755
index 0000000..af38db5
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.kpt
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.olf.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.olf.cdb
new file mode 100755
index 0000000..fe3979b
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.olf.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.olm.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.olm.cdb
new file mode 100755
index 0000000..26eb600
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.olm.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.oln.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.oln.cdb
new file mode 100755
index 0000000..3133d9f
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.oln.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.opi b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.opi
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orf.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orf.cdb
new file mode 100755
index 0000000..fe3979b
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orf.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orm.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orm.cdb
new file mode 100755
index 0000000..69127b9
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orm.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orn.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orn.cdb
new file mode 100755
index 0000000..54628ba
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.map.orn.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.cdb
new file mode 100755
index 0000000..b0871e5
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hbdb.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..789057a
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hbdb.hdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..ea7a8fe
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hdb
new file mode 100755
index 0000000..7ee4705
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.hdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.kpt b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.kpt
new file mode 100755
index 0000000..af38db5
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.root_partition.rrp.kpt
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.rrp.hdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.rrp.hdb
new file mode 100755
index 0000000..4eff2a9
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.rrp.hdb
diff --git a/part_2/ex7/incremental_db/compiled_partitions/ex7.rrs.cdb b/part_2/ex7/incremental_db/compiled_partitions/ex7.rrs.cdb
new file mode 100755
index 0000000..3cf4303
--- /dev/null
+++ b/part_2/ex7/incremental_db/compiled_partitions/ex7.rrs.cdb
diff --git a/part_2/ex7/output_files/ex7.asm.rpt b/part_2/ex7/output_files/ex7.asm.rpt
new file mode 100755
index 0000000..41cea53
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex7

+Tue Nov 22 12:51:04 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Assembler Summary

+  3. Assembler Settings

+  4. Assembler Generated Files

+  5. Assembler Device Options: C:/New folder/ex7/output_files/ex7.sof

+  6. Assembler Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------+

+; Assembler Summary                                             ;

++-----------------------+---------------------------------------+

+; Assembler Status      ; Successful - Tue Nov 22 12:51:04 2016 ;

+; Revision Name         ; ex7                                   ;

+; Top-level Entity Name ; ex7                                   ;

+; Family                ; Cyclone V                             ;

+; Device                ; 5CSEMA5F31C6                          ;

++-----------------------+---------------------------------------+

+

+

++----------------------------------+

+; Assembler Settings               ;

++--------+---------+---------------+

+; Option ; Setting ; Default Value ;

++--------+---------+---------------+

+

+

++----------------------------------------+

+; Assembler Generated Files              ;

++----------------------------------------+

+; File Name                              ;

++----------------------------------------+

+; C:/New folder/ex7/output_files/ex7.sof ;

++----------------------------------------+

+

+

++------------------------------------------------------------------+

+; Assembler Device Options: C:/New folder/ex7/output_files/ex7.sof ;

++----------------+-------------------------------------------------+

+; Option         ; Setting                                         ;

++----------------+-------------------------------------------------+

+; Device         ; 5CSEMA5F31C6                                    ;

+; JTAG usercode  ; 0x00AF9854                                      ;

+; Checksum       ; 0x00AF9854                                      ;

++----------------+-------------------------------------------------+

+

+

++--------------------+

+; Assembler Messages ;

++--------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Assembler

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Tue Nov 22 12:50:58 2016

+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex7 -c ex7

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (115030): Assembler is generating device programming files

+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 892 megabytes

+    Info: Processing ended: Tue Nov 22 12:51:04 2016

+    Info: Elapsed time: 00:00:06

+    Info: Total CPU time (on all processors): 00:00:06

+

+

diff --git a/part_2/ex7/output_files/ex7.done b/part_2/ex7/output_files/ex7.done
new file mode 100755
index 0000000..3b79e93
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.done
@@ -0,0 +1 @@
+Tue Nov 22 12:51:10 2016

diff --git a/part_2/ex7/output_files/ex7.fit.rpt b/part_2/ex7/output_files/ex7.fit.rpt
new file mode 100755
index 0000000..ed4eaa5
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.fit.rpt
@@ -0,0 +1,1934 @@
+Fitter report for ex7

+Tue Nov 22 12:50:57 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Fitter Summary

+  3. Fitter Settings

+  4. Parallel Compilation

+  5. I/O Assignment Warnings

+  6. Fitter Netlist Optimizations

+  7. Ignored Assignments

+  8. Incremental Compilation Preservation Summary

+  9. Incremental Compilation Partition Settings

+ 10. Incremental Compilation Placement Preservation

+ 11. Pin-Out File

+ 12. Fitter Resource Usage Summary

+ 13. Fitter Partition Statistics

+ 14. Input Pins

+ 15. Output Pins

+ 16. I/O Bank Usage

+ 17. All Package Pins

+ 18. Fitter Resource Utilization by Entity

+ 19. Delay Chain Summary

+ 20. Pad To Core Delay Chain Fanout

+ 21. Control Signals

+ 22. Global & Other Fast Signals

+ 23. Routing Usage Summary

+ 24. I/O Rules Summary

+ 25. I/O Rules Details

+ 26. I/O Rules Matrix

+ 27. Fitter Device Options

+ 28. Operating Settings and Conditions

+ 29. Estimated Delay Added for Hold Timing Summary

+ 30. Estimated Delay Added for Hold Timing Details

+ 31. Fitter Messages

+ 32. Fitter Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Fitter Summary                                                                    ;

++---------------------------------+-------------------------------------------------+

+; Fitter Status                   ; Successful - Tue Nov 22 12:50:57 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex7                                             ;

+; Top-level Entity Name           ; ex7                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 9 / 32,070 ( < 1 % )                            ;

+; Total registers                 ; 10                                              ;

+; Total pins                      ; 15 / 457 ( 3 % )                                ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Settings                                                                                                                                            ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Option                                                                     ; Setting                               ; Default Value                         ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;

+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;

+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;

+; Use smart compilation                                                      ; Off                                   ; Off                                   ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;

+; Enable compact report table                                                ; Off                                   ; Off                                   ;

+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;

+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;

+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;

+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;

+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;

+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;

+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;

+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;

+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;

+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;

+; SSN Optimization                                                           ; Off                                   ; Off                                   ;

+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;

+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;

+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;

+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;

+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;

+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;

+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;

+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;

+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;

+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;

+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;

+; Auto Delay Chains                                                          ; On                                    ; On                                    ;

+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;

+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;

+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;

+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;

+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;

+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;

+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;

+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;

+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;

+; Auto Global Clock                                                          ; On                                    ; On                                    ;

+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;

+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;

+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;

+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;

+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;

+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;

+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;

+; Clamping Diode                                                             ; Off                                   ; Off                                   ;

+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;

+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.1%      ;

+;     Processors 3-4         ;   0.0%      ;

++----------------------------+-------------+

+

+

++-------------------------------------------------+

+; I/O Assignment Warnings                         ;

++----------+--------------------------------------+

+; Pin Name ; Reason                               ;

++----------+--------------------------------------+

+; HEX0[0]  ; Missing drive strength and slew rate ;

+; HEX0[1]  ; Missing drive strength and slew rate ;

+; HEX0[2]  ; Missing drive strength and slew rate ;

+; HEX0[3]  ; Missing drive strength and slew rate ;

+; HEX0[4]  ; Missing drive strength and slew rate ;

+; HEX0[5]  ; Missing drive strength and slew rate ;

+; HEX0[6]  ; Missing drive strength and slew rate ;

+; HEX1[0]  ; Missing drive strength and slew rate ;

+; HEX1[1]  ; Missing drive strength and slew rate ;

+; HEX1[2]  ; Missing drive strength and slew rate ;

+; HEX1[3]  ; Missing drive strength and slew rate ;

+; HEX1[4]  ; Missing drive strength and slew rate ;

+; HEX1[5]  ; Missing drive strength and slew rate ;

+; HEX1[6]  ; Missing drive strength and slew rate ;

+; KEY3     ; Incomplete set of assignments        ;

++----------+--------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Netlist Optimizations                                                                                                                                                                                                ;

++----------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------+------------------+-----------------------+

+; Node                 ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node               ; Destination Port ; Destination Port Name ;

++----------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------+------------------+-----------------------+

+; KEY3~inputCLKENA0    ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                ;                  ;                       ;

+; LFSR:comb_3|COUNT[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; LFSR:comb_3|COUNT[2]~DUPLICATE ;                  ;                       ;

+; LFSR:comb_3|COUNT[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; LFSR:comb_3|COUNT[4]~DUPLICATE ;                  ;                       ;

+; LFSR:comb_3|COUNT[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; LFSR:comb_3|COUNT[5]~DUPLICATE ;                  ;                       ;

++----------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------+------------------+-----------------------+

+

+

++--------------------------------------------------------------------------------------------+

+; Ignored Assignments                                                                        ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;

+; Location     ;                ;              ; CLOCK_50   ; PIN_AF14      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;

+; Location     ;                ;              ; HEX2[0]    ; PIN_AB23      ; QSF Assignment ;

+; Location     ;                ;              ; HEX2[1]    ; PIN_AE29      ; QSF Assignment ;

+; Location     ;                ;              ; HEX2[2]    ; PIN_AD29      ; QSF Assignment ;

+; Location     ;                ;              ; HEX2[3]    ; PIN_AC28      ; QSF Assignment ;

+; Location     ;                ;              ; HEX2[4]    ; PIN_AD30      ; QSF Assignment ;

+; Location     ;                ;              ; HEX2[5]    ; PIN_AC29      ; QSF Assignment ;

+; Location     ;                ;              ; HEX2[6]    ; PIN_AC30      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[0]    ; PIN_AD26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[1]    ; PIN_AC27      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[2]    ; PIN_AD25      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[3]    ; PIN_AC25      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[4]    ; PIN_AB28      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[5]    ; PIN_AB25      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[6]    ; PIN_AB22      ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[0]    ; PIN_AA24      ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[1]    ; PIN_Y23       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[2]    ; PIN_Y24       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[3]    ; PIN_W22       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[4]    ; PIN_W24       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[5]    ; PIN_V23       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[6]    ; PIN_W25       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;

+; Location     ;                ;              ; KEY[0]     ; PIN_AA14      ; QSF Assignment ;

+; Location     ;                ;              ; KEY[1]     ; PIN_AA15      ; QSF Assignment ;

+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;

+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;

+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;

+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; CLOCK_50   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX2[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX2[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX2[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX2[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX2[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX2[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX2[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX3[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX3[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX3[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX3[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX3[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX3[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX3[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX4[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX4[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX4[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX4[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX4[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX4[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX4[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; KEY[0]     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; KEY[1]     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex7            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;

++--------------+----------------+--------------+------------+---------------+----------------+

+

+

++-------------------------------------------------------------------------------------------------+

+; Incremental Compilation Preservation Summary                                                    ;

++---------------------+-------------------+----------------------------+--------------------------+

+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;

++---------------------+-------------------+----------------------------+--------------------------+

+; Placement (by node) ;                   ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 )          ; 0.00 % ( 0 / 55 )        ;

+;     -- Achieved     ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 )          ; 0.00 % ( 0 / 55 )        ;

+;                     ;                   ;                            ;                          ;

+; Routing (by net)    ;                   ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

++---------------------+-------------------+----------------------------+--------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Partition Settings                                                                                                                                             ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;

+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Placement Preservation                                                                                     ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Top                            ; 0.00 % ( 0 / 55 )     ; N/A                     ; Source File       ; N/A                 ;       ;

+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+

+

++--------------+

+; Pin-Out File ;

++--------------+

+The pin-out file can be found in C:/New folder/ex7/output_files/ex7.pin.

+

+

++------------------------------------------------------------------------------------------+

+; Fitter Resource Usage Summary                                                            ;

++-------------------------------------------------------------+--------------------+-------+

+; Resource                                                    ; Usage              ; %     ;

++-------------------------------------------------------------+--------------------+-------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 9 / 32,070         ; < 1 % ;

+; ALMs needed [=A-B+C]                                        ; 9                  ;       ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 11 / 32,070        ; < 1 % ;

+;         [a] ALMs used for LUT logic and registers           ; 2                  ;       ;

+;         [b] ALMs used for LUT logic                         ; 7                  ;       ;

+;         [c] ALMs used for registers                         ; 2                  ;       ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 2 / 32,070         ; < 1 % ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;

+;         [a] Due to location constrained logic               ; 0                  ;       ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;

+;         [c] Due to LAB input limits                         ; 0                  ;       ;

+;         [d] Due to virtual I/Os                             ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Difficulty packing design                                   ; Low                ;       ;

+;                                                             ;                    ;       ;

+; Total LABs:  partially or completely used                   ; 2 / 3,207          ; < 1 % ;

+;     -- Logic LABs                                           ; 2                  ;       ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Combinational ALUT usage for logic                          ; 17                 ;       ;

+;     -- 7 input functions                                    ; 0                  ;       ;

+;     -- 6 input functions                                    ; 0                  ;       ;

+;     -- 5 input functions                                    ; 0                  ;       ;

+;     -- 4 input functions                                    ; 7                  ;       ;

+;     -- <=3 input functions                                  ; 10                 ;       ;

+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;

+; Dedicated logic registers                                   ; 10                 ;       ;

+;     -- By type:                                             ;                    ;       ;

+;         -- Primary logic registers                          ; 7 / 64,140         ; < 1 % ;

+;         -- Secondary logic registers                        ; 3 / 64,140         ; < 1 % ;

+;     -- By function:                                         ;                    ;       ;

+;         -- Design implementation registers                  ; 7                  ;       ;

+;         -- Routing optimization registers                   ; 3                  ;       ;

+;                                                             ;                    ;       ;

+; Virtual pins                                                ; 0                  ;       ;

+; I/O pins                                                    ; 15 / 457           ; 3 %   ;

+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;

+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Hard processor system peripheral utilization                ;                    ;       ;

+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;

+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;

+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;

+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;

+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;

+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;

+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;

+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;

+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;

+;                                                             ;                    ;       ;

+; Global signals                                              ; 1                  ;       ;

+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;

+; Total MLAB memory bits                                      ; 0                  ;       ;

+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;

+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;

+;                                                             ;                    ;       ;

+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;

+; Global clocks                                               ; 1 / 16             ; 6 %   ;

+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;

+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;

+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;

+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;

+; JTAGs                                                       ; 0 / 1              ; 0 %   ;

+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;

+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;

+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;

+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;

+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;

+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;

+; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.0% ;       ;

+; Peak interconnect usage (total/H/V)                         ; 0.1% / 0.0% / 0.3% ;       ;

+; Maximum fan-out                                             ; 10                 ;       ;

+; Highest non-global fan-out                                  ; 9                  ;       ;

+; Total fan-out                                               ; 102                ;       ;

+; Average fan-out                                             ; 1.76               ;       ;

++-------------------------------------------------------------+--------------------+-------+

+

+

++---------------------------------------------------------------------------------------------------------------------+

+; Fitter Partition Statistics                                                                                         ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Statistic                                                   ; Top                  ; hard_block:auto_generated_inst ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 9 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;

+; ALMs needed [=A-B+C]                                        ; 9                    ; 0                              ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 11 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+;         [a] ALMs used for LUT logic and registers           ; 2                    ; 0                              ;

+;         [b] ALMs used for LUT logic                         ; 7                    ; 0                              ;

+;         [c] ALMs used for registers                         ; 2                    ; 0                              ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                    ; 0                              ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 2 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )    ; 0 / 32070 ( 0 % )              ;

+;         [a] Due to location constrained logic               ; 0                    ; 0                              ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                    ; 0                              ;

+;         [c] Due to LAB input limits                         ; 0                    ; 0                              ;

+;         [d] Due to virtual I/Os                             ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Difficulty packing design                                   ; Low                  ; Low                            ;

+;                                                             ;                      ;                                ;

+; Total LABs:  partially or completely used                   ; 2 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;

+;     -- Logic LABs                                           ; 2                    ; 0                              ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Combinational ALUT usage for logic                          ; 17                   ; 0                              ;

+;     -- 7 input functions                                    ; 0                    ; 0                              ;

+;     -- 6 input functions                                    ; 0                    ; 0                              ;

+;     -- 5 input functions                                    ; 0                    ; 0                              ;

+;     -- 4 input functions                                    ; 7                    ; 0                              ;

+;     -- <=3 input functions                                  ; 10                   ; 0                              ;

+; Combinational ALUT usage for route-throughs                 ; 0                    ; 0                              ;

+; Memory ALUT usage                                           ; 0                    ; 0                              ;

+;     -- 64-address deep                                      ; 0                    ; 0                              ;

+;     -- 32-address deep                                      ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Dedicated logic registers                                   ; 0                    ; 0                              ;

+;     -- By type:                                             ;                      ;                                ;

+;         -- Primary logic registers                          ; 7 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;         -- Secondary logic registers                        ; 3 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;     -- By function:                                         ;                      ;                                ;

+;         -- Design implementation registers                  ; 7                    ; 0                              ;

+;         -- Routing optimization registers                   ; 3                    ; 0                              ;

+;                                                             ;                      ;                                ;

+;                                                             ;                      ;                                ;

+; Virtual pins                                                ; 0                    ; 0                              ;

+; I/O pins                                                    ; 15                   ; 0                              ;

+; I/O registers                                               ; 0                    ; 0                              ;

+; Total block memory bits                                     ; 0                    ; 0                              ;

+; Total block memory implementation bits                      ; 0                    ; 0                              ;

+; Clock enable block                                          ; 1 / 116 ( < 1 % )    ; 0 / 116 ( 0 % )                ;

+;                                                             ;                      ;                                ;

+; Connections                                                 ;                      ;                                ;

+;     -- Input Connections                                    ; 0                    ; 0                              ;

+;     -- Registered Input Connections                         ; 0                    ; 0                              ;

+;     -- Output Connections                                   ; 0                    ; 0                              ;

+;     -- Registered Output Connections                        ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Internal Connections                                        ;                      ;                                ;

+;     -- Total Connections                                    ; 102                  ; 0                              ;

+;     -- Registered Connections                               ; 59                   ; 0                              ;

+;                                                             ;                      ;                                ;

+; External Connections                                        ;                      ;                                ;

+;     -- Top                                                  ; 0                    ; 0                              ;

+;     -- hard_block:auto_generated_inst                       ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Partition Interface                                         ;                      ;                                ;

+;     -- Input Ports                                          ; 1                    ; 0                              ;

+;     -- Output Ports                                         ; 14                   ; 0                              ;

+;     -- Bidir Ports                                          ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Registered Ports                                            ;                      ;                                ;

+;     -- Registered Input Ports                               ; 0                    ; 0                              ;

+;     -- Registered Output Ports                              ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Port Connectivity                                           ;                      ;                                ;

+;     -- Input Ports driven by GND                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by GND                           ; 0                    ; 0                              ;

+;     -- Input Ports driven by VCC                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by VCC                           ; 0                    ; 0                              ;

+;     -- Input Ports with no Source                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Source                          ; 0                    ; 0                              ;

+;     -- Input Ports with no Fanout                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Fanout                          ; 0                    ; 0                              ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Input Pins                                                                                                                                                                                                                                                                          ;

++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;

++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; KEY3 ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 10                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; User                 ; no        ;

++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+

+

++----------------------------------------------------------------------------+

+; I/O Bank Usage                                                             ;

++----------+------------------+---------------+--------------+---------------+

+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;

++----------+------------------+---------------+--------------+---------------+

+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 3B       ; 1 / 48 ( 2 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 4A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 5A       ; 14 / 32 ( 44 % ) ; 3.3V          ; --           ; 3.3V          ;

+; 5B       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

++----------+------------------+---------------+--------------+---------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; All Package Pins                                                                                                                                                                  ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB23     ; 227        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC28     ; 245        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC29     ; 247        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC30     ; 259        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD29     ; 255        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AD30     ; 257        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE29     ; 253        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF14     ; 114        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;

+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;

+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y16      ; 128        ; 3B             ; KEY3                            ; input  ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+Note: Pin directions (input, output or bidir) are based on device operating in user mode.

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                  ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+; |ex7                       ; 8.5 (0.5)            ; 10.5 (0.5)                       ; 2.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (1)              ; 10 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 15   ; 0            ; |ex7                ; ex7         ; work         ;

+;    |LFSR:comb_3|           ; 2.6 (2.6)            ; 4.1 (4.1)                        ; 1.5 (1.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 2 (2)               ; 10 (10)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex7|LFSR:comb_3    ; LFSR        ; work         ;

+;    |hex_to_7seg:h0|        ; 2.9 (2.9)            ; 2.9 (2.9)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex7|hex_to_7seg:h0 ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:h1|        ; 2.5 (2.5)            ; 3.0 (3.0)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex7|hex_to_7seg:h1 ; hex_to_7seg ; work         ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++------------------------------------------------------------------------------------------------------------------------+

+; Delay Chain Summary                                                                                                    ;

++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; Name    ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;

++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; HEX0[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; KEY3    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

++---------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+

+

++---------------------------------------------------+

+; Pad To Core Delay Chain Fanout                    ;

++---------------------+-------------------+---------+

+; Source Pin / Fanout ; Pad To Core Index ; Setting ;

++---------------------+-------------------+---------+

+; KEY3                ;                   ;         ;

++---------------------+-------------------+---------+

+

+

++------------------------------------------------------------------------------------------------------------------+

+; Control Signals                                                                                                  ;

++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+

+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+

+; KEY3 ; PIN_Y16  ; 10      ; Clock ; yes    ; Global Clock         ; GCLK6            ; --                        ;

++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+

+

+

++-------------------------------------------------------------------------------------------------+

+; Global & Other Fast Signals                                                                     ;

++------+----------+---------+----------------------+------------------+---------------------------+

+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++------+----------+---------+----------------------+------------------+---------------------------+

+; KEY3 ; PIN_Y16  ; 10      ; Global Clock         ; GCLK6            ; --                        ;

++------+----------+---------+----------------------+------------------+---------------------------+

+

+

++----------------------------------------------------------------------+

+; Routing Usage Summary                                                ;

++---------------------------------------------+------------------------+

+; Routing Resource Type                       ; Usage                  ;

++---------------------------------------------+------------------------+

+; Block interconnects                         ; 21 / 289,320 ( < 1 % ) ;

+; C12 interconnects                           ; 0 / 13,420 ( 0 % )     ;

+; C2 interconnects                            ; 9 / 119,108 ( < 1 % )  ;

+; C4 interconnects                            ; 11 / 56,300 ( < 1 % )  ;

+; DQS bus muxes                               ; 0 / 25 ( 0 % )         ;

+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )         ;

+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )         ;

+; Direct links                                ; 6 / 289,320 ( < 1 % )  ;

+; Global clocks                               ; 1 / 16 ( 6 % )         ;

+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )          ;

+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )          ;

+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )          ;

+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )          ;

+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )          ;

+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )         ;

+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )         ;

+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )         ;

+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )         ;

+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )         ;

+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )          ;

+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )        ;

+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )        ;

+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )        ;

+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )        ;

+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )        ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )        ;

+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )        ;

+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )         ;

+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )         ;

+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )          ;

+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )        ;

+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )         ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )          ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )          ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )         ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )         ;

+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )         ;

+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )         ;

+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )        ;

+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )        ;

+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )          ;

+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )         ;

+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )         ;

+; Local interconnects                         ; 5 / 84,580 ( < 1 % )   ;

+; Quadrant clocks                             ; 0 / 66 ( 0 % )         ;

+; R14 interconnects                           ; 0 / 12,676 ( 0 % )     ;

+; R14/C12 interconnect drivers                ; 0 / 20,720 ( 0 % )     ;

+; R3 interconnects                            ; 3 / 130,992 ( < 1 % )  ;

+; R6 interconnects                            ; 2 / 266,960 ( < 1 % )  ;

+; Spine clocks                                ; 1 / 360 ( < 1 % )      ;

+; Wire stub REs                               ; 0 / 15,858 ( 0 % )     ;

++---------------------------------------------+------------------------+

+

+

++------------------------------------------+

+; I/O Rules Summary                        ;

++----------------------------------+-------+

+; I/O Rules Statistic              ; Total ;

++----------------------------------+-------+

+; Total I/O Rules                  ; 28    ;

+; Number of I/O Rules Passed       ; 6     ;

+; Number of I/O Rules Failed       ; 0     ;

+; Number of I/O Rules Unchecked    ; 0     ;

+; Number of I/O Rules Inapplicable ; 22    ;

++----------------------------------+-------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Details                                                                                                                                                                                                                                                  ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;

+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;

+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;

+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;

+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;

+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Total Pass         ; 15        ; 0            ; 15        ; 0            ; 0            ; 15        ; 15        ; 0            ; 15        ; 15        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Inapplicable ; 0         ; 15           ; 0         ; 15           ; 15           ; 0         ; 0         ; 15           ; 0         ; 0         ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ; 15           ;

+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY3               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+

+

++------------------------------------------------------------------------------------------------+

+; Fitter Device Options                                                                          ;

++------------------------------------------------------------------+-----------------------------+

+; Option                                                           ; Setting                     ;

++------------------------------------------------------------------+-----------------------------+

+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;

+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;

+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;

+; Enable INIT_DONE output                                          ; Off                         ;

+; Configuration scheme                                             ; Passive Serial              ;

+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;

+; Enable CvP_CONFDONE pin                                          ; Off                         ;

+; Enable open drain on CRC_ERROR pin                               ; On                          ;

+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;

+; Enable open drain on INIT_DONE pin                               ; On                          ;

+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;

+; Enable open drain on nCEO pin                                    ; On                          ;

+; Enable Partial Reconfiguration pins                              ; Off                         ;

+; Enable input tri-state on active configuration pins in user mode ; Off                         ;

+; Enable internal scrubbing                                        ; Off                         ;

+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;

+; Device initialization clock source                               ; Internal Oscillator         ;

+; Configuration via Protocol                                       ; Off                         ;

+; Configuration Voltage Level                                      ; Auto                        ;

+; Force Configuration Voltage Level                                ; Off                         ;

+; Enable nCEO output                                               ; Off                         ;

+; Data[15..8]                                                      ; Unreserved                  ;

+; Data[7..5]                                                       ; Unreserved                  ;

+; Base pin-out file on sameframe device                            ; Off                         ;

++------------------------------------------------------------------+-----------------------------+

+

+

++------------------------------------+

+; Operating Settings and Conditions  ;

++---------------------------+--------+

+; Setting                   ; Value  ;

++---------------------------+--------+

+; Nominal Core Voltage      ; 1.10 V ;

+; Low Junction Temperature  ; 0 °C   ;

+; High Junction Temperature ; 85 °C  ;

++---------------------------+--------+

+

+

++------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Summary              ;

++-----------------+----------------------+-------------------+

+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;

++-----------------+----------------------+-------------------+

+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.

+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.

+

+

++-----------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Details                   ;

++----------------------+----------------------+-------------------+

+; Source Register      ; Destination Register ; Delay Added in ns ;

++----------------------+----------------------+-------------------+

+; LFSR:comb_3|COUNT[1] ; LFSR:comb_3|COUNT[2] ; 0.231             ;

+; LFSR:comb_3|COUNT[7] ; LFSR:comb_3|COUNT[1] ; 0.204             ;

++----------------------+----------------------+-------------------+

+Note: This table only shows the top 2 path(s) that have the largest delay added for hold.

+

+

++-----------------+

+; Fitter Messages ;

++-----------------+

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (119006): Selected device 5CSEMA5F31C6 for design "ex7"

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

+Info (184020): Starting Fitter periphery placement operations

+Info (11191): Automatically promoted 1 clock (1 global)

+    Info (11162): KEY3~inputCLKENA0 with 7 fanout uses global clock CLKCTRL_G6

+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

+Info (176233): Starting register packing

+Info (176235): Finished register packing

+    Extra Info (176219): No registers were packed into other blocks

+Warning (15705): Ignored locations or region assignments to the following nodes

+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design

+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex7.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332144): No user constrained base clocks found in the design

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.

+Info (170189): Fitter placement preparation operations beginning

+Info (14951): The Fitter is using Advanced Physical Optimization.

+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00

+Info (170191): Fitter placement operations beginning

+Info (170137): Fitter placement was successful

+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01

+Info (170193): Fitter routing operations beginning

+Info (170195): Router estimated average interconnect usage is 0% of the available device resources

+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10

+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.

+    Info (170201): Optimizations that may affect the design's routability were skipped

+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01

+Info (11888): Total time spent on timing analysis during the Fitter is 0.11 seconds.

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03

+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

+Info (144001): Generated suppressed messages file C:/New folder/ex7/output_files/ex7.fit.smsg

+Info: Quartus Prime Fitter was successful. 0 errors, 71 warnings

+    Info: Peak virtual memory: 2552 megabytes

+    Info: Processing ended: Tue Nov 22 12:50:57 2016

+    Info: Elapsed time: 00:00:28

+    Info: Total CPU time (on all processors): 00:00:48

+

+

++----------------------------+

+; Fitter Suppressed Messages ;

++----------------------------+

+The suppressed messages can be found in C:/New folder/ex7/output_files/ex7.fit.smsg.

+

+

diff --git a/part_2/ex7/output_files/ex7.fit.smsg b/part_2/ex7/output_files/ex7.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing

+Extra Info (176237): Finished Fast Input/Output/OE register processing

+Extra Info (176238): Start inferring scan chains for DSP blocks

+Extra Info (176239): Inferring scan chains for DSP blocks is complete

+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density

+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

diff --git a/part_2/ex7/output_files/ex7.fit.summary b/part_2/ex7/output_files/ex7.fit.summary
new file mode 100755
index 0000000..5724b6c
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Nov 22 12:50:57 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex7

+Top-level Entity Name : ex7

+Family : Cyclone V

+Device : 5CSEMA5F31C6

+Timing Models : Final

+Logic utilization (in ALMs) : 9 / 32,070 ( < 1 % )

+Total registers : 10

+Total pins : 15 / 457 ( 3 % )

+Total virtual pins : 0

+Total block memory bits : 0 / 4,065,280 ( 0 % )

+Total RAM Blocks : 0 / 397 ( 0 % )

+Total DSP Blocks : 0 / 87 ( 0 % )

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0 / 6 ( 0 % )

+Total DLLs : 0 / 4 ( 0 % )

diff --git a/part_2/ex7/output_files/ex7.flow.rpt b/part_2/ex7/output_files/ex7.flow.rpt
new file mode 100755
index 0000000..0687695
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.flow.rpt
@@ -0,0 +1,128 @@
+Flow report for ex7

+Tue Nov 22 12:51:09 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Flow Summary

+  3. Flow Settings

+  4. Flow Non-Default Global Settings

+  5. Flow Elapsed Time

+  6. Flow OS Summary

+  7. Flow Log

+  8. Flow Messages

+  9. Flow Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Flow Summary                                                                      ;

++---------------------------------+-------------------------------------------------+

+; Flow Status                     ; Successful - Tue Nov 22 12:51:04 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex7                                             ;

+; Top-level Entity Name           ; ex7                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 9 / 32,070 ( < 1 % )                            ;

+; Total registers                 ; 10                                              ;

+; Total pins                      ; 15 / 457 ( 3 % )                                ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++-----------------------------------------+

+; Flow Settings                           ;

++-------------------+---------------------+

+; Option            ; Setting             ;

++-------------------+---------------------+

+; Start date & time ; 11/22/2016 12:50:19 ;

+; Main task         ; Compilation         ;

+; Revision Name     ; ex7                 ;

++-------------------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------+

+; Flow Non-Default Global Settings                                                                                       ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; COMPILER_SIGNATURE_ID               ; 260248564170200.147981901905736       ; --            ; --          ; --         ;

+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;

+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;

+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;

+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;

+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;

+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;

+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;

+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------+

+; Flow Elapsed Time                                                                                                             ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Analysis & Synthesis      ; 00:00:11     ; 1.0                     ; 895 MB              ; 00:00:22                           ;

+; Fitter                    ; 00:00:28     ; 1.0                     ; 2552 MB             ; 00:00:48                           ;

+; Assembler                 ; 00:00:06     ; 1.0                     ; 891 MB              ; 00:00:06                           ;

+; TimeQuest Timing Analyzer ; 00:00:04     ; 1.0                     ; 1179 MB             ; 00:00:04                           ;

+; Total                     ; 00:00:49     ; --                      ; --                  ; 00:01:20                           ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+

+

++----------------------------------------------------------------------------------------+

+; Flow OS Summary                                                                        ;

++---------------------------+------------------+-----------+------------+----------------+

+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;

++---------------------------+------------------+-----------+------------+----------------+

+; Analysis & Synthesis      ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

+; Fitter                    ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

+; Assembler                 ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

+; TimeQuest Timing Analyzer ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;

++---------------------------+------------------+-----------+------------+----------------+

+

+

+------------

+; Flow Log ;

+------------

+quartus_map --read_settings_files=on --write_settings_files=off ex7 -c ex7

+quartus_fit --read_settings_files=off --write_settings_files=off ex7 -c ex7

+quartus_asm --read_settings_files=off --write_settings_files=off ex7 -c ex7

+quartus_sta ex7 -c ex7

+

+

+

diff --git a/part_2/ex7/output_files/ex7.jdi b/part_2/ex7/output_files/ex7.jdi
new file mode 100755
index 0000000..3307023
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>

+  <project>

+    <hash md5_digest_80b="46a00ad9013248c44cb6"/>

+  </project>

+  <file_info>

+    <file device="5CSEMA5F31C6" path="ex7.sof" usercode="0xFFFFFFFF"/>

+  </file_info>

+</sld_project_info>

diff --git a/part_2/ex7/output_files/ex7.map.rpt b/part_2/ex7/output_files/ex7.map.rpt
new file mode 100755
index 0000000..8545dc9
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.map.rpt
@@ -0,0 +1,323 @@
+Analysis & Synthesis report for ex7

+Tue Nov 22 12:50:29 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Analysis & Synthesis Summary

+  3. Analysis & Synthesis Settings

+  4. Parallel Compilation

+  5. Analysis & Synthesis Source Files Read

+  6. Analysis & Synthesis Resource Usage Summary

+  7. Analysis & Synthesis Resource Utilization by Entity

+  8. General Register Statistics

+  9. Inverted Register Statistics

+ 10. Port Connectivity Checks: "LFSR:comb_3"

+ 11. Post-Synthesis Netlist Statistics for Top Partition

+ 12. Elapsed Time Per Partition

+ 13. Analysis & Synthesis Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Analysis & Synthesis Summary                                                      ;

++---------------------------------+-------------------------------------------------+

+; Analysis & Synthesis Status     ; Successful - Tue Nov 22 12:50:29 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex7                                             ;

+; Top-level Entity Name           ; ex7                                             ;

+; Family                          ; Cyclone V                                       ;

+; Logic utilization (in ALMs)     ; N/A                                             ;

+; Total registers                 ; 7                                               ;

+; Total pins                      ; 15                                              ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0                                               ;

+; Total DSP Blocks                ; 0                                               ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0                                               ;

+; Total DLLs                      ; 0                                               ;

++---------------------------------+-------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Settings                                                                                             ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Option                                                                          ; Setting            ; Default Value      ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;

+; Top-level entity name                                                           ; ex7                ; ex7                ;

+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;

+; Use smart compilation                                                           ; Off                ; Off                ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;

+; Enable compact report table                                                     ; Off                ; Off                ;

+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;

+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;

+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;

+; Preserve fewer node names                                                       ; On                 ; On                 ;

+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;

+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;

+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;

+; State Machine Processing                                                        ; Auto               ; Auto               ;

+; Safe State Machine                                                              ; Off                ; Off                ;

+; Extract Verilog State Machines                                                  ; On                 ; On                 ;

+; Extract VHDL State Machines                                                     ; On                 ; On                 ;

+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;

+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;

+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;

+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;

+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;

+; Parallel Synthesis                                                              ; On                 ; On                 ;

+; DSP Block Balancing                                                             ; Auto               ; Auto               ;

+; NOT Gate Push-Back                                                              ; On                 ; On                 ;

+; Power-Up Don't Care                                                             ; On                 ; On                 ;

+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;

+; Remove Duplicate Registers                                                      ; On                 ; On                 ;

+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;

+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;

+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;

+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;

+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;

+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;

+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;

+; Optimization Technique                                                          ; Balanced           ; Balanced           ;

+; Carry Chain Length                                                              ; 70                 ; 70                 ;

+; Auto Carry Chains                                                               ; On                 ; On                 ;

+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;

+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;

+; Auto ROM Replacement                                                            ; On                 ; On                 ;

+; Auto RAM Replacement                                                            ; On                 ; On                 ;

+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;

+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;

+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;

+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;

+; Strict RAM Replacement                                                          ; Off                ; Off                ;

+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;

+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;

+; Auto Resource Sharing                                                           ; Off                ; Off                ;

+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;

+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;

+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;

+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;

+; Report Parameter Settings                                                       ; On                 ; On                 ;

+; Report Source Assignments                                                       ; On                 ; On                 ;

+; Report Connectivity Checks                                                      ; On                 ; On                 ;

+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;

+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;

+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;

+; HDL message level                                                               ; Level2             ; Level2             ;

+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;

+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;

+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;

+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;

+; Clock MUX Protection                                                            ; On                 ; On                 ;

+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;

+; Block Design Naming                                                             ; Auto               ; Auto               ;

+; SDC constraint protection                                                       ; Off                ; Off                ;

+; Synthesis Effort                                                                ; Auto               ; Auto               ;

+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;

+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;

+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;

+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;

+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;

+; Synthesis Seed                                                                  ; 1                  ; 1                  ;

+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;

+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processors 2-4         ;   0.0%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Source Files Read                                                                                                      ;

++----------------------------------+-----------------+------------------------------+-----------------------------------------------+---------+

+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                  ; Library ;

++----------------------------------+-----------------+------------------------------+-----------------------------------------------+---------+

+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File        ; C:/New folder/ex7/verilog_files/hex_to_7seg.v ;         ;

+; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File        ; C:/New folder/ex7/verilog_files/LFSR.v        ;         ;

+; ex7.v                            ; yes             ; Auto-Found Verilog HDL File  ; C:/New folder/ex7/ex7.v                       ;         ;

++----------------------------------+-----------------+------------------------------+-----------------------------------------------+---------+

+

+

++--------------------------------------------------------------------+

+; Analysis & Synthesis Resource Usage Summary                        ;

++---------------------------------------------+----------------------+

+; Resource                                    ; Usage                ;

++---------------------------------------------+----------------------+

+; Estimate of Logic utilization (ALMs needed) ; 9                    ;

+;                                             ;                      ;

+; Combinational ALUT usage for logic          ; 16                   ;

+;     -- 7 input functions                    ; 0                    ;

+;     -- 6 input functions                    ; 0                    ;

+;     -- 5 input functions                    ; 0                    ;

+;     -- 4 input functions                    ; 7                    ;

+;     -- <=3 input functions                  ; 9                    ;

+;                                             ;                      ;

+; Dedicated logic registers                   ; 7                    ;

+;                                             ;                      ;

+; I/O pins                                    ; 15                   ;

+;                                             ;                      ;

+; Total DSP Blocks                            ; 0                    ;

+;                                             ;                      ;

+; Maximum fan-out node                        ; LFSR:comb_3|COUNT[1] ;

+; Maximum fan-out                             ; 9                    ;

+; Total fan-out                               ; 95                   ;

+; Average fan-out                             ; 1.79                 ;

++---------------------------------------------+----------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                     ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+; |ex7                       ; 16 (0)            ; 7 (0)        ; 0                 ; 0          ; 15   ; 0            ; |ex7                ; ex7         ; work         ;

+;    |LFSR:comb_3|           ; 2 (2)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex7|LFSR:comb_3    ; LFSR        ; work         ;

+;    |hex_to_7seg:h0|        ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex7|hex_to_7seg:h0 ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:h1|        ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex7|hex_to_7seg:h1 ; hex_to_7seg ; work         ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++------------------------------------------------------+

+; General Register Statistics                          ;

++----------------------------------------------+-------+

+; Statistic                                    ; Value ;

++----------------------------------------------+-------+

+; Total registers                              ; 7     ;

+; Number of registers using Synchronous Clear  ; 0     ;

+; Number of registers using Synchronous Load   ; 0     ;

+; Number of registers using Asynchronous Clear ; 0     ;

+; Number of registers using Asynchronous Load  ; 0     ;

+; Number of registers using Clock Enable       ; 0     ;

+; Number of registers using Preset             ; 0     ;

++----------------------------------------------+-------+

+

+

++--------------------------------------------------+

+; Inverted Register Statistics                     ;

++----------------------------------------+---------+

+; Inverted Register                      ; Fan out ;

++----------------------------------------+---------+

+; LFSR:comb_3|COUNT[1]                   ; 9       ;

+; Total number of inverted registers = 1 ;         ;

++----------------------------------------+---------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "LFSR:comb_3"                                                                                                                                                           ;

++-------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Port  ; Type   ; Severity ; Details                                                                                                                                                               ;

++-------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; COUNT ; Output ; Warning  ; Output or bidir port (7 bits) is smaller than the port expression (8 bits) it drives.  The 1 most-significant bit(s) in the port expression will be connected to GND. ;

++-------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------+

+; Post-Synthesis Netlist Statistics for Top Partition ;

++-----------------------+-----------------------------+

+; Type                  ; Count                       ;

++-----------------------+-----------------------------+

+; arriav_ff             ; 7                           ;

+;     plain             ; 7                           ;

+; arriav_lcell_comb     ; 17                          ;

+;     normal            ; 17                          ;

+;         1 data inputs ; 2                           ;

+;         2 data inputs ; 1                           ;

+;         3 data inputs ; 7                           ;

+;         4 data inputs ; 7                           ;

+; boundary_port         ; 15                          ;

+;                       ;                             ;

+; Max LUT depth         ; 2.00                        ;

+; Average LUT depth     ; 1.20                        ;

++-----------------------+-----------------------------+

+

+

++-------------------------------+

+; Elapsed Time Per Partition    ;

++----------------+--------------+

+; Partition Name ; Elapsed Time ;

++----------------+--------------+

+; Top            ; 00:00:00     ;

++----------------+--------------+

+

+

++-------------------------------+

+; Analysis & Synthesis Messages ;

++-------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Analysis & Synthesis

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Tue Nov 22 12:50:18 2016

+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex7 -c ex7

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v

+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex7/verilog_files/hex_to_7seg.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v

+    Info (12023): Found entity 1: LFSR File: C:/New folder/ex7/verilog_files/LFSR.v Line: 1

+Warning (12125): Using design file ex7.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project

+    Info (12023): Found entity 1: ex7 File: C:/New folder/ex7/ex7.v Line: 1

+Critical Warning (10846): Verilog HDL Instantiation warning at ex7.v(8): instance has no name File: C:/New folder/ex7/ex7.v Line: 8

+Info (12127): Elaborating entity "ex7" for the top level hierarchy

+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:comb_3" File: C:/New folder/ex7/ex7.v Line: 8

+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:h0" File: C:/New folder/ex7/ex7.v Line: 10

+Warning (12011): Net is missing source, defaulting to GND

+    Warning (12110): Net "count[7]" is missing source, defaulting to GND File: C:/New folder/ex7/ex7.v Line: 6

+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder

+Info (286030): Timing-Driven Synthesis is running

+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

+Info (21057): Implemented 36 device resources after synthesis - the final resource count might be different

+    Info (21058): Implemented 1 input pins

+    Info (21059): Implemented 14 output pins

+    Info (21061): Implemented 21 logic cells

+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings

+    Info: Peak virtual memory: 895 megabytes

+    Info: Processing ended: Tue Nov 22 12:50:29 2016

+    Info: Elapsed time: 00:00:11

+    Info: Total CPU time (on all processors): 00:00:23

+

+

diff --git a/part_2/ex7/output_files/ex7.map.summary b/part_2/ex7/output_files/ex7.map.summary
new file mode 100755
index 0000000..f504c0a
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Nov 22 12:50:29 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex7

+Top-level Entity Name : ex7

+Family : Cyclone V

+Logic utilization (in ALMs) : N/A

+Total registers : 7

+Total pins : 15

+Total virtual pins : 0

+Total block memory bits : 0

+Total DSP Blocks : 0

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0

+Total DLLs : 0

diff --git a/part_2/ex7/output_files/ex7.pin b/part_2/ex7/output_files/ex7.pin
new file mode 100755
index 0000000..dd2eff1
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+ -- Your use of Altera Corporation's design tools, logic functions 

+ -- and other software and tools, and its AMPP partner logic 

+ -- functions, and any output files from any of the foregoing 

+ -- (including device programming or simulation files), and any 

+ -- associated documentation or information are expressly subject 

+ -- to the terms and conditions of the Altera Program License 

+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,

+ -- the Altera MegaCore Function License Agreement, or other 

+ -- applicable license agreement, including, without limitation, 

+ -- that your use is for the sole purpose of programming logic 

+ -- devices manufactured by Altera and sold by Altera or its 

+ -- authorized distributors.  Please refer to the applicable 

+ -- agreement for further details.

+ -- 

+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is

+ -- not intended for use as a Quartus Prime input file. This file cannot be used

+ -- to make Quartus Prime pin assignments - for instructions on how to make pin

+ -- assignments, please see Quartus Prime help.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- NC            : No Connect. This pin has no internal connection to the device.

+ -- DNU           : Do Not Use. This pin MUST NOT be connected.

+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.

+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).

+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC

+ --                 of its bank.

+ --                  Bank 3A:       2.5V

+ --                  Bank 3B:       2.5V

+ --                  Bank 4A:       2.5V

+ --                  Bank 5A:       3.3V

+ --                  Bank 5B:       2.5V

+ --                  Bank 6B:       2.5V

+ --                  Bank 6A:  2.5V

+ --                  Bank 7A:  2.5V

+ --                  Bank 7B:  2.5V

+ --                  Bank 7C:  2.5V

+ --                  Bank 7D:  2.5V

+ --                  Bank 8A:  2.5V

+ -- RREF          : External reference resistor for the quad, MUST be connected to

+ --                 GND via a 2k Ohm resistor.

+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.

+ --                  It can also be used to report unused dedicated pins. The connection

+ --                  on the board for unused dedicated pins depends on whether this will

+ --                  be used in a future design. One example is device migration. When

+ --                  using device migration, refer to the device pin-tables. If it is a

+ --                  GND pin in the pin table or if it will not be used in a future design

+ --                  for another purpose the it MUST be connected to GND. If it is an unused

+ --                  dedicated pin, then it can be connected to a valid signal on the board

+ --                  (low, high, or toggling) if that signal is required for a different

+ --                  revision of the design.

+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.

+ --                  This pin should be connected to GND. It may also be connected  to a

+ --                  valid signal  on the board  (low, high, or toggling)  if that signal

+ --                  is required for a different revision of the design.

+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND

+ --                  or leave it unconnected.

+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.

+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.

+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.

+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.

+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.

+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin

+ --                 must not be connected.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- Pin directions (input, output or bidir) are based on device operating in user mode.

+ ---------------------------------------------------------------------------------

+

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+CHIP  "ex7"  ASSIGNED TO AN: 5CSEMA5F31C6

+

+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

+-------------------------------------------------------------------------------------------------------------

+GND                          : A2        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                

+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                

+GND                          : A12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                

+GND                          : A17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                

+GND                          : A22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                

+GND                          : A26       :        :                   :         : 7A        :                

+GND                          : A27       : gnd    :                   :         :           :                

+HPS_TRST                     : A28       :        :                   :         : 7A        :                

+HPS_TMS                      : A29       :        :                   :         : 7A        :                

+GND                          : AA1       : gnd    :                   :         :           :                

+GND                          : AA2       : gnd    :                   :         :           :                

+GND                          : AA3       : gnd    :                   :         :           :                

+GND                          : AA4       : gnd    :                   :         :           :                

+VCC                          : AA5       : power  :                   : 1.1V    :           :                

+GND                          : AA6       : gnd    :                   :         :           :                

+DNU                          : AA7       :        :                   :         :           :                

+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                

+GND                          : AA9       : gnd    :                   :         :           :                

+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                

+GND                          : AA11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                

+VCCIO4A                      : AA17      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                

+GND                          : AA22      : gnd    :                   :         :           :                

+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                

+VCCIO5B                      : AA27      : power  :                   : 2.5V    : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                

+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                

+GND                          : AB1       : gnd    :                   :         :           :                

+GND                          : AB2       : gnd    :                   :         :           :                

+DNU                          : AB3       :        :                   :         :           :                

+DNU                          : AB4       :        :                   :         :           :                

+GND                          : AB5       : gnd    :                   :         :           :                

+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                

+GND                          : AB7       : gnd    :                   :         :           :                

+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                

+TDO                          : AB9       : output :                   :         : 3A        :                

+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                

+VCCIO3B                      : AB14      : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                

+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AB18      : power  :                   : 2.5V    : 3B, 4A    :                

+GND                          : AB19      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AB20      : power  :                   : 2.5V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB23      :        :                   :         : 5A        :                

+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                

+GND                          : AB29      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                

+GND                          : AC1       : gnd    :                   :         :           :                

+GND                          : AC2       : gnd    :                   :         :           :                

+GND                          : AC3       : gnd    :                   :         :           :                

+GND                          : AC4       : gnd    :                   :         :           :                

+TCK                          : AC5       : input  :                   :         : 3A        :                

+GND                          : AC6       : gnd    :                   :         :           :                

+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                

+GND                          : AC8       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                

+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                

+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                

+VCCPD3B4A                    : AC13      : power  :                   : 2.5V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                

+VCCPD3B4A                    : AC15      : power  :                   : 2.5V    : 3B, 4A    :                

+GND                          : AC16      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AC17      : power  :                   : 2.5V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AC19      : power  :                   : 2.5V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                

+VCCIO4A                      : AC21      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                

+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                

+GND                          : AC26      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC28      :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC29      :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC30      :        :                   :         : 5B        :                

+GND                          : AD1       : gnd    :                   :         :           :                

+GND                          : AD2       : gnd    :                   :         :           :                

+DNU                          : AD3       :        :                   :         :           :                

+DNU                          : AD4       :        :                   :         :           :                

+GND                          : AD5       : gnd    :                   :         :           :                

+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                

+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                

+VCCIO3B                      : AD13      : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                

+DNU                          : AD15      :        :                   :         :           :                

+VCCPD3B4A                    : AD16      : power  :                   : 2.5V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                

+VCCIO4A                      : AD18      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                

+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                

+GND                          : AD23      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                

+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD29      :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD30      :        :                   :         : 5B        :                

+GND                          : AE1       : gnd    :                   :         :           :                

+GND                          : AE2       : gnd    :                   :         :           :                

+GND                          : AE3       : gnd    :                   :         :           :                

+GND                          : AE4       : gnd    :                   :         :           :                

+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                

+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                

+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                

+GND                          : AE10      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                

+VCCIO3B                      : AE15      : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                

+GND                          : AE20      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AE21      : power  :                   : 2.5V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                

+VCCIO4A                      : AE25      : power  :                   : 2.5V    : 4A        :                

+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE29      :        :                   :         : 5B        :                

+VCCIO5B                      : AE30      : power  :                   : 2.5V    : 5B        :                

+GND                          : AF1       : gnd    :                   :         :           :                

+GND                          : AF2       : gnd    :                   :         :           :                

+GND                          : AF3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                

+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                

+GND                          : AF12      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                

+GND                          : AF17      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                

+VCCIO4A                      : AF22      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                

+GND                          : AF27      : gnd    :                   :         :           :                

+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                

+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                

+GND                          : AG9       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                

+GND                          : AG14      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                

+VCCIO4A                      : AG19      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                

+GND                          : AG24      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                

+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                

+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AH1       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                

+GND                          : AH6       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                

+GND                          : AH11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                

+VCCIO4A                      : AH16      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                

+GND                          : AH21      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                

+VCCIO4A                      : AH26      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                

+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                

+GND                          : AJ3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                

+VCCIO3B                      : AJ8       : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                

+VCCIO3B                      : AJ13      : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                

+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                

+GND                          : AJ18      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                

+VCCIO4A                      : AJ23      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                

+GND                          : AJ28      : gnd    :                   :         :           :                

+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AJ30      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                

+GND                          : AK5       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                

+VCCIO3B                      : AK10      : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                

+GND                          : AK15      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                

+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                

+VCCIO4A                      : AK20      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                

+GND                          : AK25      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                

+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                

+GND                          : B9        : gnd    :                   :         :           :                

+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                

+GND                          : B14       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                

+GND                          : B19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                

+GND                          : B24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                

+HPS_TDI                      : B27       :        :                   :         : 7A        :                

+HPS_TDO                      : B28       :        :                   :         : 7A        :                

+GND                          : B29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                

+GND                          : C1        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                

+GND                          : C6        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                

+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                

+GND                          : C16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                

+GND                          : C21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                

+GND                          : C26       : gnd    :                   :         :           :                

+HPS_nRST                     : C27       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                

+GND                          : D3        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                

+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                

+GND                          : D13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                

+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                

+GND                          : D23       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                

+HPS_CLK1                     : D25       :        :                   :         : 7A        :                

+GND                          : D26       :        :                   :         : 7A        :                

+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                

+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                

+GND                          : E10       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                

+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                

+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                

+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                

+GND                          : E25       : gnd    :                   :         :           :                

+DNU                          : E26       :        :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                

+GND                          : E30       : gnd    :                   :         :           :                

+DNU                          : F1        :        :                   :         :           :                

+GND                          : F2        : gnd    :                   :         :           :                

+CONF_DONE                    : F3        :        :                   :         : 9A        :                

+nSTATUS                      : F4        :        :                   :         : 9A        :                

+GND                          : F5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                

+GND                          : F7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                

+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                

+GND                          : F17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                

+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                

+HPS_nPOR                     : F23       :        :                   :         : 7A        :                

+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                

+HPS_CLK2                     : F25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                

+GND                          : F27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                

+GND                          : G1        :        :                   :         :           :                

+DNU                          : G2        :        :                   :         :           :                

+GND                          : G3        : gnd    :                   :         :           :                

+GND                          : G4        : gnd    :                   :         :           :                

+nCE                          : G5        :        :                   :         : 9A        :                

+MSEL2                        : G6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                

+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                

+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                

+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                

+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                

+GND                          : G24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                

+GND                          : H1        : gnd    :                   :         :           :                

+GND                          : H2        : gnd    :                   :         :           :                

+DNU                          : H3        :        :                   :         :           :                

+DNU                          : H4        :        :                   :         :           :                

+GND                          : H5        : gnd    :                   :         :           :                

+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                

+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                

+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                

+GND                          : H11       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                

+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                

+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                

+HPS_TCK                      : H22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                

+GND                          : J1        : gnd    :                   :         :           :                

+GND                          : J2        : gnd    :                   :         :           :                

+GND                          : J3        : gnd    :                   :         :           :                

+GND                          : J4        : gnd    :                   :         :           :                

+nCONFIG                      : J5        :        :                   :         : 9A        :                

+GND                          : J6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                

+GND                          : J8        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                

+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                

+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                

+DNU                          : J15       :        :                   :         :           :                

+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                

+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                

+GND                          : J18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                

+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                

+GND                          : J22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                

+GND                          : J28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                

+GND                          : K1        : gnd    :                   :         :           :                

+GND                          : K2        : gnd    :                   :         :           :                

+DNU                          : K3        :        :                   :         :           :                

+DNU                          : K4        :        :                   :         :           :                

+GND                          : K5        : gnd    :                   :         :           :                

+MSEL1                        : K6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                

+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                

+GND                          : K10       : gnd    :                   :         :           :                

+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                

+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                

+GND                          : K15       : gnd    :                   :         :           :                

+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                

+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                

+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                

+GND                          : K20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                

+GND                          : K25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                

+GND                          : L1        : gnd    :                   :         :           :                

+GND                          : L2        : gnd    :                   :         :           :                

+GND                          : L3        : gnd    :                   :         :           :                

+GND                          : L4        : gnd    :                   :         :           :                

+VCC                          : L5        : power  :                   : 1.1V    :           :                

+GND                          : L6        : gnd    :                   :         :           :                

+MSEL3                        : L7        :        :                   :         : 9A        :                

+MSEL0                        : L8        :        :                   :         : 9A        :                

+MSEL4                        : L9        :        :                   :         : 9A        :                

+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                

+GND                          : L11       : gnd    :                   :         :           :                

+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                

+GND                          : L13       : gnd    :                   :         :           :                

+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                

+GND                          : L15       : gnd    :                   :         :           :                

+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                

+GND                          : L17       : gnd    :                   :         :           :                

+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                

+GND                          : L19       : gnd    :                   :         :           :                

+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                

+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                

+GND                          : L22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                

+GND                          : M1        : gnd    :                   :         :           :                

+GND                          : M2        : gnd    :                   :         :           :                

+DNU                          : M3        :        :                   :         :           :                

+DNU                          : M4        :        :                   :         :           :                

+GND                          : M5        : gnd    :                   :         :           :                

+VCC                          : M6        : power  :                   : 1.1V    :           :                

+GND                          : M7        : gnd    :                   :         :           :                

+GND                          : M8        : gnd    :                   :         :           :                

+VCC                          : M9        : power  :                   : 1.1V    :           :                

+GND                          : M10       : gnd    :                   :         :           :                

+VCC                          : M11       : power  :                   : 1.1V    :           :                

+GND                          : M12       : gnd    :                   :         :           :                

+VCC                          : M13       : power  :                   : 1.1V    :           :                

+GND                          : M14       : gnd    :                   :         :           :                

+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                

+GND                          : M16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                

+GND                          : M18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                

+GND                          : M20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                

+GND                          : M29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                

+GND                          : N1        : gnd    :                   :         :           :                

+GND                          : N2        : gnd    :                   :         :           :                

+GND                          : N3        : gnd    :                   :         :           :                

+GND                          : N4        : gnd    :                   :         :           :                

+VCC                          : N5        : power  :                   : 1.1V    :           :                

+GND                          : N6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                

+GND                          : N8        : gnd    :                   :         :           :                

+GND                          : N9        : gnd    :                   :         :           :                

+VCC                          : N10       : power  :                   : 1.1V    :           :                

+GND                          : N11       : gnd    :                   :         :           :                

+VCC                          : N12       : power  :                   : 1.1V    :           :                

+GND                          : N13       : gnd    :                   :         :           :                

+VCC                          : N14       : power  :                   : 1.1V    :           :                

+GND                          : N15       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                

+GND                          : N17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                

+GND                          : N19       : gnd    :                   :         :           :                

+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                

+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                

+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                

+GND                          : N26       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                

+GND                          : P1        : gnd    :                   :         :           :                

+GND                          : P2        : gnd    :                   :         :           :                

+DNU                          : P3        :        :                   :         :           :                

+DNU                          : P4        :        :                   :         :           :                

+GND                          : P5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                

+GND                          : P7        : gnd    :                   :         :           :                

+GND                          : P8        : gnd    :                   :         :           :                

+GND                          : P9        : gnd    :                   :         :           :                

+GND                          : P10       : gnd    :                   :         :           :                

+VCC                          : P11       : power  :                   : 1.1V    :           :                

+GND                          : P12       : gnd    :                   :         :           :                

+VCC                          : P13       : power  :                   : 1.1V    :           :                

+GND                          : P14       : gnd    :                   :         :           :                

+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                

+GND                          : P16       : gnd    :                   :         :           :                

+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                

+GND                          : P18       : gnd    :                   :         :           :                

+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                

+GND                          : P20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                

+GND                          : R1        : gnd    :                   :         :           :                

+GND                          : R2        : gnd    :                   :         :           :                

+GND                          : R3        : gnd    :                   :         :           :                

+GND                          : R4        : gnd    :                   :         :           :                

+VCC                          : R5        : power  :                   : 1.1V    :           :                

+GND                          : R6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                

+GND                          : R8        : gnd    :                   :         :           :                

+GND                          : R9        : gnd    :                   :         :           :                

+VCC                          : R10       : power  :                   : 1.1V    :           :                

+GND                          : R11       : gnd    :                   :         :           :                

+VCC                          : R12       : power  :                   : 1.1V    :           :                

+GND                          : R13       : gnd    :                   :         :           :                

+VCC                          : R14       : power  :                   : 1.1V    :           :                

+GND                          : R15       : gnd    :                   :         :           :                

+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                

+GND                          : R17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                

+GND                          : R30       : gnd    :                   :         :           :                

+GND                          : T1        : gnd    :                   :         :           :                

+GND                          : T2        : gnd    :                   :         :           :                

+DNU                          : T3        :        :                   :         :           :                

+DNU                          : T4        :        :                   :         :           :                

+GND                          : T5        : gnd    :                   :         :           :                

+VCC                          : T6        : power  :                   : 1.1V    :           :                

+GND                          : T7        : gnd    :                   :         :           :                

+GND                          : T8        : gnd    :                   :         :           :                

+GND                          : T9        : gnd    :                   :         :           :                

+GND                          : T10       : gnd    :                   :         :           :                

+VCC                          : T11       : power  :                   : 1.1V    :           :                

+GND                          : T12       : gnd    :                   :         :           :                

+VCC                          : T13       : power  :                   : 1.1V    :           :                

+GND                          : T14       : gnd    :                   :         :           :                

+GND                          : T15       : gnd    :                   :         :           :                

+GND                          : T16       : gnd    :                   :         :           :                

+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                

+GND                          : T18       : gnd    :                   :         :           :                

+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                

+GND                          : T20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                

+GND                          : T27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                

+GND                          : U1        : gnd    :                   :         :           :                

+GND                          : U2        : gnd    :                   :         :           :                

+GND                          : U3        : gnd    :                   :         :           :                

+GND                          : U4        : gnd    :                   :         :           :                

+VCC                          : U5        : power  :                   : 1.1V    :           :                

+GND                          : U6        : gnd    :                   :         :           :                

+DCLK                         : U7        :        :                   :         : 3A        :                

+TDI                          : U8        : input  :                   :         : 3A        :                

+GND                          : U9        : gnd    :                   :         :           :                

+VCC                          : U10       : power  :                   : 1.1V    :           :                

+GND                          : U11       : gnd    :                   :         :           :                

+VCC                          : U12       : power  :                   : 1.1V    :           :                

+GND                          : U13       : gnd    :                   :         :           :                

+VCC                          : U14       : power  :                   : 1.1V    :           :                

+GND                          : U15       : gnd    :                   :         :           :                

+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                

+GND                          : U17       : gnd    :                   :         :           :                

+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                

+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                

+VCC                          : U21       : power  :                   : 1.1V    :           :                

+GND                          : U22       : gnd    :                   :         :           :                

+VCCPD5B                      : U23       : power  :                   : 2.5V    : 5B        :                

+GND                          : U24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                

+GND                          : U29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                

+GND                          : V1        : gnd    :                   :         :           :                

+GND                          : V2        : gnd    :                   :         :           :                

+DNU                          : V3        :        :                   :         :           :                

+DNU                          : V4        :        :                   :         :           :                

+GND                          : V5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                

+GND                          : V7        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                

+TMS                          : V9        : input  :                   :         : 3A        :                

+GND                          : V10       : gnd    :                   :         :           :                

+VCC                          : V11       : power  :                   : 1.1V    :           :                

+GND                          : V12       : gnd    :                   :         :           :                

+VCC                          : V13       : power  :                   : 1.1V    :           :                

+GND                          : V14       : gnd    :                   :         :           :                

+VCC                          : V15       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                

+GND                          : V19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                

+GND                          : V21       : gnd    :                   :         :           :                

+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                

+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                

+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                

+GND                          : W1        : gnd    :                   :         :           :                

+GND                          : W2        : gnd    :                   :         :           :                

+GND                          : W3        : gnd    :                   :         :           :                

+GND                          : W4        : gnd    :                   :         :           :                

+VCC                          : W5        : power  :                   : 1.1V    :           :                

+GND                          : W6        : gnd    :                   :         :           :                

+GND                          : W7        : gnd    :                   :         :           :                

+GND                          : W8        : gnd    :                   :         :           :                

+GND                          : W9        : gnd    :                   :         :           :                

+VCC                          : W10       : power  :                   : 1.1V    :           :                

+GND                          : W11       : gnd    :                   :         :           :                

+VCC                          : W12       : power  :                   : 1.1V    :           :                

+GND                          : W13       : gnd    :                   :         :           :                

+VCC                          : W14       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                

+GND                          : W18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                

+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                

+GND                          : W28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                

+GND                          : Y1        : gnd    :                   :         :           :                

+GND                          : Y2        : gnd    :                   :         :           :                

+DNU                          : Y3        :        :                   :         :           :                

+DNU                          : Y4        :        :                   :         :           :                

+GND                          : Y5        : gnd    :                   :         :           :                

+VCC                          : Y6        : power  :                   : 1.1V    :           :                

+GND                          : Y7        : gnd    :                   :         :           :                

+GND                          : Y8        : gnd    :                   :         :           :                

+VCC                          : Y9        : power  :                   : 1.1V    :           :                

+GND                          : Y10       : gnd    :                   :         :           :                

+VCC                          : Y11       : power  :                   : 1.1V    :           :                

+GND                          : Y12       : gnd    :                   :         :           :                

+VCC                          : Y13       : power  :                   : 1.1V    :           :                

+GND                          : Y14       : gnd    :                   :         :           :                

+GND                          : Y15       : gnd    :                   :         :           :                

+KEY3                         : Y16       : input  : 2.5 V             :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                

+GND                          : Y20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                

+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                

+GND                          : Y25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                

+GND                          : Y30       : gnd    :                   :         :           :                

diff --git a/part_2/ex7/output_files/ex7.sld b/part_2/ex7/output_files/ex7.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.sld
@@ -0,0 +1 @@
+<sld_project_info/>

diff --git a/part_2/ex7/output_files/ex7.sof b/part_2/ex7/output_files/ex7.sof
new file mode 100755
index 0000000..65c9e5e
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.sof
diff --git a/part_2/ex7/output_files/ex7.sta.rpt b/part_2/ex7/output_files/ex7.sta.rpt
new file mode 100755
index 0000000..0917dcb
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.sta.rpt
@@ -0,0 +1,659 @@
+TimeQuest Timing Analyzer report for ex7

+Tue Nov 22 12:51:09 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. TimeQuest Timing Analyzer Summary

+  3. Parallel Compilation

+  4. Clocks

+  5. Slow 1100mV 85C Model Fmax Summary

+  6. Timing Closure Recommendations

+  7. Slow 1100mV 85C Model Setup Summary

+  8. Slow 1100mV 85C Model Hold Summary

+  9. Slow 1100mV 85C Model Recovery Summary

+ 10. Slow 1100mV 85C Model Removal Summary

+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary

+ 12. Slow 1100mV 85C Model Metastability Summary

+ 13. Slow 1100mV 0C Model Fmax Summary

+ 14. Slow 1100mV 0C Model Setup Summary

+ 15. Slow 1100mV 0C Model Hold Summary

+ 16. Slow 1100mV 0C Model Recovery Summary

+ 17. Slow 1100mV 0C Model Removal Summary

+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary

+ 19. Slow 1100mV 0C Model Metastability Summary

+ 20. Fast 1100mV 85C Model Setup Summary

+ 21. Fast 1100mV 85C Model Hold Summary

+ 22. Fast 1100mV 85C Model Recovery Summary

+ 23. Fast 1100mV 85C Model Removal Summary

+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary

+ 25. Fast 1100mV 85C Model Metastability Summary

+ 26. Fast 1100mV 0C Model Setup Summary

+ 27. Fast 1100mV 0C Model Hold Summary

+ 28. Fast 1100mV 0C Model Recovery Summary

+ 29. Fast 1100mV 0C Model Removal Summary

+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary

+ 31. Fast 1100mV 0C Model Metastability Summary

+ 32. Multicorner Timing Analysis Summary

+ 33. Board Trace Model Assignments

+ 34. Input Transition Times

+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)

+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)

+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)

+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)

+ 39. Setup Transfers

+ 40. Hold Transfers

+ 41. Report TCCS

+ 42. Report RSKM

+ 43. Unconstrained Paths Summary

+ 44. Clock Status Summary

+ 45. Unconstrained Output Ports

+ 46. Unconstrained Output Ports

+ 47. TimeQuest Timing Analyzer Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------------------------+

+; TimeQuest Timing Analyzer Summary                                               ;

++-----------------------+---------------------------------------------------------+

+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Timing Analyzer       ; TimeQuest                                               ;

+; Revision Name         ; ex7                                                     ;

+; Device Family         ; Cyclone V                                               ;

+; Device Name           ; 5CSEMA5F31C6                                            ;

+; Timing Models         ; Final                                                   ;

+; Delay Model           ; Combined                                                ;

+; Rise/Fall Delays      ; Enabled                                                 ;

++-----------------------+---------------------------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.02        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   1.6%      ;

+;     Processors 3-4         ;   0.3%      ;

++----------------------------+-------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Clocks                                                                                                                                                                           ;

++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+

+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets  ;

++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+

+; KEY3       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { KEY3 } ;

++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+

+

+

++--------------------------------------------------------------------------------------------+

+; Slow 1100mV 85C Model Fmax Summary                                                         ;

++------------+-----------------+------------+------------------------------------------------+

+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                           ;

++------------+-----------------+------------+------------------------------------------------+

+; 924.21 MHz ; 717.36 MHz      ; KEY3       ; limit due to minimum period restriction (tmin) ;

++------------+-----------------+------------+------------------------------------------------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

+----------------------------------

+; Timing Closure Recommendations ;

+----------------------------------

+HTML report is unavailable in plain text report export.

+

+

++-------------------------------------+

+; Slow 1100mV 85C Model Setup Summary ;

++-------+--------+--------------------+

+; Clock ; Slack  ; End Point TNS      ;

++-------+--------+--------------------+

+; KEY3  ; -0.082 ; -0.115             ;

++-------+--------+--------------------+

+

+

++------------------------------------+

+; Slow 1100mV 85C Model Hold Summary ;

++-------+-------+--------------------+

+; Clock ; Slack ; End Point TNS      ;

++-------+-------+--------------------+

+; KEY3  ; 0.347 ; 0.000              ;

++-------+-------+--------------------+

+

+

+------------------------------------------

+; Slow 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Slow 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++---------------------------------------------------+

+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;

++-------+--------+----------------------------------+

+; Clock ; Slack  ; End Point TNS                    ;

++-------+--------+----------------------------------+

+; KEY3  ; -0.394 ; -5.179                           ;

++-------+--------+----------------------------------+

+

+

+-----------------------------------------------

+; Slow 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------------------------------------------------+

+; Slow 1100mV 0C Model Fmax Summary                                                          ;

++------------+-----------------+------------+------------------------------------------------+

+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                           ;

++------------+-----------------+------------+------------------------------------------------+

+; 887.31 MHz ; 717.36 MHz      ; KEY3       ; limit due to minimum period restriction (tmin) ;

++------------+-----------------+------------+------------------------------------------------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

++------------------------------------+

+; Slow 1100mV 0C Model Setup Summary ;

++-------+--------+-------------------+

+; Clock ; Slack  ; End Point TNS     ;

++-------+--------+-------------------+

+; KEY3  ; -0.127 ; -0.175            ;

++-------+--------+-------------------+

+

+

++-----------------------------------+

+; Slow 1100mV 0C Model Hold Summary ;

++-------+-------+-------------------+

+; Clock ; Slack ; End Point TNS     ;

++-------+-------+-------------------+

+; KEY3  ; 0.326 ; 0.000             ;

++-------+-------+-------------------+

+

+

+-----------------------------------------

+; Slow 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Slow 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------+

+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;

++-------+--------+---------------------------------+

+; Clock ; Slack  ; End Point TNS                   ;

++-------+--------+---------------------------------+

+; KEY3  ; -0.394 ; -5.505                          ;

++-------+--------+---------------------------------+

+

+

+----------------------------------------------

+; Slow 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++-------------------------------------+

+; Fast 1100mV 85C Model Setup Summary ;

++-------+-------+---------------------+

+; Clock ; Slack ; End Point TNS       ;

++-------+-------+---------------------+

+; KEY3  ; 0.377 ; 0.000               ;

++-------+-------+---------------------+

+

+

++------------------------------------+

+; Fast 1100mV 85C Model Hold Summary ;

++-------+-------+--------------------+

+; Clock ; Slack ; End Point TNS      ;

++-------+-------+--------------------+

+; KEY3  ; 0.197 ; 0.000              ;

++-------+-------+--------------------+

+

+

+------------------------------------------

+; Fast 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Fast 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++---------------------------------------------------+

+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;

++-------+--------+----------------------------------+

+; Clock ; Slack  ; End Point TNS                    ;

++-------+--------+----------------------------------+

+; KEY3  ; -0.085 ; -0.831                           ;

++-------+--------+----------------------------------+

+

+

+-----------------------------------------------

+; Fast 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++------------------------------------+

+; Fast 1100mV 0C Model Setup Summary ;

++-------+-------+--------------------+

+; Clock ; Slack ; End Point TNS      ;

++-------+-------+--------------------+

+; KEY3  ; 0.402 ; 0.000              ;

++-------+-------+--------------------+

+

+

++-----------------------------------+

+; Fast 1100mV 0C Model Hold Summary ;

++-------+-------+-------------------+

+; Clock ; Slack ; End Point TNS     ;

++-------+-------+-------------------+

+; KEY3  ; 0.178 ; 0.000             ;

++-------+-------+-------------------+

+

+

+-----------------------------------------

+; Fast 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Fast 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------+

+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;

++-------+--------+---------------------------------+

+; Clock ; Slack  ; End Point TNS                   ;

++-------+--------+---------------------------------+

+; KEY3  ; -0.085 ; -0.838                          ;

++-------+--------+---------------------------------+

+

+

+----------------------------------------------

+; Fast 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++------------------------------------------------------------------------------+

+; Multicorner Timing Analysis Summary                                          ;

++------------------+--------+-------+----------+---------+---------------------+

+; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;

++------------------+--------+-------+----------+---------+---------------------+

+; Worst-case Slack ; -0.127 ; 0.178 ; N/A      ; N/A     ; -0.394              ;

+;  KEY3            ; -0.127 ; 0.178 ; N/A      ; N/A     ; -0.394              ;

+; Design-wide TNS  ; -0.175 ; 0.0   ; 0.0      ; 0.0     ; -5.505              ;

+;  KEY3            ; -0.175 ; 0.000 ; N/A      ; N/A     ; -5.505              ;

++------------------+--------+-------+----------+---------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+

+

++---------------------------------------------------------+

+; Input Transition Times                                  ;

++------+--------------+-----------------+-----------------+

+; Pin  ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;

++------+--------------+-----------------+-----------------+

+; KEY3 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;

++------+--------------+-----------------+-----------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++-------------------------------------------------------------------+

+; Setup Transfers                                                   ;

++------------+----------+----------+----------+----------+----------+

+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++------------+----------+----------+----------+----------+----------+

+; KEY3       ; KEY3     ; 11       ; 0        ; 0        ; 0        ;

++------------+----------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

++-------------------------------------------------------------------+

+; Hold Transfers                                                    ;

++------------+----------+----------+----------+----------+----------+

+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++------------+----------+----------+----------+----------+----------+

+; KEY3       ; KEY3     ; 11       ; 0        ; 0        ; 0        ;

++------------+----------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

+---------------

+; Report TCCS ;

+---------------

+No dedicated SERDES Transmitter circuitry present in device or used in design

+

+

+---------------

+; Report RSKM ;

+---------------

+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design

+

+

++------------------------------------------------+

+; Unconstrained Paths Summary                    ;

++---------------------------------+-------+------+

+; Property                        ; Setup ; Hold ;

++---------------------------------+-------+------+

+; Illegal Clocks                  ; 0     ; 0    ;

+; Unconstrained Clocks            ; 0     ; 0    ;

+; Unconstrained Input Ports       ; 0     ; 0    ;

+; Unconstrained Input Port Paths  ; 0     ; 0    ;

+; Unconstrained Output Ports      ; 14    ; 14   ;

+; Unconstrained Output Port Paths ; 49    ; 49   ;

++---------------------------------+-------+------+

+

+

++-------------------------------------+

+; Clock Status Summary                ;

++--------+-------+------+-------------+

+; Target ; Clock ; Type ; Status      ;

++--------+-------+------+-------------+

+; KEY3   ; KEY3  ; Base ; Constrained ;

++--------+-------+------+-------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++------------------------------------+

+; TimeQuest Timing Analyzer Messages ;

++------------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime TimeQuest Timing Analyzer

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Tue Nov 22 12:51:05 2016

+Info: Command: quartus_sta ex7 -c ex7

+Info: qsta_default_script.tcl version: #1

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex7.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"

+Info (332105): Deriving Clocks

+    Info (332105): create_clock -period 1.000 -name KEY3 KEY3

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON

+Info: Analyzing Slow 1100mV 85C Model

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -0.082

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.082              -0.115 KEY3 

+Info (332146): Worst-case hold slack is 0.347

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.347               0.000 KEY3 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.394

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.394              -5.179 KEY3 

+Info: Analyzing Slow 1100mV 0C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -0.127

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.127              -0.175 KEY3 

+Info (332146): Worst-case hold slack is 0.326

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.326               0.000 KEY3 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.394

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.394              -5.505 KEY3 

+Info: Analyzing Fast 1100mV 85C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332146): Worst-case setup slack is 0.377

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.377               0.000 KEY3 

+Info (332146): Worst-case hold slack is 0.197

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.197               0.000 KEY3 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case minimum pulse width slack is -0.085

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.085              -0.831 KEY3 

+Info: Analyzing Fast 1100mV 0C Model

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332146): Worst-case setup slack is 0.402

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.402               0.000 KEY3 

+Info (332146): Worst-case hold slack is 0.178

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.178               0.000 KEY3 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case minimum pulse width slack is -0.085

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.085              -0.838 KEY3 

+Info (332102): Design is not fully constrained for setup requirements

+Info (332102): Design is not fully constrained for hold requirements

+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings

+    Info: Peak virtual memory: 1179 megabytes

+    Info: Processing ended: Tue Nov 22 12:51:09 2016

+    Info: Elapsed time: 00:00:04

+    Info: Total CPU time (on all processors): 00:00:04

+

+

diff --git a/part_2/ex7/output_files/ex7.sta.summary b/part_2/ex7/output_files/ex7.sta.summary
new file mode 100755
index 0000000..7be8f51
--- /dev/null
+++ b/part_2/ex7/output_files/ex7.sta.summary
@@ -0,0 +1,53 @@
+------------------------------------------------------------

+TimeQuest Timing Analyzer Summary

+------------------------------------------------------------

+

+Type  : Slow 1100mV 85C Model Setup 'KEY3'

+Slack : -0.082

+TNS   : -0.115

+

+Type  : Slow 1100mV 85C Model Hold 'KEY3'

+Slack : 0.347

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'KEY3'

+Slack : -0.394

+TNS   : -5.179

+

+Type  : Slow 1100mV 0C Model Setup 'KEY3'

+Slack : -0.127

+TNS   : -0.175

+

+Type  : Slow 1100mV 0C Model Hold 'KEY3'

+Slack : 0.326

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'KEY3'

+Slack : -0.394

+TNS   : -5.505

+

+Type  : Fast 1100mV 85C Model Setup 'KEY3'

+Slack : 0.377

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Hold 'KEY3'

+Slack : 0.197

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'KEY3'

+Slack : -0.085

+TNS   : -0.831

+

+Type  : Fast 1100mV 0C Model Setup 'KEY3'

+Slack : 0.402

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Hold 'KEY3'

+Slack : 0.178

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'KEY3'

+Slack : -0.085

+TNS   : -0.838

+

+------------------------------------------------------------

diff --git a/part_2/ex7/verilog_files/LFSR.v b/part_2/ex7/verilog_files/LFSR.v
new file mode 100755
index 0000000..89ec82a
--- /dev/null
+++ b/part_2/ex7/verilog_files/LFSR.v
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);

+	input CLK;

+	output[7:1] COUNT;

+	reg[7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex7/verilog_files/LFSR.v.bak b/part_2/ex7/verilog_files/LFSR.v.bak
new file mode 100755
index 0000000..ae430a8
--- /dev/null
+++ b/part_2/ex7/verilog_files/LFSR.v.bak
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);

+	input CLK;

+	output[7:0] COUNT;

+	reg[7:0] COUNT;

+	initial COUNT = 7'b1;

+		

+	always @ (posedge CLK)

+		COUNT <= {COUNT[6:0], COUNT[7] ^ COUNT[1]};

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex7/verilog_files/hex_to_7seg.v b/part_2/ex7/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/ex7/verilog_files/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/ex7/verilog_files/hex_to_7seg.v.bak b/part_2/ex7/verilog_files/hex_to_7seg.v.bak
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/ex7/verilog_files/hex_to_7seg.v.bak
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/ex8/c5_pin_model_dump.txt b/part_2/ex8/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_2/ex8/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2

+io_4iomodule_c5_index: 54gpio_index: 465

+io_4iomodule_c5_index: 33gpio_index: 6

+io_4iomodule_c5_index: 51gpio_index: 461

+io_4iomodule_c5_index: 27gpio_index: 10

+io_4iomodule_c5_index: 57gpio_index: 457

+io_4iomodule_c5_index: 34gpio_index: 14

+io_4iomodule_c5_index: 28gpio_index: 453

+io_4iomodule_c5_index: 26gpio_index: 19

+io_4iomodule_c5_index: 47gpio_index: 449

+io_4iomodule_c5_index: 29gpio_index: 22

+io_4iomodule_c5_index: 3gpio_index: 445

+io_4iomodule_c5_index: 16gpio_index: 27

+io_4iomodule_c5_index: 6gpio_index: 441

+io_4iomodule_c5_index: 50gpio_index: 30

+io_4iomodule_c5_index: 35gpio_index: 437

+io_4iomodule_c5_index: 7gpio_index: 35

+io_4iomodule_c5_index: 53gpio_index: 433

+io_4iomodule_c5_index: 12gpio_index: 38

+io_4iomodule_c5_index: 1gpio_index: 429

+io_4iomodule_c5_index: 22gpio_index: 43

+io_4iomodule_c5_index: 8gpio_index: 425

+io_4iomodule_c5_index: 20gpio_index: 46

+io_4iomodule_c5_index: 30gpio_index: 421

+io_4iomodule_c5_index: 2gpio_index: 51

+io_4iomodule_c5_index: 31gpio_index: 417

+io_4iomodule_c5_index: 39gpio_index: 54

+io_4iomodule_c5_index: 18gpio_index: 413

+io_4iomodule_c5_index: 10gpio_index: 59

+io_4iomodule_c5_index: 42gpio_index: 409

+io_4iomodule_c5_index: 5gpio_index: 62

+io_4iomodule_c5_index: 24gpio_index: 405

+io_4iomodule_c5_index: 37gpio_index: 67

+io_4iomodule_c5_index: 13gpio_index: 401

+io_4iomodule_c5_index: 0gpio_index: 70

+io_4iomodule_c5_index: 44gpio_index: 397

+io_4iomodule_c5_index: 38gpio_index: 75

+io_4iomodule_c5_index: 52gpio_index: 393

+io_4iomodule_c5_index: 32gpio_index: 78

+io_4iomodule_c5_index: 56gpio_index: 389

+io_4iomodule_a_index: 13gpio_index: 385

+io_4iomodule_c5_index: 4gpio_index: 83

+io_4iomodule_c5_index: 23gpio_index: 86

+io_4iomodule_a_index: 15gpio_index: 381

+io_4iomodule_a_index: 8gpio_index: 377

+io_4iomodule_c5_index: 46gpio_index: 91

+io_4iomodule_a_index: 5gpio_index: 373

+io_4iomodule_a_index: 11gpio_index: 369

+io_4iomodule_c5_index: 41gpio_index: 94

+io_4iomodule_a_index: 3gpio_index: 365

+io_4iomodule_c5_index: 25gpio_index: 99

+io_4iomodule_a_index: 7gpio_index: 361

+io_4iomodule_c5_index: 9gpio_index: 102

+io_4iomodule_a_index: 0gpio_index: 357

+io_4iomodule_c5_index: 14gpio_index: 107

+io_4iomodule_a_index: 12gpio_index: 353

+io_4iomodule_c5_index: 45gpio_index: 110

+io_4iomodule_c5_index: 17gpio_index: 115

+io_4iomodule_a_index: 4gpio_index: 349

+io_4iomodule_c5_index: 36gpio_index: 118

+io_4iomodule_a_index: 10gpio_index: 345

+io_4iomodule_a_index: 16gpio_index: 341

+io_4iomodule_c5_index: 15gpio_index: 123

+io_4iomodule_a_index: 14gpio_index: 337

+io_4iomodule_c5_index: 43gpio_index: 126

+io_4iomodule_c5_index: 19gpio_index: 131

+io_4iomodule_a_index: 1gpio_index: 333

+io_4iomodule_c5_index: 59gpio_index: 134

+io_4iomodule_a_index: 2gpio_index: 329

+io_4iomodule_a_index: 9gpio_index: 325

+io_4iomodule_c5_index: 48gpio_index: 139

+io_4iomodule_a_index: 6gpio_index: 321

+io_4iomodule_a_index: 17gpio_index: 317

+io_4iomodule_c5_index: 40gpio_index: 142

+io_4iomodule_c5_index: 11gpio_index: 147

+io_4iomodule_c5_index: 58gpio_index: 150

+io_4iomodule_c5_index: 21gpio_index: 155

+io_4iomodule_c5_index: 49gpio_index: 158

+io_4iomodule_h_c5_index: 0gpio_index: 161

+io_4iomodule_h_c5_index: 6gpio_index: 165

+io_4iomodule_h_c5_index: 10gpio_index: 169

+io_4iomodule_h_c5_index: 3gpio_index: 173

+io_4iomodule_h_c5_index: 8gpio_index: 176

+io_4iomodule_h_c5_index: 11gpio_index: 180

+io_4iomodule_h_c5_index: 7gpio_index: 184

+io_4iomodule_h_c5_index: 5gpio_index: 188

+io_4iomodule_h_c5_index: 1gpio_index: 192

+io_4iomodule_h_c5_index: 2gpio_index: 196

+io_4iomodule_h_c5_index: 9gpio_index: 200

+io_4iomodule_h_c5_index: 4gpio_index: 204

+io_4iomodule_h_index: 15gpio_index: 208

+io_4iomodule_h_index: 1gpio_index: 212

+io_4iomodule_h_index: 3gpio_index: 216

+io_4iomodule_h_index: 2gpio_index: 220

+io_4iomodule_h_index: 11gpio_index: 224

+io_4iomodule_vref_h_index: 1gpio_index: 228

+io_4iomodule_h_index: 20gpio_index: 231

+io_4iomodule_h_index: 8gpio_index: 235

+io_4iomodule_h_index: 6gpio_index: 239

+io_4iomodule_h_index: 10gpio_index: 243

+io_4iomodule_h_index: 23gpio_index: 247

+io_4iomodule_h_index: 7gpio_index: 251

+io_4iomodule_h_index: 22gpio_index: 255

+io_4iomodule_h_index: 5gpio_index: 259

+io_4iomodule_h_index: 24gpio_index: 263

+io_4iomodule_h_index: 0gpio_index: 267

+io_4iomodule_h_index: 13gpio_index: 271

+io_4iomodule_h_index: 21gpio_index: 275

+io_4iomodule_h_index: 16gpio_index: 279

+io_4iomodule_vref_h_index: 0gpio_index: 283

+io_4iomodule_h_index: 12gpio_index: 286

+io_4iomodule_h_index: 4gpio_index: 290

+io_4iomodule_h_index: 19gpio_index: 294

+io_4iomodule_h_index: 18gpio_index: 298

+io_4iomodule_h_index: 17gpio_index: 302

+io_4iomodule_h_index: 25gpio_index: 306

+io_4iomodule_h_index: 14gpio_index: 310

+io_4iomodule_h_index: 9gpio_index: 314

diff --git a/part_2/ex8/db/.cmp.kpt b/part_2/ex8/db/.cmp.kpt
new file mode 100755
index 0000000..113b18d
--- /dev/null
+++ b/part_2/ex8/db/.cmp.kpt
diff --git a/part_2/ex8/db/ex8.(0).cnf.cdb b/part_2/ex8/db/ex8.(0).cnf.cdb
new file mode 100755
index 0000000..5cdd1d4
--- /dev/null
+++ b/part_2/ex8/db/ex8.(0).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(0).cnf.hdb b/part_2/ex8/db/ex8.(0).cnf.hdb
new file mode 100755
index 0000000..4517872
--- /dev/null
+++ b/part_2/ex8/db/ex8.(0).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(1).cnf.cdb b/part_2/ex8/db/ex8.(1).cnf.cdb
new file mode 100755
index 0000000..4aa533b
--- /dev/null
+++ b/part_2/ex8/db/ex8.(1).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(1).cnf.hdb b/part_2/ex8/db/ex8.(1).cnf.hdb
new file mode 100755
index 0000000..592417b
--- /dev/null
+++ b/part_2/ex8/db/ex8.(1).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(2).cnf.cdb b/part_2/ex8/db/ex8.(2).cnf.cdb
new file mode 100755
index 0000000..fa21ea0
--- /dev/null
+++ b/part_2/ex8/db/ex8.(2).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(2).cnf.hdb b/part_2/ex8/db/ex8.(2).cnf.hdb
new file mode 100755
index 0000000..9b7ef11
--- /dev/null
+++ b/part_2/ex8/db/ex8.(2).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(3).cnf.cdb b/part_2/ex8/db/ex8.(3).cnf.cdb
new file mode 100755
index 0000000..4ac3994
--- /dev/null
+++ b/part_2/ex8/db/ex8.(3).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(3).cnf.hdb b/part_2/ex8/db/ex8.(3).cnf.hdb
new file mode 100755
index 0000000..b5a6f32
--- /dev/null
+++ b/part_2/ex8/db/ex8.(3).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(4).cnf.cdb b/part_2/ex8/db/ex8.(4).cnf.cdb
new file mode 100755
index 0000000..e6a0005
--- /dev/null
+++ b/part_2/ex8/db/ex8.(4).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(4).cnf.hdb b/part_2/ex8/db/ex8.(4).cnf.hdb
new file mode 100755
index 0000000..1aa2860
--- /dev/null
+++ b/part_2/ex8/db/ex8.(4).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(5).cnf.cdb b/part_2/ex8/db/ex8.(5).cnf.cdb
new file mode 100755
index 0000000..e02c97b
--- /dev/null
+++ b/part_2/ex8/db/ex8.(5).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(5).cnf.hdb b/part_2/ex8/db/ex8.(5).cnf.hdb
new file mode 100755
index 0000000..92790f4
--- /dev/null
+++ b/part_2/ex8/db/ex8.(5).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(6).cnf.cdb b/part_2/ex8/db/ex8.(6).cnf.cdb
new file mode 100755
index 0000000..2ef9091
--- /dev/null
+++ b/part_2/ex8/db/ex8.(6).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(6).cnf.hdb b/part_2/ex8/db/ex8.(6).cnf.hdb
new file mode 100755
index 0000000..af5dcd5
--- /dev/null
+++ b/part_2/ex8/db/ex8.(6).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(7).cnf.cdb b/part_2/ex8/db/ex8.(7).cnf.cdb
new file mode 100755
index 0000000..280aa80
--- /dev/null
+++ b/part_2/ex8/db/ex8.(7).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(7).cnf.hdb b/part_2/ex8/db/ex8.(7).cnf.hdb
new file mode 100755
index 0000000..42ab8b5
--- /dev/null
+++ b/part_2/ex8/db/ex8.(7).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(8).cnf.cdb b/part_2/ex8/db/ex8.(8).cnf.cdb
new file mode 100755
index 0000000..75ea495
--- /dev/null
+++ b/part_2/ex8/db/ex8.(8).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(8).cnf.hdb b/part_2/ex8/db/ex8.(8).cnf.hdb
new file mode 100755
index 0000000..1df751e
--- /dev/null
+++ b/part_2/ex8/db/ex8.(8).cnf.hdb
diff --git a/part_2/ex8/db/ex8.ae.hdb b/part_2/ex8/db/ex8.ae.hdb
new file mode 100755
index 0000000..58cff3f
--- /dev/null
+++ b/part_2/ex8/db/ex8.ae.hdb
diff --git a/part_2/ex8/db/ex8.analyze_file.qmsg b/part_2/ex8/db/ex8.analyze_file.qmsg
new file mode 100755
index 0000000..34ad0f8
--- /dev/null
+++ b/part_2/ex8/db/ex8.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479898397112 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 23 10:53:16 2016 " "Processing started: Wed Nov 23 10:53:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479898397114 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479898397537 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479898397537 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "827 " "Peak virtual memory: 827 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 10:53:26 2016 " "Processing ended: Wed Nov 23 10:53:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479898406239 ""}

diff --git a/part_2/ex8/db/ex8.asm.qmsg b/part_2/ex8/db/ex8.asm.qmsg
new file mode 100755
index 0000000..ef22aca
--- /dev/null
+++ b/part_2/ex8/db/ex8.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069275578 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069275579 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:21:15 2016 " "Processing started: Fri Nov 25 10:21:15 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069275579 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480069275579 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480069275579 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480069276308 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480069280806 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "891 " "Peak virtual memory: 891 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069281145 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:21:21 2016 " "Processing ended: Fri Nov 25 10:21:21 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069281145 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069281145 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069281145 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480069281145 ""}

diff --git a/part_2/ex8/db/ex8.asm.rdb b/part_2/ex8/db/ex8.asm.rdb
new file mode 100755
index 0000000..dfb3a37
--- /dev/null
+++ b/part_2/ex8/db/ex8.asm.rdb
diff --git a/part_2/ex8/db/ex8.cbx.xml b/part_2/ex8/db/ex8.cbx.xml
new file mode 100755
index 0000000..721f2cf
--- /dev/null
+++ b/part_2/ex8/db/ex8.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex8">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex8/db/ex8.cmp.ammdb b/part_2/ex8/db/ex8.cmp.ammdb
new file mode 100755
index 0000000..69804ca
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.ammdb
diff --git a/part_2/ex8/db/ex8.cmp.bpm b/part_2/ex8/db/ex8.cmp.bpm
new file mode 100755
index 0000000..c507a35
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.bpm
diff --git a/part_2/ex8/db/ex8.cmp.cdb b/part_2/ex8/db/ex8.cmp.cdb
new file mode 100755
index 0000000..02cc71a
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.cdb
diff --git a/part_2/ex8/db/ex8.cmp.hdb b/part_2/ex8/db/ex8.cmp.hdb
new file mode 100755
index 0000000..668f70d
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.hdb
diff --git a/part_2/ex8/db/ex8.cmp.idb b/part_2/ex8/db/ex8.cmp.idb
new file mode 100755
index 0000000..197cc17
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.idb
diff --git a/part_2/ex8/db/ex8.cmp.logdb b/part_2/ex8/db/ex8.cmp.logdb
new file mode 100755
index 0000000..b69cd55
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.logdb
@@ -0,0 +1,75 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,36;0;36;0;0;36;36;0;36;36;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,0;36;0;36;36;0;0;36;0;0;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex8/db/ex8.cmp.rdb b/part_2/ex8/db/ex8.cmp.rdb
new file mode 100755
index 0000000..e73dbf7
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.rdb
diff --git a/part_2/ex8/db/ex8.cmp_merge.kpt b/part_2/ex8/db/ex8.cmp_merge.kpt
new file mode 100755
index 0000000..214a1dd
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp_merge.kpt
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..da61997
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..acc52a8
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex8/db/ex8.db_info b/part_2/ex8/db/ex8.db_info
new file mode 100755
index 0000000..1c55704
--- /dev/null
+++ b/part_2/ex8/db/ex8.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Fri Nov 25 09:03:31 2016

diff --git a/part_2/ex8/db/ex8.fit.qmsg b/part_2/ex8/db/ex8.fit.qmsg
new file mode 100755
index 0000000..5eedf90
--- /dev/null
+++ b/part_2/ex8/db/ex8.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480069241195 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480069241195 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480069241428 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069241476 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069241476 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480069241861 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480069241993 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480069252081 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 28 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480069252159 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480069252159 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069252160 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480069252162 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069252163 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069252164 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480069252164 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480069252164 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480069252165 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480069252738 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480069252739 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480069252739 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480069252742 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480069252742 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480069252743 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480069252745 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480069252746 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480069252746 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480069252779 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069252781 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480069257842 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480069258034 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069258608 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480069259183 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480069260053 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069260053 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480069261137 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X67_Y0 X77_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10"} { { 12 { 0 ""} 67 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480069265623 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480069265623 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480069269026 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480069269026 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069269030 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.42 " "Total time spent on timing analysis during the Fitter is 0.42 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480069270334 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069270372 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069270735 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069270736 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069271090 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069273487 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480069273723 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480069273779 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 51 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 51 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2595 " "Peak virtual memory: 2595 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069274198 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:21:14 2016 " "Processing ended: Fri Nov 25 10:21:14 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069274198 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069274198 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:58 " "Total CPU time (on all processors): 00:00:58" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069274198 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480069274198 ""}

diff --git a/part_2/ex8/db/ex8.hier_info b/part_2/ex8/db/ex8.hier_info
new file mode 100755
index 0000000..70306ab
--- /dev/null
+++ b/part_2/ex8/db/ex8.hier_info
@@ -0,0 +1,669 @@
+|ex8

+CLOCK_50 => CLOCK_50.IN2

+KEY[0] => ~NO_FANOUT~

+KEY[1] => ~NO_FANOUT~

+KEY[2] => ~NO_FANOUT~

+KEY[3] => _.IN1

+HEX0[0] <= hex_to_7seg:SEG0.port0

+HEX0[1] <= hex_to_7seg:SEG0.port0

+HEX0[2] <= hex_to_7seg:SEG0.port0

+HEX0[3] <= hex_to_7seg:SEG0.port0

+HEX0[4] <= hex_to_7seg:SEG0.port0

+HEX0[5] <= hex_to_7seg:SEG0.port0

+HEX0[6] <= hex_to_7seg:SEG0.port0

+HEX1[0] <= hex_to_7seg:SEG1.port0

+HEX1[1] <= hex_to_7seg:SEG1.port0

+HEX1[2] <= hex_to_7seg:SEG1.port0

+HEX1[3] <= hex_to_7seg:SEG1.port0

+HEX1[4] <= hex_to_7seg:SEG1.port0

+HEX1[5] <= hex_to_7seg:SEG1.port0

+HEX1[6] <= hex_to_7seg:SEG1.port0

+HEX2[0] <= hex_to_7seg:SEG2.port0

+HEX2[1] <= hex_to_7seg:SEG2.port0

+HEX2[2] <= hex_to_7seg:SEG2.port0

+HEX2[3] <= hex_to_7seg:SEG2.port0

+HEX2[4] <= hex_to_7seg:SEG2.port0

+HEX2[5] <= hex_to_7seg:SEG2.port0

+HEX2[6] <= hex_to_7seg:SEG2.port0

+LEDR[0] <= formula_fsm:FSM.port6

+LEDR[1] <= formula_fsm:FSM.port6

+LEDR[2] <= formula_fsm:FSM.port6

+LEDR[3] <= formula_fsm:FSM.port6

+LEDR[4] <= formula_fsm:FSM.port6

+LEDR[5] <= formula_fsm:FSM.port6

+LEDR[6] <= formula_fsm:FSM.port6

+LEDR[7] <= formula_fsm:FSM.port6

+LEDR[8] <= formula_fsm:FSM.port6

+LEDR[9] <= formula_fsm:FSM.port6

+

+

+|ex8|tick_50000:TICK0

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => count[12].CLK

+CLOCK_IN => count[13].CLK

+CLOCK_IN => count[14].CLK

+CLOCK_IN => count[15].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|tick_2500:TICK1

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+en => CLK_OUT.OUTPUTSELECT

+en => count[0].ENA

+en => count[1].ENA

+en => count[2].ENA

+en => count[3].ENA

+en => count[4].ENA

+en => count[5].ENA

+en => count[6].ENA

+en => count[7].ENA

+en => count[8].ENA

+en => count[9].ENA

+en => count[10].ENA

+en => count[11].ENA

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|formula_fsm:FSM

+clk => state~3.DATAIN

+tick => ledr[0]~reg0.CLK

+tick => ledr[1]~reg0.CLK

+tick => ledr[2]~reg0.CLK

+tick => ledr[3]~reg0.CLK

+tick => ledr[4]~reg0.CLK

+tick => ledr[5]~reg0.CLK

+tick => ledr[6]~reg0.CLK

+tick => ledr[7]~reg0.CLK

+tick => ledr[8]~reg0.CLK

+tick => ledr[9]~reg0.CLK

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE

+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE

+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|LFSR:LFSR0

+CLK => COUNT[1]~reg0.CLK

+CLK => COUNT[2]~reg0.CLK

+CLK => COUNT[3]~reg0.CLK

+CLK => COUNT[4]~reg0.CLK

+CLK => COUNT[5]~reg0.CLK

+CLK => COUNT[6]~reg0.CLK

+CLK => COUNT[7]~reg0.CLK

+en => COUNT[1]~reg0.ENA

+en => COUNT[2]~reg0.ENA

+en => COUNT[3]~reg0.ENA

+en => COUNT[4]~reg0.ENA

+en => COUNT[5]~reg0.ENA

+en => COUNT[6]~reg0.ENA

+en => COUNT[7]~reg0.ENA

+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|delay:DEL0

+clk => count[0].CLK

+clk => count[1].CLK

+clk => count[2].CLK

+clk => count[3].CLK

+clk => count[4].CLK

+clk => count[5].CLK

+clk => count[6].CLK

+clk => count[7].CLK

+clk => count[8].CLK

+clk => count[9].CLK

+clk => count[10].CLK

+clk => count[11].CLK

+clk => count[12].CLK

+clk => count[13].CLK

+clk => state~4.DATAIN

+N[0] => count.DATAB

+N[1] => count.DATAB

+N[2] => count.DATAB

+N[3] => count.DATAB

+N[4] => count.DATAB

+N[5] => count.DATAB

+N[6] => count.DATAB

+N[7] => ~NO_FANOUT~

+N[8] => ~NO_FANOUT~

+N[9] => ~NO_FANOUT~

+N[10] => ~NO_FANOUT~

+N[11] => ~NO_FANOUT~

+N[12] => ~NO_FANOUT~

+N[13] => ~NO_FANOUT~

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector17.IN3

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector14.IN2

+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD

+B[0] => BCD_0[0].DATAIN

+B[1] => w35[0].IN1

+B[2] => w30[0].IN1

+B[3] => w26[0].IN1

+B[4] => w22[0].IN1

+B[5] => w18[0].IN1

+B[6] => w15[0].IN1

+B[7] => w12[0].IN1

+B[8] => w9[0].IN1

+B[9] => w7[0].IN1

+B[10] => w5[0].IN1

+B[11] => w3[0].IN1

+B[12] => w2[0].IN1

+B[13] => w1[0].IN1

+B[14] => w1[1].IN1

+B[15] => w1[2].IN1

+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE

+BCD_0[1] <= add3_ge5:A35.port1

+BCD_0[2] <= add3_ge5:A35.port1

+BCD_0[3] <= add3_ge5:A35.port1

+BCD_1[0] <= add3_ge5:A35.port1

+BCD_1[1] <= add3_ge5:A34.port1

+BCD_1[2] <= add3_ge5:A34.port1

+BCD_1[3] <= add3_ge5:A34.port1

+BCD_2[0] <= add3_ge5:A34.port1

+BCD_2[1] <= add3_ge5:A33.port1

+BCD_2[2] <= add3_ge5:A33.port1

+BCD_2[3] <= add3_ge5:A33.port1

+BCD_3[0] <= add3_ge5:A33.port1

+BCD_3[1] <= add3_ge5:A32.port1

+BCD_3[2] <= add3_ge5:A32.port1

+BCD_3[3] <= add3_ge5:A32.port1

+BCD_4[0] <= add3_ge5:A32.port1

+BCD_4[1] <= add3_ge5:A31.port1

+BCD_4[2] <= add3_ge5:A31.port1

+BCD_4[3] <= add3_ge5:A31.port1

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A1

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A2

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A3

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A4

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A5

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A6

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A7

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A8

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A9

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A10

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A11

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A12

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A13

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A14

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A15

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A16

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A17

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A18

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A19

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A20

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A21

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A22

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A23

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A24

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A25

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A26

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A27

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A28

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A29

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A30

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A31

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A32

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A33

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A34

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A35

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|hex_to_7seg:SEG0

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex8|hex_to_7seg:SEG1

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex8|hex_to_7seg:SEG2

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

diff --git a/part_2/ex8/db/ex8.hif b/part_2/ex8/db/ex8.hif
new file mode 100755
index 0000000..81f8f61
--- /dev/null
+++ b/part_2/ex8/db/ex8.hif
diff --git a/part_2/ex8/db/ex8.lpc.html b/part_2/ex8/db/ex8.lpc.html
new file mode 100755
index 0000000..b0b17d7
--- /dev/null
+++ b/part_2/ex8/db/ex8.lpc.html
@@ -0,0 +1,722 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+<TR >

+<TD >SEG2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG1</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A35</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A34</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A33</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A32</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A31</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A30</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A29</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A28</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A27</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A26</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A25</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A24</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A23</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A22</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A21</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A20</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A19</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A18</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A17</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A16</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A15</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A14</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A13</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A12</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A11</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A10</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A9</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A8</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A7</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A6</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A5</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A4</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A3</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD</TD>

+<TD >16</TD>

+<TD >9</TD>

+<TD >0</TD>

+<TD >9</TD>

+<TD >20</TD>

+<TD >9</TD>

+<TD >9</TD>

+<TD >9</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >DEL0</TD>

+<TD >16</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >1</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >LFSR0</TD>

+<TD >2</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >FSM</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >12</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >TICK1</TD>

+<TD >2</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >TICK0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+</TABLE>

diff --git a/part_2/ex8/db/ex8.lpc.rdb b/part_2/ex8/db/ex8.lpc.rdb
new file mode 100755
index 0000000..f107311
--- /dev/null
+++ b/part_2/ex8/db/ex8.lpc.rdb
diff --git a/part_2/ex8/db/ex8.lpc.txt b/part_2/ex8/db/ex8.lpc.txt
new file mode 100755
index 0000000..5e9734c
--- /dev/null
+++ b/part_2/ex8/db/ex8.lpc.txt
@@ -0,0 +1,50 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD       ; 16    ; 9              ; 0            ; 9              ; 20     ; 9               ; 9             ; 9               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; FSM       ; 4     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; TICK1     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex8/db/ex8.map.ammdb b/part_2/ex8/db/ex8.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.ammdb
diff --git a/part_2/ex8/db/ex8.map.bpm b/part_2/ex8/db/ex8.map.bpm
new file mode 100755
index 0000000..e407061
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.bpm
diff --git a/part_2/ex8/db/ex8.map.cdb b/part_2/ex8/db/ex8.map.cdb
new file mode 100755
index 0000000..e054ff8
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.cdb
diff --git a/part_2/ex8/db/ex8.map.hdb b/part_2/ex8/db/ex8.map.hdb
new file mode 100755
index 0000000..4070275
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.hdb
diff --git a/part_2/ex8/db/ex8.map.kpt b/part_2/ex8/db/ex8.map.kpt
new file mode 100755
index 0000000..97786a3
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.kpt
diff --git a/part_2/ex8/db/ex8.map.logdb b/part_2/ex8/db/ex8.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex8/db/ex8.map.qmsg b/part_2/ex8/db/ex8.map.qmsg
new file mode 100755
index 0000000..c26ecb2
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.qmsg
@@ -0,0 +1,74 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069229728 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069229730 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:20:29 2016 " "Processing started: Fri Nov 25 10:20:29 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069229730 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069229730 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069229730 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480069230202 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480069230202 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238583 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238583 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238585 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238585 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238586 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238586 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238588 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238588 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238589 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238591 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238592 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238592 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480069238594 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238594 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238594 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238595 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238595 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238595 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238597 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238597 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238600 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238600 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480069238629 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex8.v" "TICK0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238635 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" {  } { { "verilog_files/ex8.v" "TICK1" { Text "C:/New folder/ex8/verilog_files/ex8.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238636 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex8.v" "FSM" { Text "C:/New folder/ex8/verilog_files/ex8.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238637 ""}

+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(37) " "Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 37 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 "|ex8|formula_fsm:comb_5"}

+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(47) " "Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 "|ex8|formula_fsm:comb_5"}

+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(47) " "Inferred latch for \"start_delay\" at formula_fsm.v(47)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 "|ex8|formula_fsm:comb_5"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex8.v" "LFSR0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex8.v" "DEL0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238639 ""}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480069238639 "|ex8|delay:comb_8"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex8.v" "BCD" { Text "C:/New folder/ex8/verilog_files/ex8.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238640 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238641 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex8.v" "SEG0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238646 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480069239089 ""}

+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069239127 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069239127 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069239127 "|ex8|HEX2[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480069239127 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480069239203 ""}

+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480069239399 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069239421 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480069239504 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069239504 ""}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069239539 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069239539 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069239539 "|ex8|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480069239539 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "183 " "Implemented 183 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480069239540 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480069239540 ""} { "Info" "ICUT_CUT_TM_LCELLS" "147 " "Implemented 147 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480069239540 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480069239540 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "916 " "Peak virtual memory: 916 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069239553 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:20:39 2016 " "Processing ended: Fri Nov 25 10:20:39 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069239553 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069239553 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069239553 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069239553 ""}

diff --git a/part_2/ex8/db/ex8.map.rdb b/part_2/ex8/db/ex8.map.rdb
new file mode 100755
index 0000000..44ea2dd
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.rdb
diff --git a/part_2/ex8/db/ex8.map_bb.cdb b/part_2/ex8/db/ex8.map_bb.cdb
new file mode 100755
index 0000000..652b850
--- /dev/null
+++ b/part_2/ex8/db/ex8.map_bb.cdb
diff --git a/part_2/ex8/db/ex8.map_bb.hdb b/part_2/ex8/db/ex8.map_bb.hdb
new file mode 100755
index 0000000..d485d10
--- /dev/null
+++ b/part_2/ex8/db/ex8.map_bb.hdb
diff --git a/part_2/ex8/db/ex8.map_bb.logdb b/part_2/ex8/db/ex8.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex8/db/ex8.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex8/db/ex8.pre_map.cdb b/part_2/ex8/db/ex8.pre_map.cdb
new file mode 100755
index 0000000..7e3e287
--- /dev/null
+++ b/part_2/ex8/db/ex8.pre_map.cdb
diff --git a/part_2/ex8/db/ex8.pre_map.hdb b/part_2/ex8/db/ex8.pre_map.hdb
new file mode 100755
index 0000000..b23e67a
--- /dev/null
+++ b/part_2/ex8/db/ex8.pre_map.hdb
diff --git a/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..f01a94f
--- /dev/null
+++ b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
diff --git a/part_2/ex8/db/ex8.routing.rdb b/part_2/ex8/db/ex8.routing.rdb
new file mode 100755
index 0000000..99de65e
--- /dev/null
+++ b/part_2/ex8/db/ex8.routing.rdb
diff --git a/part_2/ex8/db/ex8.rtlv.hdb b/part_2/ex8/db/ex8.rtlv.hdb
new file mode 100755
index 0000000..a81a06a
--- /dev/null
+++ b/part_2/ex8/db/ex8.rtlv.hdb
diff --git a/part_2/ex8/db/ex8.rtlv_sg.cdb b/part_2/ex8/db/ex8.rtlv_sg.cdb
new file mode 100755
index 0000000..74a197d
--- /dev/null
+++ b/part_2/ex8/db/ex8.rtlv_sg.cdb
diff --git a/part_2/ex8/db/ex8.rtlv_sg_swap.cdb b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..54c6f7c
--- /dev/null
+++ b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
diff --git a/part_2/ex8/db/ex8.sld_design_entry.sci b/part_2/ex8/db/ex8.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex8/db/ex8.sld_design_entry.sci
diff --git a/part_2/ex8/db/ex8.sld_design_entry_dsc.sci b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
diff --git a/part_2/ex8/db/ex8.smart_action.txt b/part_2/ex8/db/ex8.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex8/db/ex8.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex8/db/ex8.smp_dump.txt b/part_2/ex8/db/ex8.smp_dump.txt
new file mode 100755
index 0000000..04f2111
--- /dev/null
+++ b/part_2/ex8/db/ex8.smp_dump.txt
@@ -0,0 +1,13 @@
+

+State Machine - |ex8|delay:DEL0|state

+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 

+state.IDLE 0 0 0 0 

+state.COUNTING 0 0 1 1 

+state.TIME_OUT 0 1 0 1 

+state.WAIT_LOW 1 0 0 1 

+

+State Machine - |ex8|formula_fsm:FSM|state

+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 

+state.WAIT_TRIGGER 0 0 0 

+state.LIGHT_UP_LEDS 1 0 1 

+state.WAIT_FOR_TIMEOUT 1 1 0 

diff --git a/part_2/ex8/db/ex8.sta.qmsg b/part_2/ex8/db/ex8.sta.qmsg
new file mode 100755
index 0000000..69fb7fe
--- /dev/null
+++ b/part_2/ex8/db/ex8.sta.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069282649 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069282650 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:21:22 2016 " "Processing started: Fri Nov 25 10:21:22 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069282650 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069282650 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069282650 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069282780 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283327 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283327 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283377 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283377 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283871 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283890 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283890 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT " "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283891 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283893 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283898 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069283899 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069283906 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069283924 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283924 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.828 " "Worst-case setup slack is -4.828" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.828             -90.826 CLOCK_50  " "   -4.828             -90.826 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.650             -63.464 tick_50000:TICK0\|CLK_OUT  " "   -2.650             -63.464 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.004             -18.612 tick_2500:TICK1\|CLK_OUT  " "   -2.004             -18.612 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.489              -1.489 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.489              -1.489 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283926 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.283 " "Worst-case hold slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.283               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.283               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.376               0.000 CLOCK_50  " "    0.376               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.424               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.424               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.523               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.523               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283929 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283931 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283933 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.636 " "Worst-case minimum pulse width slack is -0.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.636             -25.765 CLOCK_50  " "   -0.636             -25.765 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -14.976 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -14.976 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.130 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.130 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.404               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.404               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283934 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069283945 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283979 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284794 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284844 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069284850 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284850 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.731 " "Worst-case setup slack is -4.731" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.731             -86.467 CLOCK_50  " "   -4.731             -86.467 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.603             -61.065 tick_50000:TICK0\|CLK_OUT  " "   -2.603             -61.065 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.916             -17.960 tick_2500:TICK1\|CLK_OUT  " "   -1.916             -17.960 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.373              -1.373 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.373              -1.373 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284851 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.283 " "Worst-case hold slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.283               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.283               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.287               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.287               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.389               0.000 CLOCK_50  " "    0.389               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.530               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.530               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284854 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284856 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284857 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.690 " "Worst-case minimum pulse width slack is -0.690" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.690             -23.719 CLOCK_50  " "   -0.690             -23.719 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -14.868 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -14.868 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.140 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.140 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.384               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.384               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284859 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069284870 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285012 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285704 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285750 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069285752 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285752 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.046 " "Worst-case setup slack is -4.046" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.046             -58.106 CLOCK_50  " "   -4.046             -58.106 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.373             -12.517 tick_2500:TICK1\|CLK_OUT  " "   -1.373             -12.517 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.359             -32.665 tick_50000:TICK0\|CLK_OUT  " "   -1.359             -32.665 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.480              -0.480 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.480              -0.480 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285754 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.023 " "Worst-case hold slack is 0.023" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.023               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.023               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.061               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.061               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.092               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.092               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.182               0.000 CLOCK_50  " "    0.182               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285757 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285759 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285761 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.760 " "Worst-case minimum pulse width slack is -0.760" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.760             -18.549 CLOCK_50  " "   -0.760             -18.549 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.049               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.049               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.131               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.131               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.469               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.469               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285762 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069285773 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285920 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069285922 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285922 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.445 " "Worst-case setup slack is -3.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.445             -47.547 CLOCK_50  " "   -3.445             -47.547 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.171             -10.740 tick_2500:TICK1\|CLK_OUT  " "   -1.171             -10.740 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.164             -27.696 tick_50000:TICK0\|CLK_OUT  " "   -1.164             -27.696 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.362              -0.362 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.362              -0.362 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285924 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.013 " "Worst-case hold slack is 0.013" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.013               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.013               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.014               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.014               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.024               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172               0.000 CLOCK_50  " "    0.172               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285927 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285929 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285930 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.812 " "Worst-case minimum pulse width slack is -0.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.812             -22.016 CLOCK_50  " "   -0.812             -22.016 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.076               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.076               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.135               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.465               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.465               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285932 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069287278 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069287278 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1209 " "Peak virtual memory: 1209 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069287320 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:21:27 2016 " "Processing ended: Fri Nov 25 10:21:27 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069287320 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069287320 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069287320 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069287320 ""}

diff --git a/part_2/ex8/db/ex8.sta.rdb b/part_2/ex8/db/ex8.sta.rdb
new file mode 100755
index 0000000..18c12e2
--- /dev/null
+++ b/part_2/ex8/db/ex8.sta.rdb
diff --git a/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..cc7aaf1
--- /dev/null
+++ b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex8/db/ex8.tis_db_list.ddb b/part_2/ex8/db/ex8.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_2/ex8/db/ex8.tis_db_list.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..058f4f0
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..57389e8
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..cc60683
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..c35046f
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex8/db/ex8.tmw_info b/part_2/ex8/db/ex8.tmw_info
new file mode 100755
index 0000000..97862be
--- /dev/null
+++ b/part_2/ex8/db/ex8.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:01:00

+start_analysis_synthesis:s:00:00:12-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:00:34-start_full_compilation

+start_assembler:s:00:00:07-start_full_compilation

+start_timing_analyzer:s:00:00:07-start_full_compilation

diff --git a/part_2/ex8/db/ex8.vpr.ammdb b/part_2/ex8/db/ex8.vpr.ammdb
new file mode 100755
index 0000000..0f304da
--- /dev/null
+++ b/part_2/ex8/db/ex8.vpr.ammdb
diff --git a/part_2/ex8/db/ex8_partition_pins.json b/part_2/ex8/db/ex8_partition_pins.json
new file mode 100755
index 0000000..ad28bfb
--- /dev/null
+++ b/part_2/ex8/db/ex8_partition_pins.json
@@ -0,0 +1,129 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "HEX0[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[5]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[0]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[1]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[2]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[3]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[4]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[5]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[6]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[7]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[8]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[9]",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[3]",

+					"strict" : false

+				},

+				{

+					"name" : "CLOCK_50",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex8/db/prev_cmp_ex8.qmsg b/part_2/ex8/db/prev_cmp_ex8.qmsg
new file mode 100755
index 0000000..ddafb7b
--- /dev/null
+++ b/part_2/ex8/db/prev_cmp_ex8.qmsg
@@ -0,0 +1,195 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069024021 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069024023 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:03 2016 " "Processing started: Fri Nov 25 10:17:03 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069024023 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069024023 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069024023 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480069024479 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480069024480 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032679 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032679 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032681 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032681 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032682 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032682 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032684 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032684 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032687 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032688 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032688 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480069032691 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032692 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032692 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032693 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032693 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032693 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032695 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032695 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032696 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032696 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(13) " "Verilog HDL Instantiation warning at ex8.v(13): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 13 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032697 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(14) " "Verilog HDL Instantiation warning at ex8.v(14): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 14 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(15) " "Verilog HDL Instantiation warning at ex8.v(15): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 15 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(16) " "Verilog HDL Instantiation warning at ex8.v(16): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 16 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(17) " "Verilog HDL Instantiation warning at ex8.v(17): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 17 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(18) " "Verilog HDL Instantiation warning at ex8.v(18): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 18 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(19) " "Verilog HDL Instantiation warning at ex8.v(19): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 19 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(20) " "Verilog HDL Instantiation warning at ex8.v(20): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 20 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480069032724 ""}

+{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX2 ex8.v(6) " "Output port \"HEX2\" at ex8.v(6) has no driver" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1480069032725 "|ex8"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:comb_3 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:comb_3\"" {  } { { "verilog_files/ex8.v" "comb_3" { Text "C:/New folder/ex8/verilog_files/ex8.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032725 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:comb_4 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:comb_4\"" {  } { { "verilog_files/ex8.v" "comb_4" { Text "C:/New folder/ex8/verilog_files/ex8.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032726 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:comb_5 " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:comb_5\"" {  } { { "verilog_files/ex8.v" "comb_5" { Text "C:/New folder/ex8/verilog_files/ex8.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032727 ""}

+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(37) " "Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 37 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480069032728 "|ex8|formula_fsm:comb_5"}

+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(47) " "Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480069032728 "|ex8|formula_fsm:comb_5"}

+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(47) " "Inferred latch for \"start_delay\" at formula_fsm.v(47)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032728 "|ex8|formula_fsm:comb_5"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:comb_7 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:comb_7\"" {  } { { "verilog_files/ex8.v" "comb_7" { Text "C:/New folder/ex8/verilog_files/ex8.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032734 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:comb_8 " "Elaborating entity \"delay\" for hierarchy \"delay:comb_8\"" {  } { { "verilog_files/ex8.v" "comb_8" { Text "C:/New folder/ex8/verilog_files/ex8.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032735 ""}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480069032736 "|ex8|delay:comb_8"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:comb_9 " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:comb_9\"" {  } { { "verilog_files/ex8.v" "comb_9" { Text "C:/New folder/ex8/verilog_files/ex8.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032737 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:comb_9\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:comb_9\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032738 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:comb_10 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:comb_10\"" {  } { { "verilog_files/ex8.v" "comb_10" { Text "C:/New folder/ex8/verilog_files/ex8.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032743 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480069033183 ""}

+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[0\] GND " "Pin \"HEX2\[0\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[3\] GND " "Pin \"HEX2\[3\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[4\] GND " "Pin \"HEX2\[4\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[5\] GND " "Pin \"HEX2\[5\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] GND " "Pin \"HEX2\[6\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480069033220 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480069033295 ""}

+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480069033491 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069033516 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480069033599 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069033599 ""}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069033635 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069033635 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069033635 "|ex8|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480069033635 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "182 " "Implemented 182 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480069033636 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480069033636 ""} { "Info" "ICUT_CUT_TM_LCELLS" "146 " "Implemented 146 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480069033636 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480069033636 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "914 " "Peak virtual memory: 914 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069033648 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:17:13 2016 " "Processing ended: Fri Nov 25 10:17:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069033648 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069033648 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069033648 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069033648 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1480069035073 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069035074 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:14 2016 " "Processing started: Fri Nov 25 10:17:14 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069035074 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480069035074 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480069035074 ""}

+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480069035195 ""}

+{ "Info" "0" "" "Project  = ex8" {  } {  } 0 0 "Project  = ex8" 0 0 "Fitter" 0 0 1480069035195 ""}

+{ "Info" "0" "" "Revision = ex8" {  } {  } 0 0 "Revision = ex8" 0 0 "Fitter" 0 0 1480069035195 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480069035310 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480069035311 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480069035571 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069035633 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069035633 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480069036022 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480069036154 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480069046211 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 28 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480069046288 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480069046288 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069046288 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480069046291 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069046291 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069046292 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480069046292 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480069046293 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480069046293 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480069046865 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480069046866 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480069046866 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480069046869 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480069046869 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480069046870 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480069046872 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480069046873 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480069046873 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480069046907 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069046909 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480069051902 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480069052104 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069052666 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480069053236 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480069054137 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069054138 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480069055233 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480069059723 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480069059723 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480069063963 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480069063963 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069063968 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.43 " "Total time spent on timing analysis during the Fitter is 0.43 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480069065291 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069065331 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069065698 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069065698 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069066056 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069068455 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480069068691 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480069068745 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 51 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 51 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2630 " "Peak virtual memory: 2630 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069069180 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:17:49 2016 " "Processing ended: Fri Nov 25 10:17:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069069180 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:35 " "Elapsed time: 00:00:35" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069069180 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:58 " "Total CPU time (on all processors): 00:00:58" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069069180 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480069069180 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480069070489 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069070491 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:50 2016 " "Processing started: Fri Nov 25 10:17:50 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069070491 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480069070491 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480069070492 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480069071266 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480069075853 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "889 " "Peak virtual memory: 889 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069076193 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:17:56 2016 " "Processing ended: Fri Nov 25 10:17:56 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069076193 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069076193 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069076193 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480069076193 ""}

+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480069076843 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480069077652 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069077653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:57 2016 " "Processing started: Fri Nov 25 10:17:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069077653 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069077653 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069077653 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069077776 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078333 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078333 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078381 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078381 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078878 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078898 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078898 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:comb_3\|CLK_OUT tick_50000:comb_3\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:comb_3\|CLK_OUT tick_50000:comb_3\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_2500:comb_4\|CLK_OUT tick_2500:comb_4\|CLK_OUT " "create_clock -period 1.000 -name tick_2500:comb_4\|CLK_OUT tick_2500:comb_4\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:comb_5\|state.LIGHT_UP_LEDS formula_fsm:comb_5\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:comb_5\|state.LIGHT_UP_LEDS formula_fsm:comb_5\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078899 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078900 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078906 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069078906 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069078913 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069078929 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078929 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.713 " "Worst-case setup slack is -3.713" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.713             -89.478 CLOCK_50  " "   -3.713             -89.478 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.069             -68.001 tick_50000:comb_3\|CLK_OUT  " "   -3.069             -68.001 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.865             -17.220 tick_2500:comb_4\|CLK_OUT  " "   -1.865             -17.220 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.559              -1.559 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -1.559              -1.559 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078931 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.282 " "Worst-case hold slack is 0.282" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.282               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.282               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.376               0.000 CLOCK_50  " "    0.376               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.380               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.380               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.425               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.425               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078934 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078935 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078937 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.679 " "Worst-case minimum pulse width slack is -0.679" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.679             -25.746 CLOCK_50  " "   -0.679             -25.746 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -15.156 tick_50000:comb_3\|CLK_OUT  " "   -0.394             -15.156 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.330 tick_2500:comb_4\|CLK_OUT  " "   -0.394              -5.330 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.461               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.461               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078939 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069078950 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078985 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079799 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079849 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069079855 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079855 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.511 " "Worst-case setup slack is -3.511" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.511             -84.954 CLOCK_50  " "   -3.511             -84.954 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.976             -66.210 tick_50000:comb_3\|CLK_OUT  " "   -2.976             -66.210 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.912             -17.517 tick_2500:comb_4\|CLK_OUT  " "   -1.912             -17.517 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.528              -1.528 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -1.528              -1.528 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079857 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.265 " "Worst-case hold slack is 0.265" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.265               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.265               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.285               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.285               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.374               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.374               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.392               0.000 CLOCK_50  " "    0.392               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079859 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079861 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079862 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.722 " "Worst-case minimum pulse width slack is -0.722" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.722             -23.943 CLOCK_50  " "   -0.722             -23.943 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -14.998 tick_50000:comb_3\|CLK_OUT  " "   -0.394             -14.998 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.250 tick_2500:comb_4\|CLK_OUT  " "   -0.394              -5.250 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.444               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.444               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079864 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069079874 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080017 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080708 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080756 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069080758 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080758 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.058 " "Worst-case setup slack is -3.058" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.058             -53.489 CLOCK_50  " "   -3.058             -53.489 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.522             -33.572 tick_50000:comb_3\|CLK_OUT  " "   -1.522             -33.572 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.243             -11.298 tick_2500:comb_4\|CLK_OUT  " "   -1.243             -11.298 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.459              -0.459 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -0.459              -0.459 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080760 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.004 " "Worst-case hold slack is 0.004" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.004               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.004               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.023               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.023               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.095               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.095               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.182               0.000 CLOCK_50  " "    0.182               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080763 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080764 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080766 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.801 " "Worst-case minimum pulse width slack is -0.801" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.801             -18.381 CLOCK_50  " "   -0.801             -18.381 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.108               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.108               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.120               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.120               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.491               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.491               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080767 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069080778 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080927 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069080929 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080929 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.570 " "Worst-case setup slack is -2.570" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.570             -43.622 CLOCK_50  " "   -2.570             -43.622 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.344             -29.187 tick_50000:comb_3\|CLK_OUT  " "   -1.344             -29.187 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.091              -9.985 tick_2500:comb_4\|CLK_OUT  " "   -1.091              -9.985 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.376              -0.376 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -0.376              -0.376 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080931 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.039 " "Worst-case hold slack is -0.039" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.039              -0.039 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -0.039              -0.039 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.035              -0.155 tick_2500:comb_4\|CLK_OUT  " "   -0.035              -0.155 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.076               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.076               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.174               0.000 CLOCK_50  " "    0.174               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080934 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080936 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080938 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.840 " "Worst-case minimum pulse width slack is -0.840" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.840             -21.816 CLOCK_50  " "   -0.840             -21.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.123               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.123               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.135               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.485               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.485               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080939 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069082294 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069082295 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1210 " "Peak virtual memory: 1210 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069082337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:18:02 2016 " "Processing ended: Fri Nov 25 10:18:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069082337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069082337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069082337 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069082337 ""}

+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 84 s " "Quartus Prime Full Compilation was successful. 0 errors, 84 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069083091 ""}

diff --git a/part_2/ex8/ex8.qpf b/part_2/ex8/ex8.qpf
new file mode 100755
index 0000000..a8b23d4
--- /dev/null
+++ b/part_2/ex8/ex8.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 09:21:41  November 23, 2016

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "16.0"

+DATE = "09:21:41  November 23, 2016"

+

+# Revisions

+

+PROJECT_REVISION = "ex8"

diff --git a/part_2/ex8/ex8.qsf b/part_2/ex8/ex8.qsf
new file mode 100755
index 0000000..b806fc9
--- /dev/null
+++ b/part_2/ex8/ex8.qsf
@@ -0,0 +1,275 @@
+#============================================================

+# CLOCK

+#============================================================

+set_location_assignment PIN_AF14 -to CLOCK_50

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50

+

+#============================================================

+# Add-on Card Interface Pins

+#============================================================

+set_location_assignment PIN_AJ20 -to PWM_OUT

+set_location_assignment PIN_AK21 -to DAC_LD

+set_location_assignment PIN_AD20 -to DAC_CS

+set_location_assignment PIN_AF20 -to DAC_SCK

+set_location_assignment PIN_AF21 -to ADC_SCK

+set_location_assignment PIN_AG21 -to ADC_SDI

+set_location_assignment PIN_AG20 -to ADC_CS

+set_location_assignment PIN_AG18 -to DAC_SDI

+set_location_assignment PIN_AJ21 -to ADC_SDO

+set_location_assignment PIN_Y17 -to OLED_CS

+set_location_assignment PIN_Y18 -to OLED_RST

+set_location_assignment PIN_AK18 -to OLED_DC

+set_location_assignment PIN_AJ19 -to OLED_CLK

+set_location_assignment PIN_AJ16 -to OLED_DATA

+

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO

+

+

+#============================================================

+# HEX0

+#============================================================

+set_location_assignment PIN_AE26 -to HEX0[0]

+set_location_assignment PIN_AE27 -to HEX0[1]

+set_location_assignment PIN_AE28 -to HEX0[2]

+set_location_assignment PIN_AG27 -to HEX0[3]

+set_location_assignment PIN_AF28 -to HEX0[4]

+set_location_assignment PIN_AG28 -to HEX0[5]

+set_location_assignment PIN_AH28 -to HEX0[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]

+

+#============================================================

+# HEX1

+#============================================================

+set_location_assignment PIN_AJ29 -to HEX1[0]

+set_location_assignment PIN_AH29 -to HEX1[1]

+set_location_assignment PIN_AH30 -to HEX1[2]

+set_location_assignment PIN_AG30 -to HEX1[3]

+set_location_assignment PIN_AF29 -to HEX1[4]

+set_location_assignment PIN_AF30 -to HEX1[5]

+set_location_assignment PIN_AD27 -to HEX1[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]

+

+#============================================================

+# HEX2

+#============================================================

+set_location_assignment PIN_AB23 -to HEX2[0]

+set_location_assignment PIN_AE29 -to HEX2[1]

+set_location_assignment PIN_AD29 -to HEX2[2]

+set_location_assignment PIN_AC28 -to HEX2[3]

+set_location_assignment PIN_AD30 -to HEX2[4]

+set_location_assignment PIN_AC29 -to HEX2[5]

+set_location_assignment PIN_AC30 -to HEX2[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]

+

+#============================================================

+# HEX3

+#============================================================

+set_location_assignment PIN_AD26 -to HEX3[0]

+set_location_assignment PIN_AC27 -to HEX3[1]

+set_location_assignment PIN_AD25 -to HEX3[2]

+set_location_assignment PIN_AC25 -to HEX3[3]

+set_location_assignment PIN_AB28 -to HEX3[4]

+set_location_assignment PIN_AB25 -to HEX3[5]

+set_location_assignment PIN_AB22 -to HEX3[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]

+

+#============================================================

+# HEX4

+#============================================================

+set_location_assignment PIN_AA24 -to HEX4[0]

+set_location_assignment PIN_Y23 -to HEX4[1]

+set_location_assignment PIN_Y24 -to HEX4[2]

+set_location_assignment PIN_W22 -to HEX4[3]

+set_location_assignment PIN_W24 -to HEX4[4]

+set_location_assignment PIN_V23 -to HEX4[5]

+set_location_assignment PIN_W25 -to HEX4[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]

+

+#============================================================

+# HEX5

+#============================================================

+set_location_assignment PIN_V25 -to HEX5[0]

+set_location_assignment PIN_AA28 -to HEX5[1]

+set_location_assignment PIN_Y27 -to HEX5[2]

+set_location_assignment PIN_AB27 -to HEX5[3]

+set_location_assignment PIN_AB26 -to HEX5[4]

+set_location_assignment PIN_AA26 -to HEX5[5]

+set_location_assignment PIN_AA25 -to HEX5[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]

+

+#============================================================

+# KEY

+#============================================================

+set_location_assignment PIN_AA14 -to KEY[0]

+set_location_assignment PIN_AA15 -to KEY[1]

+set_location_assignment PIN_W15 -to KEY[2]

+set_location_assignment PIN_Y16 -to KEY[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]

+

+#============================================================

+# LEDR

+#============================================================

+set_location_assignment PIN_V16 -to LEDR[0]

+set_location_assignment PIN_W16 -to LEDR[1]

+set_location_assignment PIN_V17 -to LEDR[2]

+set_location_assignment PIN_V18 -to LEDR[3]

+set_location_assignment PIN_W17 -to LEDR[4]

+set_location_assignment PIN_W19 -to LEDR[5]

+set_location_assignment PIN_Y19 -to LEDR[6]

+set_location_assignment PIN_W20 -to LEDR[7]

+set_location_assignment PIN_W21 -to LEDR[8]

+set_location_assignment PIN_Y21 -to LEDR[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]

+

+#============================================================

+# SW

+#============================================================

+set_location_assignment PIN_AB12 -to SW[0]

+set_location_assignment PIN_AC12 -to SW[1]

+set_location_assignment PIN_AF9 -to SW[2]

+set_location_assignment PIN_AF10 -to SW[3]

+set_location_assignment PIN_AD11 -to SW[4]

+set_location_assignment PIN_AD12 -to SW[5]

+set_location_assignment PIN_AE11 -to SW[6]

+set_location_assignment PIN_AC9 -to SW[7]

+set_location_assignment PIN_AD10 -to SW[8]

+set_location_assignment PIN_AE12 -to SW[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]

+

+#============================================================

+# End of pin and io_standard assignments

+#============================================================# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 09:21:41  November 23, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex8_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex8

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:21:41  NOVEMBER 23, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v

+set_global_assignment -name VERILOG_FILE verilog_files/delay.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v

+set_global_assignment -name VERILOG_FILE verilog_files/ex8.v

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex8/ex8.qsf.bak b/part_2/ex8/ex8.qsf.bak
new file mode 100755
index 0000000..910707e
--- /dev/null
+++ b/part_2/ex8/ex8.qsf.bak
@@ -0,0 +1,65 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 09:21:41  November 23, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex8_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex8

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:21:41  NOVEMBER 23, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v

+set_global_assignment -name VERILOG_FILE verilog_files/delay.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v

+set_global_assignment -name VERILOG_FILE verilog_files/ex8.v

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex8/ex8.qws b/part_2/ex8/ex8.qws
new file mode 100755
index 0000000..9089262
--- /dev/null
+++ b/part_2/ex8/ex8.qws
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info b/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
new file mode 100755
index 0000000..2914929
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Wed Nov 23 10:30:54 2016

diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
new file mode 100755
index 0000000..fb6a772
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
new file mode 100755
index 0000000..a5692a9
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.dfp b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.dfp
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..d458de1
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..593ea83
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.sig b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
new file mode 100755
index 0000000..5f0b6dc
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..449914f
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
new file mode 100755
index 0000000..db8a5f8
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
new file mode 100755
index 0000000..7caafad
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..207dc90
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hb_info b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..c7054d3
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.sig b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
new file mode 100755
index 0000000..608768a
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
new file mode 100755
index 0000000..ad2cc36
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb
new file mode 100755
index 0000000..78725ed
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb
new file mode 100755
index 0000000..e74f467
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb
new file mode 100755
index 0000000..0e7f8d9
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb
new file mode 100755
index 0000000..78725ed
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb
new file mode 100755
index 0000000..4c83a2e
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb
new file mode 100755
index 0000000..d958de6
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb
new file mode 100755
index 0000000..db8a5f8
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..207dc90
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..c7054d3
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb
new file mode 100755
index 0000000..608768a
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.kpt b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.kpt
new file mode 100755
index 0000000..ad2cc36
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.kpt
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
new file mode 100755
index 0000000..df267bf
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
new file mode 100755
index 0000000..59c9e37
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
diff --git a/part_2/ex8/output_files/ex8.asm.rpt b/part_2/ex8/output_files/ex8.asm.rpt
new file mode 100755
index 0000000..f3c8b64
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex8

+Fri Nov 25 10:21:21 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Assembler Summary

+  3. Assembler Settings

+  4. Assembler Generated Files

+  5. Assembler Device Options: C:/New folder/ex8/output_files/ex8.sof

+  6. Assembler Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------+

+; Assembler Summary                                             ;

++-----------------------+---------------------------------------+

+; Assembler Status      ; Successful - Fri Nov 25 10:21:21 2016 ;

+; Revision Name         ; ex8                                   ;

+; Top-level Entity Name ; ex8                                   ;

+; Family                ; Cyclone V                             ;

+; Device                ; 5CSEMA5F31C6                          ;

++-----------------------+---------------------------------------+

+

+

++----------------------------------+

+; Assembler Settings               ;

++--------+---------+---------------+

+; Option ; Setting ; Default Value ;

++--------+---------+---------------+

+

+

++----------------------------------------+

+; Assembler Generated Files              ;

++----------------------------------------+

+; File Name                              ;

++----------------------------------------+

+; C:/New folder/ex8/output_files/ex8.sof ;

++----------------------------------------+

+

+

++------------------------------------------------------------------+

+; Assembler Device Options: C:/New folder/ex8/output_files/ex8.sof ;

++----------------+-------------------------------------------------+

+; Option         ; Setting                                         ;

++----------------+-------------------------------------------------+

+; Device         ; 5CSEMA5F31C6                                    ;

+; JTAG usercode  ; 0x00B20264                                      ;

+; Checksum       ; 0x00B20264                                      ;

++----------------+-------------------------------------------------+

+

+

++--------------------+

+; Assembler Messages ;

++--------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Assembler

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 10:21:15 2016

+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (115030): Assembler is generating device programming files

+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 891 megabytes

+    Info: Processing ended: Fri Nov 25 10:21:21 2016

+    Info: Elapsed time: 00:00:06

+    Info: Total CPU time (on all processors): 00:00:06

+

+

diff --git a/part_2/ex8/output_files/ex8.done b/part_2/ex8/output_files/ex8.done
new file mode 100755
index 0000000..6873047
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.done
@@ -0,0 +1 @@
+Fri Nov 25 10:21:28 2016

diff --git a/part_2/ex8/output_files/ex8.fit.rpt b/part_2/ex8/output_files/ex8.fit.rpt
new file mode 100755
index 0000000..3b99d43
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.fit.rpt
@@ -0,0 +1,2054 @@
+Fitter report for ex8

+Fri Nov 25 10:21:13 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Fitter Summary

+  3. Fitter Settings

+  4. Parallel Compilation

+  5. I/O Assignment Warnings

+  6. Fitter Netlist Optimizations

+  7. Ignored Assignments

+  8. Incremental Compilation Preservation Summary

+  9. Incremental Compilation Partition Settings

+ 10. Incremental Compilation Placement Preservation

+ 11. Pin-Out File

+ 12. Fitter Resource Usage Summary

+ 13. Fitter Partition Statistics

+ 14. Input Pins

+ 15. Output Pins

+ 16. I/O Bank Usage

+ 17. All Package Pins

+ 18. Fitter Resource Utilization by Entity

+ 19. Delay Chain Summary

+ 20. Pad To Core Delay Chain Fanout

+ 21. Control Signals

+ 22. Global & Other Fast Signals

+ 23. Routing Usage Summary

+ 24. I/O Rules Summary

+ 25. I/O Rules Details

+ 26. I/O Rules Matrix

+ 27. Fitter Device Options

+ 28. Operating Settings and Conditions

+ 29. Estimated Delay Added for Hold Timing Summary

+ 30. Estimated Delay Added for Hold Timing Details

+ 31. Fitter Messages

+ 32. Fitter Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Fitter Summary                                                                    ;

++---------------------------------+-------------------------------------------------+

+; Fitter Status                   ; Successful - Fri Nov 25 10:21:13 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex8                                             ;

+; Top-level Entity Name           ; ex8                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 75 / 32,070 ( < 1 % )                           ;

+; Total registers                 ; 76                                              ;

+; Total pins                      ; 36 / 457 ( 8 % )                                ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Settings                                                                                                                                            ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Option                                                                     ; Setting                               ; Default Value                         ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;

+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;

+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;

+; Use smart compilation                                                      ; Off                                   ; Off                                   ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;

+; Enable compact report table                                                ; Off                                   ; Off                                   ;

+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;

+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;

+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;

+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;

+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;

+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;

+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;

+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;

+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;

+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;

+; SSN Optimization                                                           ; Off                                   ; Off                                   ;

+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;

+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;

+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;

+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;

+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;

+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;

+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;

+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;

+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;

+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;

+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;

+; Auto Delay Chains                                                          ; On                                    ; On                                    ;

+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;

+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;

+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;

+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;

+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;

+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;

+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;

+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;

+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;

+; Auto Global Clock                                                          ; On                                    ; On                                    ;

+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;

+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;

+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;

+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;

+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;

+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;

+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;

+; Clamping Diode                                                             ; Off                                   ; Off                                   ;

+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;

+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.01        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.5%      ;

+;     Processor 3            ;   0.5%      ;

+;     Processor 4            ;   0.4%      ;

++----------------------------+-------------+

+

+

++-------------------------------------------------+

+; I/O Assignment Warnings                         ;

++----------+--------------------------------------+

+; Pin Name ; Reason                               ;

++----------+--------------------------------------+

+; HEX0[0]  ; Missing drive strength and slew rate ;

+; HEX0[1]  ; Missing drive strength and slew rate ;

+; HEX0[2]  ; Missing drive strength and slew rate ;

+; HEX0[3]  ; Missing drive strength and slew rate ;

+; HEX0[4]  ; Missing drive strength and slew rate ;

+; HEX0[5]  ; Missing drive strength and slew rate ;

+; HEX0[6]  ; Missing drive strength and slew rate ;

+; HEX1[0]  ; Missing drive strength and slew rate ;

+; HEX1[1]  ; Missing drive strength and slew rate ;

+; HEX1[2]  ; Missing drive strength and slew rate ;

+; HEX1[3]  ; Missing drive strength and slew rate ;

+; HEX1[4]  ; Missing drive strength and slew rate ;

+; HEX1[5]  ; Missing drive strength and slew rate ;

+; HEX1[6]  ; Missing drive strength and slew rate ;

+; HEX2[0]  ; Missing drive strength and slew rate ;

+; HEX2[1]  ; Missing drive strength and slew rate ;

+; HEX2[2]  ; Missing drive strength and slew rate ;

+; HEX2[3]  ; Missing drive strength and slew rate ;

+; HEX2[4]  ; Missing drive strength and slew rate ;

+; HEX2[5]  ; Missing drive strength and slew rate ;

+; HEX2[6]  ; Missing drive strength and slew rate ;

+; LEDR[0]  ; Missing drive strength and slew rate ;

+; LEDR[1]  ; Missing drive strength and slew rate ;

+; LEDR[2]  ; Missing drive strength and slew rate ;

+; LEDR[3]  ; Missing drive strength and slew rate ;

+; LEDR[4]  ; Missing drive strength and slew rate ;

+; LEDR[5]  ; Missing drive strength and slew rate ;

+; LEDR[6]  ; Missing drive strength and slew rate ;

+; LEDR[7]  ; Missing drive strength and slew rate ;

+; LEDR[8]  ; Missing drive strength and slew rate ;

+; LEDR[9]  ; Missing drive strength and slew rate ;

++----------+--------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Netlist Optimizations                                                                                                                                                                                                            ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;

+; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[3]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[3]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[4]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[4]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+

+

++--------------------------------------------------------------------------------------------+

+; Ignored Assignments                                                                        ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[0]    ; PIN_AD26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[1]    ; PIN_AC27      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[2]    ; PIN_AD25      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[3]    ; PIN_AC25      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[4]    ; PIN_AB28      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[5]    ; PIN_AB25      ; QSF Assignment ;

+; Location     ;                ;              ; HEX3[6]    ; PIN_AB22      ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[0]    ; PIN_AA24      ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[1]    ; PIN_Y23       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[2]    ; PIN_Y24       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[3]    ; PIN_W22       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[4]    ; PIN_W24       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[5]    ; PIN_V23       ; QSF Assignment ;

+; Location     ;                ;              ; HEX4[6]    ; PIN_W25       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;

+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;

+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;

+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX3[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX3[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX3[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX3[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX3[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX3[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX3[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX4[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX4[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX4[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX4[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX4[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX4[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX4[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex8            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;

++--------------+----------------+--------------+------------+---------------+----------------+

+

+

++--------------------------------------------------------------------------------------------------+

+; Incremental Compilation Preservation Summary                                                     ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Placement (by node) ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 280 ) ; 0.00 % ( 0 / 280 )         ; 0.00 % ( 0 / 280 )       ;

+;     -- Achieved     ; 0.00 % ( 0 / 280 ) ; 0.00 % ( 0 / 280 )         ; 0.00 % ( 0 / 280 )       ;

+;                     ;                    ;                            ;                          ;

+; Routing (by net)    ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

++---------------------+--------------------+----------------------------+--------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Partition Settings                                                                                                                                             ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;

+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Placement Preservation                                                                                     ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Top                            ; 0.00 % ( 0 / 280 )    ; N/A                     ; Source File       ; N/A                 ;       ;

+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+

+

++--------------+

+; Pin-Out File ;

++--------------+

+The pin-out file can be found in C:/New folder/ex8/output_files/ex8.pin.

+

+

++------------------------------------------------------------------------------------------+

+; Fitter Resource Usage Summary                                                            ;

++-------------------------------------------------------------+--------------------+-------+

+; Resource                                                    ; Usage              ; %     ;

++-------------------------------------------------------------+--------------------+-------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 75 / 32,070        ; < 1 % ;

+; ALMs needed [=A-B+C]                                        ; 75                 ;       ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 77 / 32,070        ; < 1 % ;

+;         [a] ALMs used for LUT logic and registers           ; 31                 ;       ;

+;         [b] ALMs used for LUT logic                         ; 43                 ;       ;

+;         [c] ALMs used for registers                         ; 3                  ;       ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 2 / 32,070         ; < 1 % ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;

+;         [a] Due to location constrained logic               ; 0                  ;       ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;

+;         [c] Due to LAB input limits                         ; 0                  ;       ;

+;         [d] Due to virtual I/Os                             ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Difficulty packing design                                   ; Low                ;       ;

+;                                                             ;                    ;       ;

+; Total LABs:  partially or completely used                   ; 10 / 3,207         ; < 1 % ;

+;     -- Logic LABs                                           ; 10                 ;       ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Combinational ALUT usage for logic                          ; 139                ;       ;

+;     -- 7 input functions                                    ; 0                  ;       ;

+;     -- 6 input functions                                    ; 11                 ;       ;

+;     -- 5 input functions                                    ; 14                 ;       ;

+;     -- 4 input functions                                    ; 33                 ;       ;

+;     -- <=3 input functions                                  ; 81                 ;       ;

+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;

+; Dedicated logic registers                                   ; 76                 ;       ;

+;     -- By type:                                             ;                    ;       ;

+;         -- Primary logic registers                          ; 68 / 64,140        ; < 1 % ;

+;         -- Secondary logic registers                        ; 8 / 64,140         ; < 1 % ;

+;     -- By function:                                         ;                    ;       ;

+;         -- Design implementation registers                  ; 68                 ;       ;

+;         -- Routing optimization registers                   ; 8                  ;       ;

+;                                                             ;                    ;       ;

+; Virtual pins                                                ; 0                  ;       ;

+; I/O pins                                                    ; 36 / 457           ; 8 %   ;

+;     -- Clock pins                                           ; 2 / 8              ; 25 %  ;

+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Hard processor system peripheral utilization                ;                    ;       ;

+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;

+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;

+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;

+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;

+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;

+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;

+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;

+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;

+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;

+;                                                             ;                    ;       ;

+; Global signals                                              ; 1                  ;       ;

+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;

+; Total MLAB memory bits                                      ; 0                  ;       ;

+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;

+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;

+;                                                             ;                    ;       ;

+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;

+; Global clocks                                               ; 1 / 16             ; 6 %   ;

+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;

+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;

+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;

+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;

+; JTAGs                                                       ; 0 / 1              ; 0 %   ;

+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;

+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;

+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;

+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;

+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;

+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;

+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;

+; Peak interconnect usage (total/H/V)                         ; 2.7% / 3.1% / 1.6% ;       ;

+; Maximum fan-out                                             ; 41                 ;       ;

+; Highest non-global fan-out                                  ; 41                 ;       ;

+; Total fan-out                                               ; 702                ;       ;

+; Average fan-out                                             ; 2.44               ;       ;

++-------------------------------------------------------------+--------------------+-------+

+

+

++---------------------------------------------------------------------------------------------------------------------+

+; Fitter Partition Statistics                                                                                         ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Statistic                                                   ; Top                  ; hard_block:auto_generated_inst ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 75 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+; ALMs needed [=A-B+C]                                        ; 75                   ; 0                              ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 77 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+;         [a] ALMs used for LUT logic and registers           ; 31                   ; 0                              ;

+;         [b] ALMs used for LUT logic                         ; 43                   ; 0                              ;

+;         [c] ALMs used for registers                         ; 3                    ; 0                              ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                    ; 0                              ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 2 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )    ; 0 / 32070 ( 0 % )              ;

+;         [a] Due to location constrained logic               ; 0                    ; 0                              ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                    ; 0                              ;

+;         [c] Due to LAB input limits                         ; 0                    ; 0                              ;

+;         [d] Due to virtual I/Os                             ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Difficulty packing design                                   ; Low                  ; Low                            ;

+;                                                             ;                      ;                                ;

+; Total LABs:  partially or completely used                   ; 10 / 3207 ( < 1 % )  ; 0 / 3207 ( 0 % )               ;

+;     -- Logic LABs                                           ; 10                   ; 0                              ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Combinational ALUT usage for logic                          ; 139                  ; 0                              ;

+;     -- 7 input functions                                    ; 0                    ; 0                              ;

+;     -- 6 input functions                                    ; 11                   ; 0                              ;

+;     -- 5 input functions                                    ; 14                   ; 0                              ;

+;     -- 4 input functions                                    ; 33                   ; 0                              ;

+;     -- <=3 input functions                                  ; 81                   ; 0                              ;

+; Combinational ALUT usage for route-throughs                 ; 0                    ; 0                              ;

+; Memory ALUT usage                                           ; 0                    ; 0                              ;

+;     -- 64-address deep                                      ; 0                    ; 0                              ;

+;     -- 32-address deep                                      ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Dedicated logic registers                                   ; 0                    ; 0                              ;

+;     -- By type:                                             ;                      ;                                ;

+;         -- Primary logic registers                          ; 68 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;

+;         -- Secondary logic registers                        ; 8 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;     -- By function:                                         ;                      ;                                ;

+;         -- Design implementation registers                  ; 68                   ; 0                              ;

+;         -- Routing optimization registers                   ; 8                    ; 0                              ;

+;                                                             ;                      ;                                ;

+;                                                             ;                      ;                                ;

+; Virtual pins                                                ; 0                    ; 0                              ;

+; I/O pins                                                    ; 36                   ; 0                              ;

+; I/O registers                                               ; 0                    ; 0                              ;

+; Total block memory bits                                     ; 0                    ; 0                              ;

+; Total block memory implementation bits                      ; 0                    ; 0                              ;

+; Clock enable block                                          ; 1 / 116 ( < 1 % )    ; 0 / 116 ( 0 % )                ;

+;                                                             ;                      ;                                ;

+; Connections                                                 ;                      ;                                ;

+;     -- Input Connections                                    ; 0                    ; 0                              ;

+;     -- Registered Input Connections                         ; 0                    ; 0                              ;

+;     -- Output Connections                                   ; 0                    ; 0                              ;

+;     -- Registered Output Connections                        ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Internal Connections                                        ;                      ;                                ;

+;     -- Total Connections                                    ; 702                  ; 0                              ;

+;     -- Registered Connections                               ; 302                  ; 0                              ;

+;                                                             ;                      ;                                ;

+; External Connections                                        ;                      ;                                ;

+;     -- Top                                                  ; 0                    ; 0                              ;

+;     -- hard_block:auto_generated_inst                       ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Partition Interface                                         ;                      ;                                ;

+;     -- Input Ports                                          ; 5                    ; 0                              ;

+;     -- Output Ports                                         ; 31                   ; 0                              ;

+;     -- Bidir Ports                                          ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Registered Ports                                            ;                      ;                                ;

+;     -- Registered Input Ports                               ; 0                    ; 0                              ;

+;     -- Registered Output Ports                              ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Port Connectivity                                           ;                      ;                                ;

+;     -- Input Ports driven by GND                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by GND                           ; 0                    ; 0                              ;

+;     -- Input Ports driven by VCC                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by VCC                           ; 0                    ; 0                              ;

+;     -- Input Ports with no Source                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Source                          ; 0                    ; 0                              ;

+;     -- Input Ports with no Fanout                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Fanout                          ; 0                    ; 0                              ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Input Pins                                                                                                                                                                                                                                                                              ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 38                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+

+

++----------------------------------------------------------------------------+

+; I/O Bank Usage                                                             ;

++----------+------------------+---------------+--------------+---------------+

+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;

++----------+------------------+---------------+--------------+---------------+

+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 3B       ; 5 / 48 ( 10 % )  ; 3.3V          ; --           ; 3.3V          ;

+; 4A       ; 7 / 80 ( 9 % )   ; 3.3V          ; --           ; 3.3V          ;

+; 5A       ; 18 / 32 ( 56 % ) ; 3.3V          ; --           ; 3.3V          ;

+; 5B       ; 6 / 16 ( 38 % )  ; 3.3V          ; --           ; 3.3V          ;

+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

++----------+------------------+---------------+--------------+---------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; All Package Pins                                                                                                                                                                  ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;

+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;

+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+Note: Pin directions (input, output or bidir) are based on device operating in user mode.

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+; |ex8                       ; 74.5 (0.5)           ; 77.0 (0.5)                       ; 2.5 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 139 (1)             ; 76 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 36   ; 0            ; |ex8                             ; ex8         ; work         ;

+;    |LFSR:LFSR0|            ; 2.6 (2.6)            ; 2.9 (2.9)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|LFSR:LFSR0                  ; LFSR        ; work         ;

+;    |bin2bcd_16:BCD|        ; 6.2 (0.0)            ; 6.2 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 14 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A22|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 1.3 (1.3)            ; 1.7 (1.7)                        ; 0.4 (0.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A30|       ; 1.5 (1.5)            ; 1.5 (1.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;

+;       |add3_ge5:A34|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;

+;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;

+;    |delay:DEL0|            ; 12.3 (12.3)          ; 13.3 (13.3)                      ; 1.0 (1.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 22 (22)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|delay:DEL0                  ; delay       ; work         ;

+;    |formula_fsm:FSM|       ; 9.1 (9.1)            ; 9.1 (9.1)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (16)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|formula_fsm:FSM             ; formula_fsm ; work         ;

+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 7.2 (7.2)            ; 7.5 (7.5)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;

+;    |tick_2500:TICK1|       ; 14.4 (14.4)          ; 15.2 (15.2)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 27 (27)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|tick_2500:TICK1             ; tick_2500   ; work         ;

+;    |tick_50000:TICK0|      ; 18.1 (18.1)          ; 18.8 (18.8)                      ; 0.7 (0.7)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 25 (25)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|tick_50000:TICK0            ; tick_50000  ; work         ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Delay Chain Summary                                                                                                     ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; KEY[0]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; KEY[3]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+

+

++-------------------------------------------------------------------------------+

+; Pad To Core Delay Chain Fanout                                                ;

++-------------------------------------------------+-------------------+---------+

+; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;

++-------------------------------------------------+-------------------+---------+

+; KEY[0]                                          ;                   ;         ;

+; KEY[1]                                          ;                   ;         ;

+; KEY[2]                                          ;                   ;         ;

+; KEY[3]                                          ;                   ;         ;

+;      - formula_fsm:FSM|Selector3~0              ; 0                 ; 0       ;

+;      - formula_fsm:FSM|Selector2~0              ; 0                 ; 0       ;

+;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 0                 ; 0       ;

+; CLOCK_50                                        ;                   ;         ;

+;      - tick_50000:TICK0|CLK_OUT                 ; 1                 ; 0       ;

+;      - tick_2500:TICK1|CLK_OUT                  ; 1                 ; 0       ;

++-------------------------------------------------+-------------------+---------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Control Signals                                                                                                                                                                ;

++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+; CLOCK_50                            ; PIN_AF14           ; 3       ; Clock                      ; no     ; --                   ; --               ; --                        ;

+; CLOCK_50                            ; PIN_AF14           ; 36      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;

+; delay:DEL0|count[2]~0               ; LABCELL_X74_Y7_N48 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;

+; delay:DEL0|state.COUNTING           ; FF_X74_Y7_N47      ; 18      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X75_Y7_N47      ; 19      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;

+; tick_2500:TICK1|CLK_OUT             ; FF_X74_Y8_N46      ; 10      ; Clock                      ; no     ; --                   ; --               ; --                        ;

+; tick_50000:TICK0|CLK_OUT            ; FF_X74_Y8_N44      ; 41      ; Clock, Clock enable        ; no     ; --                   ; --               ; --                        ;

++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Global & Other Fast Signals                                                                         ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; CLOCK_50 ; PIN_AF14 ; 36      ; Global Clock         ; GCLK6            ; --                        ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------+

+; Routing Usage Summary                                                 ;

++---------------------------------------------+-------------------------+

+; Routing Resource Type                       ; Usage                   ;

++---------------------------------------------+-------------------------+

+; Block interconnects                         ; 210 / 289,320 ( < 1 % ) ;

+; C12 interconnects                           ; 10 / 13,420 ( < 1 % )   ;

+; C2 interconnects                            ; 75 / 119,108 ( < 1 % )  ;

+; C4 interconnects                            ; 47 / 56,300 ( < 1 % )   ;

+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;

+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;

+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;

+; Direct links                                ; 35 / 289,320 ( < 1 % )  ;

+; Global clocks                               ; 1 / 16 ( 6 % )          ;

+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;

+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;

+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;

+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;

+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;

+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;

+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;

+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;

+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;

+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;

+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;

+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;

+; Local interconnects                         ; 67 / 84,580 ( < 1 % )   ;

+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;

+; R14 interconnects                           ; 44 / 12,676 ( < 1 % )   ;

+; R14/C12 interconnect drivers                ; 45 / 20,720 ( < 1 % )   ;

+; R3 interconnects                            ; 129 / 130,992 ( < 1 % ) ;

+; R6 interconnects                            ; 131 / 266,960 ( < 1 % ) ;

+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;

+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;

++---------------------------------------------+-------------------------+

+

+

++------------------------------------------+

+; I/O Rules Summary                        ;

++----------------------------------+-------+

+; I/O Rules Statistic              ; Total ;

++----------------------------------+-------+

+; Total I/O Rules                  ; 28    ;

+; Number of I/O Rules Passed       ; 6     ;

+; Number of I/O Rules Failed       ; 0     ;

+; Number of I/O Rules Unchecked    ; 0     ;

+; Number of I/O Rules Inapplicable ; 22    ;

++----------------------------------+-------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Details                                                                                                                                                                                                                                                  ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;

+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;

+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;

+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;

+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;

+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Total Pass         ; 36        ; 0            ; 36        ; 0            ; 0            ; 36        ; 36        ; 0            ; 36        ; 36        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Inapplicable ; 0         ; 36           ; 0         ; 36           ; 36           ; 0         ; 0         ; 36           ; 0         ; 0         ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ;

+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+

+

++------------------------------------------------------------------------------------------------+

+; Fitter Device Options                                                                          ;

++------------------------------------------------------------------+-----------------------------+

+; Option                                                           ; Setting                     ;

++------------------------------------------------------------------+-----------------------------+

+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;

+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;

+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;

+; Enable INIT_DONE output                                          ; Off                         ;

+; Configuration scheme                                             ; Passive Serial              ;

+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;

+; Enable CvP_CONFDONE pin                                          ; Off                         ;

+; Enable open drain on CRC_ERROR pin                               ; On                          ;

+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;

+; Enable open drain on INIT_DONE pin                               ; On                          ;

+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;

+; Enable open drain on nCEO pin                                    ; On                          ;

+; Enable Partial Reconfiguration pins                              ; Off                         ;

+; Enable input tri-state on active configuration pins in user mode ; Off                         ;

+; Enable internal scrubbing                                        ; Off                         ;

+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;

+; Device initialization clock source                               ; Internal Oscillator         ;

+; Configuration via Protocol                                       ; Off                         ;

+; Configuration Voltage Level                                      ; Auto                        ;

+; Force Configuration Voltage Level                                ; Off                         ;

+; Enable nCEO output                                               ; Off                         ;

+; Data[15..8]                                                      ; Unreserved                  ;

+; Data[7..5]                                                       ; Unreserved                  ;

+; Base pin-out file on sameframe device                            ; Off                         ;

++------------------------------------------------------------------+-----------------------------+

+

+

++------------------------------------+

+; Operating Settings and Conditions  ;

++---------------------------+--------+

+; Setting                   ; Value  ;

++---------------------------+--------+

+; Nominal Core Voltage      ; 1.10 V ;

+; Low Junction Temperature  ; 0 °C   ;

+; High Junction Temperature ; 85 °C  ;

++---------------------------+--------+

+

+

++------------------------------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Summary                                      ;

++-------------------------------------+--------------------------+-------------------+

+; Source Clock(s)                     ; Destination Clock(s)     ; Delay Added in ns ;

++-------------------------------------+--------------------------+-------------------+

+; CLOCK_50                            ; CLOCK_50                 ; 47.2              ;

+; tick_50000:TICK0|CLK_OUT            ; tick_2500:TICK1|CLK_OUT  ; 26.1              ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT ; 22.2              ;

+; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT  ; 8.3               ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 2.9               ;

++-------------------------------------+--------------------------+-------------------+

+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.

+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.

+

+

++-----------------------------------------------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Details                                                       ;

++----------------------------------------+----------------------------------------+-------------------+

+; Source Register                        ; Destination Register                   ; Delay Added in ns ;

++----------------------------------------+----------------------------------------+-------------------+

+; tick_50000:TICK0|CLK_OUT               ; tick_2500:TICK1|CLK_OUT                ; 6.343             ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[1]                ; 2.046             ;

+; tick_2500:TICK1|count[0]               ; tick_2500:TICK1|CLK_OUT                ; 2.022             ;

+; tick_2500:TICK1|count[1]               ; tick_2500:TICK1|CLK_OUT                ; 1.994             ;

+; tick_2500:TICK1|count[2]               ; tick_2500:TICK1|CLK_OUT                ; 1.977             ;

+; tick_2500:TICK1|count[3]               ; tick_2500:TICK1|CLK_OUT                ; 1.949             ;

+; tick_2500:TICK1|count[4]               ; tick_2500:TICK1|CLK_OUT                ; 1.942             ;

+; tick_2500:TICK1|count[11]              ; tick_2500:TICK1|CLK_OUT                ; 1.855             ;

+; tick_2500:TICK1|count[5]               ; tick_2500:TICK1|CLK_OUT                ; 1.808             ;

+; tick_2500:TICK1|count[8]               ; tick_2500:TICK1|CLK_OUT                ; 1.701             ;

+; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT               ; 1.692             ;

+; tick_2500:TICK1|count[9]               ; tick_2500:TICK1|CLK_OUT                ; 1.687             ;

+; tick_2500:TICK1|count[6]               ; tick_2500:TICK1|CLK_OUT                ; 1.681             ;

+; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT               ; 1.671             ;

+; tick_2500:TICK1|count[7]               ; tick_2500:TICK1|CLK_OUT                ; 1.632             ;

+; tick_2500:TICK1|count[10]              ; tick_2500:TICK1|CLK_OUT                ; 1.624             ;

+; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT               ; 1.584             ;

+; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT               ; 1.577             ;

+; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT               ; 1.569             ;

+; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT               ; 1.568             ;

+; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT               ; 1.564             ;

+; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT               ; 1.555             ;

+; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT               ; 1.552             ;

+; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT               ; 1.551             ;

+; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT               ; 1.536             ;

+; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT               ; 1.505             ;

+; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT               ; 1.496             ;

+; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT               ; 1.467             ;

+; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT               ; 1.465             ;

+; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT               ; 1.460             ;

+; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE                  ; 1.326             ;

+; delay:DEL0|count[13]                   ; delay:DEL0|state.IDLE                  ; 1.124             ;

+; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|ledr[9]                ; 0.949             ;

+; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|ledr[4]                ; 0.939             ;

+; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|ledr[6]                ; 0.939             ;

+; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|ledr[8]                ; 0.939             ;

+; delay:DEL0|count[12]                   ; delay:DEL0|state.IDLE                  ; 0.934             ;

+; delay:DEL0|count[3]                    ; delay:DEL0|state.IDLE                  ; 0.920             ;

+; delay:DEL0|count[2]                    ; delay:DEL0|state.IDLE                  ; 0.919             ;

+; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|ledr[7]                ; 0.916             ;

+; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                    ; 0.915             ;

+; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                    ; 0.915             ;

+; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|ledr[5]                ; 0.914             ;

+; delay:DEL0|count[9]                    ; delay:DEL0|state.IDLE                  ; 0.914             ;

+; delay:DEL0|count[8]                    ; delay:DEL0|state.IDLE                  ; 0.912             ;

+; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|ledr[1]                ; 0.910             ;

+; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|ledr[3]                ; 0.910             ;

+; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|ledr[2]                ; 0.900             ;

+; delay:DEL0|count[0]                    ; delay:DEL0|state.IDLE                  ; 0.893             ;

+; delay:DEL0|count[1]                    ; delay:DEL0|state.IDLE                  ; 0.876             ;

+; delay:DEL0|count[4]                    ; delay:DEL0|state.IDLE                  ; 0.821             ;

+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[1]                ; 0.809             ;

+; delay:DEL0|count[6]                    ; delay:DEL0|state.IDLE                  ; 0.803             ;

+; delay:DEL0|count[5]                    ; delay:DEL0|state.IDLE                  ; 0.803             ;

+; delay:DEL0|count[7]                    ; delay:DEL0|state.IDLE                  ; 0.802             ;

+; delay:DEL0|count[11]                   ; delay:DEL0|state.IDLE                  ; 0.770             ;

+; delay:DEL0|count[10]                   ; delay:DEL0|state.IDLE                  ; 0.761             ;

+; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; 0.657             ;

+; LFSR:LFSR0|COUNT[3]                    ; delay:DEL0|count[9]                    ; 0.637             ;

+; LFSR:LFSR0|COUNT[5]                    ; delay:DEL0|count[11]                   ; 0.633             ;

+; LFSR:LFSR0|COUNT[2]                    ; LFSR:LFSR0|COUNT[3]                    ; 0.630             ;

+; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.WAIT_LOW              ; 0.622             ;

+; delay:DEL0|state.TIME_OUT              ; delay:DEL0|state.WAIT_LOW              ; 0.622             ;

+; LFSR:LFSR0|COUNT[4]                    ; delay:DEL0|count[10]                   ; 0.620             ;

+; LFSR:LFSR0|COUNT[6]                    ; delay:DEL0|count[12]                   ; 0.620             ;

+; delay:DEL0|state.IDLE                  ; delay:DEL0|count[11]                   ; 0.608             ;

+; delay:DEL0|state.COUNTING              ; delay:DEL0|count[11]                   ; 0.608             ;

+; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.602             ;

+; KEY[3]                                 ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.602             ;

++----------------------------------------+----------------------------------------+-------------------+

+Note: This table only shows the top 69 path(s) that have the largest delay added for hold.

+

+

++-----------------+

+; Fitter Messages ;

++-----------------+

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (119006): Selected device 5CSEMA5F31C6 for design "ex8"

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

+Info (184020): Starting Fitter periphery placement operations

+Info (11191): Automatically promoted 1 clock (1 global)

+    Info (11162): CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6

+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

+Info (176233): Starting register packing

+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332144): No user constrained base clocks found in the design

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.

+Info (176235): Finished register packing

+    Extra Info (176219): No registers were packed into other blocks

+Warning (15705): Ignored locations or region assignments to the following nodes

+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design

+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11

+Info (170189): Fitter placement preparation operations beginning

+Info (14951): The Fitter is using Advanced Physical Optimization.

+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01

+Info (170191): Fitter placement operations beginning

+Info (170137): Fitter placement was successful

+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01

+Info (170193): Fitter routing operations beginning

+Info (170195): Router estimated average interconnect usage is 0% of the available device resources

+    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10

+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.

+    Info (170201): Optimizations that may affect the design's routability were skipped

+Info (170194): Fitter routing operations ending: elapsed time is 00:00:04

+Info (11888): Total time spent on timing analysis during the Fitter is 0.42 seconds.

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03

+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

+Info (144001): Generated suppressed messages file C:/New folder/ex8/output_files/ex8.fit.smsg

+Info: Quartus Prime Fitter was successful. 0 errors, 51 warnings

+    Info: Peak virtual memory: 2595 megabytes

+    Info: Processing ended: Fri Nov 25 10:21:14 2016

+    Info: Elapsed time: 00:00:34

+    Info: Total CPU time (on all processors): 00:00:58

+

+

++----------------------------+

+; Fitter Suppressed Messages ;

++----------------------------+

+The suppressed messages can be found in C:/New folder/ex8/output_files/ex8.fit.smsg.

+

+

diff --git a/part_2/ex8/output_files/ex8.fit.smsg b/part_2/ex8/output_files/ex8.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing

+Extra Info (176237): Finished Fast Input/Output/OE register processing

+Extra Info (176238): Start inferring scan chains for DSP blocks

+Extra Info (176239): Inferring scan chains for DSP blocks is complete

+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density

+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

diff --git a/part_2/ex8/output_files/ex8.fit.summary b/part_2/ex8/output_files/ex8.fit.summary
new file mode 100755
index 0000000..ae3c656
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Fri Nov 25 10:21:13 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex8

+Top-level Entity Name : ex8

+Family : Cyclone V

+Device : 5CSEMA5F31C6

+Timing Models : Final

+Logic utilization (in ALMs) : 75 / 32,070 ( < 1 % )

+Total registers : 76

+Total pins : 36 / 457 ( 8 % )

+Total virtual pins : 0

+Total block memory bits : 0 / 4,065,280 ( 0 % )

+Total RAM Blocks : 0 / 397 ( 0 % )

+Total DSP Blocks : 0 / 87 ( 0 % )

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0 / 6 ( 0 % )

+Total DLLs : 0 / 4 ( 0 % )

diff --git a/part_2/ex8/output_files/ex8.flow.rpt b/part_2/ex8/output_files/ex8.flow.rpt
new file mode 100755
index 0000000..5a0c85e
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.flow.rpt
@@ -0,0 +1,128 @@
+Flow report for ex8

+Fri Nov 25 10:21:27 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Flow Summary

+  3. Flow Settings

+  4. Flow Non-Default Global Settings

+  5. Flow Elapsed Time

+  6. Flow OS Summary

+  7. Flow Log

+  8. Flow Messages

+  9. Flow Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Flow Summary                                                                      ;

++---------------------------------+-------------------------------------------------+

+; Flow Status                     ; Successful - Fri Nov 25 10:21:21 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex8                                             ;

+; Top-level Entity Name           ; ex8                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 75 / 32,070 ( < 1 % )                           ;

+; Total registers                 ; 76                                              ;

+; Total pins                      ; 36 / 457 ( 8 % )                                ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++-----------------------------------------+

+; Flow Settings                           ;

++-------------------+---------------------+

+; Option            ; Setting             ;

++-------------------+---------------------+

+; Start date & time ; 11/25/2016 10:20:30 ;

+; Main task         ; Compilation         ;

+; Revision Name     ; ex8                 ;

++-------------------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------+

+; Flow Non-Default Global Settings                                                                                       ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; COMPILER_SIGNATURE_ID               ; 260248564297095.148006922903352       ; --            ; --          ; --         ;

+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;

+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;

+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;

+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;

+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;

+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;

+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;

+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------+

+; Flow Elapsed Time                                                                                                             ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 916 MB              ; 00:00:22                           ;

+; Fitter                    ; 00:00:33     ; 1.0                     ; 2595 MB             ; 00:00:58                           ;

+; Assembler                 ; 00:00:06     ; 1.0                     ; 890 MB              ; 00:00:06                           ;

+; TimeQuest Timing Analyzer ; 00:00:05     ; 1.1                     ; 1209 MB             ; 00:00:05                           ;

+; Total                     ; 00:00:54     ; --                      ; --                  ; 00:01:31                           ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+

+

++----------------------------------------------------------------------------------------+

+; Flow OS Summary                                                                        ;

++---------------------------+------------------+-----------+------------+----------------+

+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;

++---------------------------+------------------+-----------+------------+----------------+

+; Analysis & Synthesis      ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; Fitter                    ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; Assembler                 ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; TimeQuest Timing Analyzer ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

++---------------------------+------------------+-----------+------------+----------------+

+

+

+------------

+; Flow Log ;

+------------

+quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8

+quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8

+quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8

+quartus_sta ex8 -c ex8

+

+

+

diff --git a/part_2/ex8/output_files/ex8.jdi b/part_2/ex8/output_files/ex8.jdi
new file mode 100755
index 0000000..02e5642
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>

+  <project>

+    <hash md5_digest_80b="1da9bc28c8befe910722"/>

+  </project>

+  <file_info>

+    <file device="5CSEMA5F31C6" path="ex8.sof" usercode="0xFFFFFFFF"/>

+  </file_info>

+</sld_project_info>

diff --git a/part_2/ex8/output_files/ex8.map.rpt b/part_2/ex8/output_files/ex8.map.rpt
new file mode 100755
index 0000000..349f864
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.map.rpt
@@ -0,0 +1,579 @@
+Analysis & Synthesis report for ex8

+Fri Nov 25 10:20:39 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Analysis & Synthesis Summary

+  3. Analysis & Synthesis Settings

+  4. Parallel Compilation

+  5. Analysis & Synthesis Source Files Read

+  6. Analysis & Synthesis Resource Usage Summary

+  7. Analysis & Synthesis Resource Utilization by Entity

+  8. State Machine - |ex8|delay:DEL0|state

+  9. State Machine - |ex8|formula_fsm:FSM|state

+ 10. User-Specified and Inferred Latches

+ 11. Registers Removed During Synthesis

+ 12. General Register Statistics

+ 13. Inverted Register Statistics

+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)

+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0

+ 16. Parameter Settings for User Entity Instance: tick_2500:TICK1

+ 17. Parameter Settings for User Entity Instance: formula_fsm:FSM

+ 18. Parameter Settings for User Entity Instance: delay:DEL0

+ 19. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"

+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"

+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"

+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"

+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"

+ 24. Port Connectivity Checks: "bin2bcd_16:BCD"

+ 25. Port Connectivity Checks: "delay:DEL0"

+ 26. Post-Synthesis Netlist Statistics for Top Partition

+ 27. Elapsed Time Per Partition

+ 28. Analysis & Synthesis Messages

+ 29. Analysis & Synthesis Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Analysis & Synthesis Summary                                                      ;

++---------------------------------+-------------------------------------------------+

+; Analysis & Synthesis Status     ; Successful - Fri Nov 25 10:20:39 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex8                                             ;

+; Top-level Entity Name           ; ex8                                             ;

+; Family                          ; Cyclone V                                       ;

+; Logic utilization (in ALMs)     ; N/A                                             ;

+; Total registers                 ; 68                                              ;

+; Total pins                      ; 36                                              ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0                                               ;

+; Total DSP Blocks                ; 0                                               ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0                                               ;

+; Total DLLs                      ; 0                                               ;

++---------------------------------+-------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Settings                                                                                             ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Option                                                                          ; Setting            ; Default Value      ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;

+; Top-level entity name                                                           ; ex8                ; ex8                ;

+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;

+; Use smart compilation                                                           ; Off                ; Off                ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;

+; Enable compact report table                                                     ; Off                ; Off                ;

+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;

+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;

+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;

+; Preserve fewer node names                                                       ; On                 ; On                 ;

+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;

+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;

+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;

+; State Machine Processing                                                        ; Auto               ; Auto               ;

+; Safe State Machine                                                              ; Off                ; Off                ;

+; Extract Verilog State Machines                                                  ; On                 ; On                 ;

+; Extract VHDL State Machines                                                     ; On                 ; On                 ;

+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;

+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;

+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;

+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;

+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;

+; Parallel Synthesis                                                              ; On                 ; On                 ;

+; DSP Block Balancing                                                             ; Auto               ; Auto               ;

+; NOT Gate Push-Back                                                              ; On                 ; On                 ;

+; Power-Up Don't Care                                                             ; On                 ; On                 ;

+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;

+; Remove Duplicate Registers                                                      ; On                 ; On                 ;

+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;

+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;

+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;

+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;

+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;

+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;

+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;

+; Optimization Technique                                                          ; Balanced           ; Balanced           ;

+; Carry Chain Length                                                              ; 70                 ; 70                 ;

+; Auto Carry Chains                                                               ; On                 ; On                 ;

+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;

+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;

+; Auto ROM Replacement                                                            ; On                 ; On                 ;

+; Auto RAM Replacement                                                            ; On                 ; On                 ;

+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;

+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;

+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;

+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;

+; Strict RAM Replacement                                                          ; Off                ; Off                ;

+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;

+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;

+; Auto Resource Sharing                                                           ; Off                ; Off                ;

+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;

+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;

+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;

+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;

+; Report Parameter Settings                                                       ; On                 ; On                 ;

+; Report Source Assignments                                                       ; On                 ; On                 ;

+; Report Connectivity Checks                                                      ; On                 ; On                 ;

+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;

+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;

+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;

+; HDL message level                                                               ; Level2             ; Level2             ;

+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;

+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;

+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;

+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;

+; Clock MUX Protection                                                            ; On                 ; On                 ;

+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;

+; Block Design Naming                                                             ; Auto               ; Auto               ;

+; SDC constraint protection                                                       ; Off                ; Off                ;

+; Synthesis Effort                                                                ; Auto               ; Auto               ;

+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;

+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;

+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;

+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;

+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;

+; Synthesis Seed                                                                  ; 1                  ; 1                  ;

+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;

+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.0%      ;

+;     Processors 3-4         ;   0.0%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Source Files Read                                                                                                ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ; Library ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/tick_50000.v  ;         ;

+; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/LFSR.v        ;         ;

+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/hex_to_7seg.v ;         ;

+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/bin2bcd_16.v  ;         ;

+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/add3_ge5.v    ;         ;

+; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/formula_fsm.v ;         ;

+; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/delay.v       ;         ;

+; verilog_files/tick_2500.v        ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/tick_2500.v   ;         ;

+; verilog_files/ex8.v              ; yes             ; User Verilog HDL File  ; C:/New folder/ex8/verilog_files/ex8.v         ;         ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+

+

++------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Usage Summary                            ;

++---------------------------------------------+--------------------------+

+; Resource                                    ; Usage                    ;

++---------------------------------------------+--------------------------+

+; Estimate of Logic utilization (ALMs needed) ; 76                       ;

+;                                             ;                          ;

+; Combinational ALUT usage for logic          ; 139                      ;

+;     -- 7 input functions                    ; 0                        ;

+;     -- 6 input functions                    ; 11                       ;

+;     -- 5 input functions                    ; 14                       ;

+;     -- 4 input functions                    ; 33                       ;

+;     -- <=3 input functions                  ; 81                       ;

+;                                             ;                          ;

+; Dedicated logic registers                   ; 68                       ;

+;                                             ;                          ;

+; I/O pins                                    ; 36                       ;

+;                                             ;                          ;

+; Total DSP Blocks                            ; 0                        ;

+;                                             ;                          ;

+; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;

+; Maximum fan-out                             ; 41                       ;

+; Total fan-out                               ; 685                      ;

+; Average fan-out                             ; 2.46                     ;

++---------------------------------------------+--------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+; |ex8                       ; 139 (1)           ; 68 (0)       ; 0                 ; 0          ; 36   ; 0            ; |ex8                             ; ex8         ; work         ;

+;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|LFSR:LFSR0                  ; LFSR        ; work         ;

+;    |bin2bcd_16:BCD|        ; 14 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A22|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;

+;       |add3_ge5:A34|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;

+;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;

+;    |delay:DEL0|            ; 22 (22)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex8|delay:DEL0                  ; delay       ; work         ;

+;    |formula_fsm:FSM|       ; 16 (16)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex8|formula_fsm:FSM             ; formula_fsm ; work         ;

+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;

+;    |tick_2500:TICK1|       ; 27 (27)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex8|tick_2500:TICK1             ; tick_2500   ; work         ;

+;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex8|tick_50000:TICK0            ; tick_50000  ; work         ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

+Encoding Type:  One-Hot

++--------------------------------------------------------------------------------+

+; State Machine - |ex8|delay:DEL0|state                                          ;

++----------------+----------------+----------------+----------------+------------+

+; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;

++----------------+----------------+----------------+----------------+------------+

+; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;

+; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;

+; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;

+; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;

++----------------+----------------+----------------+----------------+------------+

+

+

+Encoding Type:  One-Hot

++--------------------------------------------------------------------------------------------+

+; State Machine - |ex8|formula_fsm:FSM|state                                                 ;

++------------------------+--------------------+------------------------+---------------------+

+; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;

++------------------------+--------------------+------------------------+---------------------+

+; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;

+; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;

+; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;

++------------------------+--------------------+------------------------+---------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------+

+; User-Specified and Inferred Latches                                                                               ;

++----------------------------------------------------+-------------------------------------+------------------------+

+; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;

++----------------------------------------------------+-------------------------------------+------------------------+

+; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;

+; Number of user-specified and inferred latches = 1  ;                                     ;                        ;

++----------------------------------------------------+-------------------------------------+------------------------+

+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.

+

+

++------------------------------------------------------------+

+; Registers Removed During Synthesis                         ;

++---------------------------------------+--------------------+

+; Register name                         ; Reason for Removal ;

++---------------------------------------+--------------------+

+; delay:DEL0|state~5                    ; Lost fanout        ;

+; delay:DEL0|state~6                    ; Lost fanout        ;

+; Total Number of Removed Registers = 2 ;                    ;

++---------------------------------------+--------------------+

+

+

++------------------------------------------------------+

+; General Register Statistics                          ;

++----------------------------------------------+-------+

+; Statistic                                    ; Value ;

++----------------------------------------------+-------+

+; Total registers                              ; 68    ;

+; Number of registers using Synchronous Clear  ; 0     ;

+; Number of registers using Synchronous Load   ; 15    ;

+; Number of registers using Asynchronous Clear ; 0     ;

+; Number of registers using Asynchronous Load  ; 0     ;

+; Number of registers using Clock Enable       ; 32    ;

+; Number of registers using Preset             ; 0     ;

++----------------------------------------------+-------+

+

+

++---------------------------------------------------+

+; Inverted Register Statistics                      ;

++-----------------------------------------+---------+

+; Inverted Register                       ; Fan out ;

++-----------------------------------------+---------+

+; LFSR:LFSR0|COUNT[1]                     ; 10      ;

+; tick_50000:TICK0|count[14]              ; 2       ;

+; tick_50000:TICK0|count[15]              ; 2       ;

+; tick_50000:TICK0|count[0]               ; 2       ;

+; tick_50000:TICK0|count[1]               ; 2       ;

+; tick_50000:TICK0|count[2]               ; 2       ;

+; tick_50000:TICK0|count[3]               ; 2       ;

+; tick_50000:TICK0|count[6]               ; 2       ;

+; tick_50000:TICK0|count[8]               ; 2       ;

+; tick_50000:TICK0|count[9]               ; 2       ;

+; tick_2500:TICK1|count[11]               ; 8       ;

+; tick_2500:TICK1|count[0]                ; 2       ;

+; tick_2500:TICK1|count[1]                ; 2       ;

+; tick_2500:TICK1|count[6]                ; 2       ;

+; tick_2500:TICK1|count[7]                ; 2       ;

+; tick_2500:TICK1|count[8]                ; 2       ;

+; Total number of inverted registers = 16 ;         ;

++-----------------------------------------+---------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------+

+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+

+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+

+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex8|delay:DEL0|count[2]       ;

+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex8|delay:DEL0|count[13]      ;

+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex8|formula_fsm:FSM|Selector2 ;

+; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex8|delay:DEL0|Selector16     ;

+; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex8|delay:DEL0|Selector17     ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+

+

+

++---------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;

++----------------+-------+--------------------------------------+

+; Parameter Name ; Value ; Type                                 ;

++----------------+-------+--------------------------------------+

+; NBIT           ; 16    ; Signed Integer                       ;

++----------------+-------+--------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++--------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;

++----------------+-------+-------------------------------------+

+; Parameter Name ; Value ; Type                                ;

++----------------+-------+-------------------------------------+

+; NBIT           ; 12    ; Signed Integer                      ;

++----------------+-------+-------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++--------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;

++------------------+-------+-----------------------------------+

+; Parameter Name   ; Value ; Type                              ;

++------------------+-------+-----------------------------------+

+; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;

+; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;

+; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;

++------------------+-------+-----------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++---------------------------------------------------------+

+; Parameter Settings for User Entity Instance: delay:DEL0 ;

++----------------+-------+--------------------------------+

+; Parameter Name ; Value ; Type                           ;

++----------------+-------+--------------------------------+

+; BIT_SZ         ; 14    ; Signed Integer                 ;

+; IDLE           ; 00    ; Unsigned Binary                ;

+; COUNTING       ; 01    ; Unsigned Binary                ;

+; TIME_OUT       ; 10    ; Unsigned Binary                ;

+; WAIT_LOW       ; 11    ; Unsigned Binary                ;

++----------------+-------+--------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++-----------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+; Port  ; Type   ; Severity ; Details                                                                             ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;

+; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+

+

++---------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;

++-------+-------+----------+------------------------------+

+; Port  ; Type  ; Severity ; Details                      ;

++-------+-------+----------+------------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                 ;

++-------+-------+----------+------------------------------+

+

+

++---------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;

++-------+-------+----------+------------------------------+

+; Port  ; Type  ; Severity ; Details                      ;

++-------+-------+----------+------------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                 ;

++-------+-------+----------+------------------------------+

+

+

++--------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;

++-------+-------+----------+-----------------------------+

+; Port  ; Type  ; Severity ; Details                     ;

++-------+-------+----------+-----------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                ;

++-------+-------+----------+-----------------------------+

+

+

++--------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;

++-------+-------+----------+-----------------------------+

+; Port  ; Type  ; Severity ; Details                     ;

++-------+-------+----------+-----------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                ;

++-------+-------+----------+-----------------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD"                                                                                                                              ;

++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; Port  ; Type   ; Severity ; Details                                                                                                                                     ;

++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; B     ; Input  ; Warning  ; Input port expression (7 bits) is smaller than the input port (16 bits) it drives.  Extra input bit(s) "B[15..7]" will be connected to GND. ;

+; BCD_3 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                         ;

+; BCD_4 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                         ;

++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; Port ; Type  ; Severity ; Details                                                                                                                                     ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------+

+; Post-Synthesis Netlist Statistics for Top Partition ;

++-----------------------+-----------------------------+

+; Type                  ; Count                       ;

++-----------------------+-----------------------------+

+; arriav_ff             ; 68                          ;

+;     ENA               ; 18                          ;

+;     ENA SLD           ; 14                          ;

+;     SLD               ; 1                           ;

+;     plain             ; 35                          ;

+; arriav_lcell_comb     ; 143                         ;

+;     arith             ; 42                          ;

+;         1 data inputs ; 42                          ;

+;     normal            ; 101                         ;

+;         0 data inputs ; 2                           ;

+;         1 data inputs ; 20                          ;

+;         2 data inputs ; 6                           ;

+;         3 data inputs ; 15                          ;

+;         4 data inputs ; 33                          ;

+;         5 data inputs ; 14                          ;

+;         6 data inputs ; 11                          ;

+; boundary_port         ; 36                          ;

+;                       ;                             ;

+; Max LUT depth         ; 6.00                        ;

+; Average LUT depth     ; 2.91                        ;

++-----------------------+-----------------------------+

+

+

++-------------------------------+

+; Elapsed Time Per Partition    ;

++----------------+--------------+

+; Partition Name ; Elapsed Time ;

++----------------+--------------+

+; Top            ; 00:00:00     ;

++----------------+--------------+

+

+

++-------------------------------+

+; Analysis & Synthesis Messages ;

++-------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Analysis & Synthesis

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 10:20:29 2016

+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v

+    Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex8/verilog_files/tick_50000.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v

+    Info (12023): Found entity 1: LFSR File: C:/New folder/ex8/verilog_files/LFSR.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v

+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex8/verilog_files/hex_to_7seg.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v

+    Info (12023): Found entity 1: counter_16 File: C:/New folder/ex8/verilog_files/counter_16.v Line: 3

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v

+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 12

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v

+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex8/verilog_files/add3_ge5.v Line: 9

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v

+    Info (12023): Found entity 1: formula_fsm File: C:/New folder/ex8/verilog_files/formula_fsm.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v

+    Info (12023): Found entity 1: delay File: C:/New folder/ex8/verilog_files/delay.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v

+    Info (12023): Found entity 1: tick_2500 File: C:/New folder/ex8/verilog_files/tick_2500.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex8.v

+    Info (12023): Found entity 1: ex8 File: C:/New folder/ex8/verilog_files/ex8.v Line: 1

+Info (12127): Elaborating entity "ex8" for the top level hierarchy

+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: C:/New folder/ex8/verilog_files/ex8.v Line: 13

+Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: C:/New folder/ex8/verilog_files/ex8.v Line: 14

+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: C:/New folder/ex8/verilog_files/ex8.v Line: 15

+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot File: C:/New folder/ex8/verilog_files/formula_fsm.v Line: 37

+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: C:/New folder/ex8/verilog_files/formula_fsm.v Line: 47

+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(47) File: C:/New folder/ex8/verilog_files/formula_fsm.v Line: 47

+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: C:/New folder/ex8/verilog_files/ex8.v Line: 16

+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: C:/New folder/ex8/verilog_files/ex8.v Line: 17

+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: C:/New folder/ex8/verilog_files/delay.v Line: 24

+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: C:/New folder/ex8/verilog_files/ex8.v Line: 18

+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 26

+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex8/verilog_files/ex8.v Line: 19

+Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder

+Warning (13024): Output pins are stuck at VCC or GND

+    Warning (13410): Pin "HEX2[1]" is stuck at GND File: C:/New folder/ex8/verilog_files/ex8.v Line: 6

+    Warning (13410): Pin "HEX2[2]" is stuck at GND File: C:/New folder/ex8/verilog_files/ex8.v Line: 6

+    Warning (13410): Pin "HEX2[6]" is stuck at VCC File: C:/New folder/ex8/verilog_files/ex8.v Line: 6

+Info (286030): Timing-Driven Synthesis is running

+Info (17049): 2 registers lost all their fanouts during netlist optimizations.

+Info (144001): Generated suppressed messages file C:/New folder/ex8/output_files/ex8.map.smsg

+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

+Warning (21074): Design contains 3 input pin(s) that do not drive logic

+    Warning (15610): No output dependent on input pin "KEY[0]" File: C:/New folder/ex8/verilog_files/ex8.v Line: 4

+    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/New folder/ex8/verilog_files/ex8.v Line: 4

+    Warning (15610): No output dependent on input pin "KEY[2]" File: C:/New folder/ex8/verilog_files/ex8.v Line: 4

+Info (21057): Implemented 183 device resources after synthesis - the final resource count might be different

+    Info (21058): Implemented 5 input pins

+    Info (21059): Implemented 31 output pins

+    Info (21061): Implemented 147 logic cells

+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings

+    Info: Peak virtual memory: 916 megabytes

+    Info: Processing ended: Fri Nov 25 10:20:39 2016

+    Info: Elapsed time: 00:00:10

+    Info: Total CPU time (on all processors): 00:00:22

+

+

++------------------------------------------+

+; Analysis & Synthesis Suppressed Messages ;

++------------------------------------------+

+The suppressed messages can be found in C:/New folder/ex8/output_files/ex8.map.smsg.

+

+

diff --git a/part_2/ex8/output_files/ex8.map.smsg b/part_2/ex8/output_files/ex8.map.smsg
new file mode 100755
index 0000000..3f8ada0
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.map.smsg
@@ -0,0 +1,37 @@
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex8/verilog_files/bin2bcd_16.v Line: 22

+Warning (10268): Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex8/verilog_files/formula_fsm.v Line: 36

+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: C:/New folder/ex8/verilog_files/delay.v Line: 7

diff --git a/part_2/ex8/output_files/ex8.map.summary b/part_2/ex8/output_files/ex8.map.summary
new file mode 100755
index 0000000..2f84f3d
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Fri Nov 25 10:20:39 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex8

+Top-level Entity Name : ex8

+Family : Cyclone V

+Logic utilization (in ALMs) : N/A

+Total registers : 68

+Total pins : 36

+Total virtual pins : 0

+Total block memory bits : 0

+Total DSP Blocks : 0

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0

+Total DLLs : 0

diff --git a/part_2/ex8/output_files/ex8.pin b/part_2/ex8/output_files/ex8.pin
new file mode 100755
index 0000000..7f57443
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+ -- Your use of Altera Corporation's design tools, logic functions 

+ -- and other software and tools, and its AMPP partner logic 

+ -- functions, and any output files from any of the foregoing 

+ -- (including device programming or simulation files), and any 

+ -- associated documentation or information are expressly subject 

+ -- to the terms and conditions of the Altera Program License 

+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,

+ -- the Altera MegaCore Function License Agreement, or other 

+ -- applicable license agreement, including, without limitation, 

+ -- that your use is for the sole purpose of programming logic 

+ -- devices manufactured by Altera and sold by Altera or its 

+ -- authorized distributors.  Please refer to the applicable 

+ -- agreement for further details.

+ -- 

+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is

+ -- not intended for use as a Quartus Prime input file. This file cannot be used

+ -- to make Quartus Prime pin assignments - for instructions on how to make pin

+ -- assignments, please see Quartus Prime help.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- NC            : No Connect. This pin has no internal connection to the device.

+ -- DNU           : Do Not Use. This pin MUST NOT be connected.

+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.

+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).

+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC

+ --                 of its bank.

+ --                  Bank 3A:       2.5V

+ --                  Bank 3B:       3.3V

+ --                  Bank 4A:       3.3V

+ --                  Bank 5A:       3.3V

+ --                  Bank 5B:       3.3V

+ --                  Bank 6B:       2.5V

+ --                  Bank 6A:  2.5V

+ --                  Bank 7A:  2.5V

+ --                  Bank 7B:  2.5V

+ --                  Bank 7C:  2.5V

+ --                  Bank 7D:  2.5V

+ --                  Bank 8A:  2.5V

+ -- RREF          : External reference resistor for the quad, MUST be connected to

+ --                 GND via a 2k Ohm resistor.

+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.

+ --                  It can also be used to report unused dedicated pins. The connection

+ --                  on the board for unused dedicated pins depends on whether this will

+ --                  be used in a future design. One example is device migration. When

+ --                  using device migration, refer to the device pin-tables. If it is a

+ --                  GND pin in the pin table or if it will not be used in a future design

+ --                  for another purpose the it MUST be connected to GND. If it is an unused

+ --                  dedicated pin, then it can be connected to a valid signal on the board

+ --                  (low, high, or toggling) if that signal is required for a different

+ --                  revision of the design.

+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.

+ --                  This pin should be connected to GND. It may also be connected  to a

+ --                  valid signal  on the board  (low, high, or toggling)  if that signal

+ --                  is required for a different revision of the design.

+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND

+ --                  or leave it unconnected.

+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.

+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.

+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.

+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.

+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.

+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin

+ --                 must not be connected.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- Pin directions (input, output or bidir) are based on device operating in user mode.

+ ---------------------------------------------------------------------------------

+

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+CHIP  "ex8"  ASSIGNED TO AN: 5CSEMA5F31C6

+

+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

+-------------------------------------------------------------------------------------------------------------

+GND                          : A2        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                

+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                

+GND                          : A12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                

+GND                          : A17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                

+GND                          : A22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                

+GND                          : A26       :        :                   :         : 7A        :                

+GND                          : A27       : gnd    :                   :         :           :                

+HPS_TRST                     : A28       :        :                   :         : 7A        :                

+HPS_TMS                      : A29       :        :                   :         : 7A        :                

+GND                          : AA1       : gnd    :                   :         :           :                

+GND                          : AA2       : gnd    :                   :         :           :                

+GND                          : AA3       : gnd    :                   :         :           :                

+GND                          : AA4       : gnd    :                   :         :           :                

+VCC                          : AA5       : power  :                   : 1.1V    :           :                

+GND                          : AA6       : gnd    :                   :         :           :                

+DNU                          : AA7       :        :                   :         :           :                

+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                

+GND                          : AA9       : gnd    :                   :         :           :                

+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                

+GND                          : AA11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                

+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                

+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                

+GND                          : AA22      : gnd    :                   :         :           :                

+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                

+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                

+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                

+GND                          : AB1       : gnd    :                   :         :           :                

+GND                          : AB2       : gnd    :                   :         :           :                

+DNU                          : AB3       :        :                   :         :           :                

+DNU                          : AB4       :        :                   :         :           :                

+GND                          : AB5       : gnd    :                   :         :           :                

+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                

+GND                          : AB7       : gnd    :                   :         :           :                

+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                

+TDO                          : AB9       : output :                   :         : 3A        :                

+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                

+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                

+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AB19      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                

+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                

+GND                          : AB29      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                

+GND                          : AC1       : gnd    :                   :         :           :                

+GND                          : AC2       : gnd    :                   :         :           :                

+GND                          : AC3       : gnd    :                   :         :           :                

+GND                          : AC4       : gnd    :                   :         :           :                

+TCK                          : AC5       : input  :                   :         : 3A        :                

+GND                          : AC6       : gnd    :                   :         :           :                

+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                

+GND                          : AC8       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                

+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                

+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                

+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                

+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AC16      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                

+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                

+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                

+GND                          : AC26      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                

+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AD1       : gnd    :                   :         :           :                

+GND                          : AD2       : gnd    :                   :         :           :                

+DNU                          : AD3       :        :                   :         :           :                

+DNU                          : AD4       :        :                   :         :           :                

+GND                          : AD5       : gnd    :                   :         :           :                

+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                

+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                

+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                

+DNU                          : AD15      :        :                   :         :           :                

+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                

+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                

+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                

+GND                          : AD23      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                

+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                

+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AE1       : gnd    :                   :         :           :                

+GND                          : AE2       : gnd    :                   :         :           :                

+GND                          : AE3       : gnd    :                   :         :           :                

+GND                          : AE4       : gnd    :                   :         :           :                

+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                

+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                

+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                

+GND                          : AE10      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                

+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                

+GND                          : AE20      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                

+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                

+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                

+GND                          : AF1       : gnd    :                   :         :           :                

+GND                          : AF2       : gnd    :                   :         :           :                

+GND                          : AF3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                

+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                

+GND                          : AF12      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                

+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                

+GND                          : AF17      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                

+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                

+GND                          : AF27      : gnd    :                   :         :           :                

+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                

+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                

+GND                          : AG9       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                

+GND                          : AG14      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                

+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                

+GND                          : AG24      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                

+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                

+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AH1       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                

+GND                          : AH6       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                

+GND                          : AH11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                

+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                

+GND                          : AH21      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                

+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                

+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                

+GND                          : AJ3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                

+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                

+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                

+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                

+GND                          : AJ18      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                

+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                

+GND                          : AJ28      : gnd    :                   :         :           :                

+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AJ30      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                

+GND                          : AK5       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                

+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                

+GND                          : AK15      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                

+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                

+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                

+GND                          : AK25      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                

+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                

+GND                          : B9        : gnd    :                   :         :           :                

+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                

+GND                          : B14       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                

+GND                          : B19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                

+GND                          : B24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                

+HPS_TDI                      : B27       :        :                   :         : 7A        :                

+HPS_TDO                      : B28       :        :                   :         : 7A        :                

+GND                          : B29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                

+GND                          : C1        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                

+GND                          : C6        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                

+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                

+GND                          : C16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                

+GND                          : C21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                

+GND                          : C26       : gnd    :                   :         :           :                

+HPS_nRST                     : C27       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                

+GND                          : D3        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                

+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                

+GND                          : D13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                

+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                

+GND                          : D23       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                

+HPS_CLK1                     : D25       :        :                   :         : 7A        :                

+GND                          : D26       :        :                   :         : 7A        :                

+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                

+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                

+GND                          : E10       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                

+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                

+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                

+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                

+GND                          : E25       : gnd    :                   :         :           :                

+DNU                          : E26       :        :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                

+GND                          : E30       : gnd    :                   :         :           :                

+DNU                          : F1        :        :                   :         :           :                

+GND                          : F2        : gnd    :                   :         :           :                

+CONF_DONE                    : F3        :        :                   :         : 9A        :                

+nSTATUS                      : F4        :        :                   :         : 9A        :                

+GND                          : F5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                

+GND                          : F7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                

+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                

+GND                          : F17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                

+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                

+HPS_nPOR                     : F23       :        :                   :         : 7A        :                

+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                

+HPS_CLK2                     : F25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                

+GND                          : F27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                

+GND                          : G1        :        :                   :         :           :                

+DNU                          : G2        :        :                   :         :           :                

+GND                          : G3        : gnd    :                   :         :           :                

+GND                          : G4        : gnd    :                   :         :           :                

+nCE                          : G5        :        :                   :         : 9A        :                

+MSEL2                        : G6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                

+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                

+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                

+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                

+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                

+GND                          : G24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                

+GND                          : H1        : gnd    :                   :         :           :                

+GND                          : H2        : gnd    :                   :         :           :                

+DNU                          : H3        :        :                   :         :           :                

+DNU                          : H4        :        :                   :         :           :                

+GND                          : H5        : gnd    :                   :         :           :                

+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                

+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                

+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                

+GND                          : H11       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                

+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                

+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                

+HPS_TCK                      : H22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                

+GND                          : J1        : gnd    :                   :         :           :                

+GND                          : J2        : gnd    :                   :         :           :                

+GND                          : J3        : gnd    :                   :         :           :                

+GND                          : J4        : gnd    :                   :         :           :                

+nCONFIG                      : J5        :        :                   :         : 9A        :                

+GND                          : J6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                

+GND                          : J8        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                

+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                

+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                

+DNU                          : J15       :        :                   :         :           :                

+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                

+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                

+GND                          : J18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                

+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                

+GND                          : J22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                

+GND                          : J28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                

+GND                          : K1        : gnd    :                   :         :           :                

+GND                          : K2        : gnd    :                   :         :           :                

+DNU                          : K3        :        :                   :         :           :                

+DNU                          : K4        :        :                   :         :           :                

+GND                          : K5        : gnd    :                   :         :           :                

+MSEL1                        : K6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                

+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                

+GND                          : K10       : gnd    :                   :         :           :                

+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                

+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                

+GND                          : K15       : gnd    :                   :         :           :                

+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                

+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                

+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                

+GND                          : K20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                

+GND                          : K25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                

+GND                          : L1        : gnd    :                   :         :           :                

+GND                          : L2        : gnd    :                   :         :           :                

+GND                          : L3        : gnd    :                   :         :           :                

+GND                          : L4        : gnd    :                   :         :           :                

+VCC                          : L5        : power  :                   : 1.1V    :           :                

+GND                          : L6        : gnd    :                   :         :           :                

+MSEL3                        : L7        :        :                   :         : 9A        :                

+MSEL0                        : L8        :        :                   :         : 9A        :                

+MSEL4                        : L9        :        :                   :         : 9A        :                

+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                

+GND                          : L11       : gnd    :                   :         :           :                

+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                

+GND                          : L13       : gnd    :                   :         :           :                

+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                

+GND                          : L15       : gnd    :                   :         :           :                

+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                

+GND                          : L17       : gnd    :                   :         :           :                

+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                

+GND                          : L19       : gnd    :                   :         :           :                

+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                

+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                

+GND                          : L22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                

+GND                          : M1        : gnd    :                   :         :           :                

+GND                          : M2        : gnd    :                   :         :           :                

+DNU                          : M3        :        :                   :         :           :                

+DNU                          : M4        :        :                   :         :           :                

+GND                          : M5        : gnd    :                   :         :           :                

+VCC                          : M6        : power  :                   : 1.1V    :           :                

+GND                          : M7        : gnd    :                   :         :           :                

+GND                          : M8        : gnd    :                   :         :           :                

+VCC                          : M9        : power  :                   : 1.1V    :           :                

+GND                          : M10       : gnd    :                   :         :           :                

+VCC                          : M11       : power  :                   : 1.1V    :           :                

+GND                          : M12       : gnd    :                   :         :           :                

+VCC                          : M13       : power  :                   : 1.1V    :           :                

+GND                          : M14       : gnd    :                   :         :           :                

+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                

+GND                          : M16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                

+GND                          : M18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                

+GND                          : M20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                

+GND                          : M29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                

+GND                          : N1        : gnd    :                   :         :           :                

+GND                          : N2        : gnd    :                   :         :           :                

+GND                          : N3        : gnd    :                   :         :           :                

+GND                          : N4        : gnd    :                   :         :           :                

+VCC                          : N5        : power  :                   : 1.1V    :           :                

+GND                          : N6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                

+GND                          : N8        : gnd    :                   :         :           :                

+GND                          : N9        : gnd    :                   :         :           :                

+VCC                          : N10       : power  :                   : 1.1V    :           :                

+GND                          : N11       : gnd    :                   :         :           :                

+VCC                          : N12       : power  :                   : 1.1V    :           :                

+GND                          : N13       : gnd    :                   :         :           :                

+VCC                          : N14       : power  :                   : 1.1V    :           :                

+GND                          : N15       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                

+GND                          : N17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                

+GND                          : N19       : gnd    :                   :         :           :                

+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                

+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                

+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                

+GND                          : N26       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                

+GND                          : P1        : gnd    :                   :         :           :                

+GND                          : P2        : gnd    :                   :         :           :                

+DNU                          : P3        :        :                   :         :           :                

+DNU                          : P4        :        :                   :         :           :                

+GND                          : P5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                

+GND                          : P7        : gnd    :                   :         :           :                

+GND                          : P8        : gnd    :                   :         :           :                

+GND                          : P9        : gnd    :                   :         :           :                

+GND                          : P10       : gnd    :                   :         :           :                

+VCC                          : P11       : power  :                   : 1.1V    :           :                

+GND                          : P12       : gnd    :                   :         :           :                

+VCC                          : P13       : power  :                   : 1.1V    :           :                

+GND                          : P14       : gnd    :                   :         :           :                

+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                

+GND                          : P16       : gnd    :                   :         :           :                

+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                

+GND                          : P18       : gnd    :                   :         :           :                

+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                

+GND                          : P20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                

+GND                          : R1        : gnd    :                   :         :           :                

+GND                          : R2        : gnd    :                   :         :           :                

+GND                          : R3        : gnd    :                   :         :           :                

+GND                          : R4        : gnd    :                   :         :           :                

+VCC                          : R5        : power  :                   : 1.1V    :           :                

+GND                          : R6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                

+GND                          : R8        : gnd    :                   :         :           :                

+GND                          : R9        : gnd    :                   :         :           :                

+VCC                          : R10       : power  :                   : 1.1V    :           :                

+GND                          : R11       : gnd    :                   :         :           :                

+VCC                          : R12       : power  :                   : 1.1V    :           :                

+GND                          : R13       : gnd    :                   :         :           :                

+VCC                          : R14       : power  :                   : 1.1V    :           :                

+GND                          : R15       : gnd    :                   :         :           :                

+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                

+GND                          : R17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                

+GND                          : R30       : gnd    :                   :         :           :                

+GND                          : T1        : gnd    :                   :         :           :                

+GND                          : T2        : gnd    :                   :         :           :                

+DNU                          : T3        :        :                   :         :           :                

+DNU                          : T4        :        :                   :         :           :                

+GND                          : T5        : gnd    :                   :         :           :                

+VCC                          : T6        : power  :                   : 1.1V    :           :                

+GND                          : T7        : gnd    :                   :         :           :                

+GND                          : T8        : gnd    :                   :         :           :                

+GND                          : T9        : gnd    :                   :         :           :                

+GND                          : T10       : gnd    :                   :         :           :                

+VCC                          : T11       : power  :                   : 1.1V    :           :                

+GND                          : T12       : gnd    :                   :         :           :                

+VCC                          : T13       : power  :                   : 1.1V    :           :                

+GND                          : T14       : gnd    :                   :         :           :                

+GND                          : T15       : gnd    :                   :         :           :                

+GND                          : T16       : gnd    :                   :         :           :                

+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                

+GND                          : T18       : gnd    :                   :         :           :                

+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                

+GND                          : T20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                

+GND                          : T27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                

+GND                          : U1        : gnd    :                   :         :           :                

+GND                          : U2        : gnd    :                   :         :           :                

+GND                          : U3        : gnd    :                   :         :           :                

+GND                          : U4        : gnd    :                   :         :           :                

+VCC                          : U5        : power  :                   : 1.1V    :           :                

+GND                          : U6        : gnd    :                   :         :           :                

+DCLK                         : U7        :        :                   :         : 3A        :                

+TDI                          : U8        : input  :                   :         : 3A        :                

+GND                          : U9        : gnd    :                   :         :           :                

+VCC                          : U10       : power  :                   : 1.1V    :           :                

+GND                          : U11       : gnd    :                   :         :           :                

+VCC                          : U12       : power  :                   : 1.1V    :           :                

+GND                          : U13       : gnd    :                   :         :           :                

+VCC                          : U14       : power  :                   : 1.1V    :           :                

+GND                          : U15       : gnd    :                   :         :           :                

+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                

+GND                          : U17       : gnd    :                   :         :           :                

+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                

+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                

+VCC                          : U21       : power  :                   : 1.1V    :           :                

+GND                          : U22       : gnd    :                   :         :           :                

+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                

+GND                          : U24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                

+GND                          : U29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                

+GND                          : V1        : gnd    :                   :         :           :                

+GND                          : V2        : gnd    :                   :         :           :                

+DNU                          : V3        :        :                   :         :           :                

+DNU                          : V4        :        :                   :         :           :                

+GND                          : V5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                

+GND                          : V7        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                

+TMS                          : V9        : input  :                   :         : 3A        :                

+GND                          : V10       : gnd    :                   :         :           :                

+VCC                          : V11       : power  :                   : 1.1V    :           :                

+GND                          : V12       : gnd    :                   :         :           :                

+VCC                          : V13       : power  :                   : 1.1V    :           :                

+GND                          : V14       : gnd    :                   :         :           :                

+VCC                          : V15       : power  :                   : 1.1V    :           :                

+LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : V19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                

+GND                          : V21       : gnd    :                   :         :           :                

+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                

+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                

+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                

+GND                          : W1        : gnd    :                   :         :           :                

+GND                          : W2        : gnd    :                   :         :           :                

+GND                          : W3        : gnd    :                   :         :           :                

+GND                          : W4        : gnd    :                   :         :           :                

+VCC                          : W5        : power  :                   : 1.1V    :           :                

+GND                          : W6        : gnd    :                   :         :           :                

+GND                          : W7        : gnd    :                   :         :           :                

+GND                          : W8        : gnd    :                   :         :           :                

+GND                          : W9        : gnd    :                   :         :           :                

+VCC                          : W10       : power  :                   : 1.1V    :           :                

+GND                          : W11       : gnd    :                   :         :           :                

+VCC                          : W12       : power  :                   : 1.1V    :           :                

+GND                          : W13       : gnd    :                   :         :           :                

+VCC                          : W14       : power  :                   : 1.1V    :           :                

+KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              

+LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : W18       : gnd    :                   :         :           :                

+LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              

+LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                

+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                

+GND                          : W28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                

+GND                          : Y1        : gnd    :                   :         :           :                

+GND                          : Y2        : gnd    :                   :         :           :                

+DNU                          : Y3        :        :                   :         :           :                

+DNU                          : Y4        :        :                   :         :           :                

+GND                          : Y5        : gnd    :                   :         :           :                

+VCC                          : Y6        : power  :                   : 1.1V    :           :                

+GND                          : Y7        : gnd    :                   :         :           :                

+GND                          : Y8        : gnd    :                   :         :           :                

+VCC                          : Y9        : power  :                   : 1.1V    :           :                

+GND                          : Y10       : gnd    :                   :         :           :                

+VCC                          : Y11       : power  :                   : 1.1V    :           :                

+GND                          : Y12       : gnd    :                   :         :           :                

+VCC                          : Y13       : power  :                   : 1.1V    :           :                

+GND                          : Y14       : gnd    :                   :         :           :                

+GND                          : Y15       : gnd    :                   :         :           :                

+KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                

+LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : Y20       : gnd    :                   :         :           :                

+LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                

+GND                          : Y25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                

+GND                          : Y30       : gnd    :                   :         :           :                

diff --git a/part_2/ex8/output_files/ex8.sld b/part_2/ex8/output_files/ex8.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.sld
@@ -0,0 +1 @@
+<sld_project_info/>

diff --git a/part_2/ex8/output_files/ex8.sof b/part_2/ex8/output_files/ex8.sof
new file mode 100755
index 0000000..86b455f
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.sof
diff --git a/part_2/ex8/output_files/ex8.sta.rpt b/part_2/ex8/output_files/ex8.sta.rpt
new file mode 100755
index 0000000..d2fa247
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.sta.rpt
@@ -0,0 +1,905 @@
+TimeQuest Timing Analyzer report for ex8

+Fri Nov 25 10:21:27 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. TimeQuest Timing Analyzer Summary

+  3. Parallel Compilation

+  4. Clocks

+  5. Slow 1100mV 85C Model Fmax Summary

+  6. Timing Closure Recommendations

+  7. Slow 1100mV 85C Model Setup Summary

+  8. Slow 1100mV 85C Model Hold Summary

+  9. Slow 1100mV 85C Model Recovery Summary

+ 10. Slow 1100mV 85C Model Removal Summary

+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary

+ 12. Slow 1100mV 85C Model Metastability Summary

+ 13. Slow 1100mV 0C Model Fmax Summary

+ 14. Slow 1100mV 0C Model Setup Summary

+ 15. Slow 1100mV 0C Model Hold Summary

+ 16. Slow 1100mV 0C Model Recovery Summary

+ 17. Slow 1100mV 0C Model Removal Summary

+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary

+ 19. Slow 1100mV 0C Model Metastability Summary

+ 20. Fast 1100mV 85C Model Setup Summary

+ 21. Fast 1100mV 85C Model Hold Summary

+ 22. Fast 1100mV 85C Model Recovery Summary

+ 23. Fast 1100mV 85C Model Removal Summary

+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary

+ 25. Fast 1100mV 85C Model Metastability Summary

+ 26. Fast 1100mV 0C Model Setup Summary

+ 27. Fast 1100mV 0C Model Hold Summary

+ 28. Fast 1100mV 0C Model Recovery Summary

+ 29. Fast 1100mV 0C Model Removal Summary

+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary

+ 31. Fast 1100mV 0C Model Metastability Summary

+ 32. Multicorner Timing Analysis Summary

+ 33. Board Trace Model Assignments

+ 34. Input Transition Times

+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)

+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)

+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)

+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)

+ 39. Setup Transfers

+ 40. Hold Transfers

+ 41. Report TCCS

+ 42. Report RSKM

+ 43. Unconstrained Paths Summary

+ 44. Clock Status Summary

+ 45. Unconstrained Input Ports

+ 46. Unconstrained Output Ports

+ 47. Unconstrained Input Ports

+ 48. Unconstrained Output Ports

+ 49. TimeQuest Timing Analyzer Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------------------------+

+; TimeQuest Timing Analyzer Summary                                               ;

++-----------------------+---------------------------------------------------------+

+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Timing Analyzer       ; TimeQuest                                               ;

+; Revision Name         ; ex8                                                     ;

+; Device Family         ; Cyclone V                                               ;

+; Device Name           ; 5CSEMA5F31C6                                            ;

+; Timing Models         ; Final                                                   ;

+; Delay Model           ; Combined                                                ;

+; Rise/Fall Delays      ; Enabled                                                 ;

++-----------------------+---------------------------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.11        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   3.6%      ;

+;     Processor 3            ;   3.5%      ;

+;     Processor 4            ;   3.4%      ;

++----------------------------+-------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Clocks                                                                                                                                                                                                                                   ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;

+; tick_2500:TICK1|CLK_OUT             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_2500:TICK1|CLK_OUT }             ;

+; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+

+

++----------------------------------------------------------------+

+; Slow 1100mV 85C Model Fmax Summary                             ;

++------------+-----------------+--------------------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;

++------------+-----------------+--------------------------+------+

+; 273.97 MHz ; 273.97 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;

+; 284.25 MHz ; 284.25 MHz      ; CLOCK_50                 ;      ;

+; 469.04 MHz ; 469.04 MHz      ; tick_2500:TICK1|CLK_OUT  ;      ;

++------------+-----------------+--------------------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

+----------------------------------

+; Timing Closure Recommendations ;

+----------------------------------

+HTML report is unavailable in plain text report export.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 85C Model Setup Summary                          ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -4.828 ; -90.826       ;

+; tick_50000:TICK0|CLK_OUT            ; -2.650 ; -63.464       ;

+; tick_2500:TICK1|CLK_OUT             ; -2.004 ; -18.612       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.489 ; -1.489        ;

++-------------------------------------+--------+---------------+

+

+

++-------------------------------------------------------------+

+; Slow 1100mV 85C Model Hold Summary                          ;

++-------------------------------------+-------+---------------+

+; Clock                               ; Slack ; End Point TNS ;

++-------------------------------------+-------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; 0.283 ; 0.000         ;

+; CLOCK_50                            ; 0.376 ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.424 ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.523 ; 0.000         ;

++-------------------------------------+-------+---------------+

+

+

+------------------------------------------

+; Slow 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Slow 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.636 ; -25.765       ;

+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -14.976       ;

+; tick_2500:TICK1|CLK_OUT             ; -0.394 ; -5.130        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.404  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------------

+; Slow 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++----------------------------------------------------------------+

+; Slow 1100mV 0C Model Fmax Summary                              ;

++------------+-----------------+--------------------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;

++------------+-----------------+--------------------------+------+

+; 276.01 MHz ; 276.01 MHz      ; CLOCK_50                 ;      ;

+; 277.55 MHz ; 277.55 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;

+; 483.56 MHz ; 483.56 MHz      ; tick_2500:TICK1|CLK_OUT  ;      ;

++------------+-----------------+--------------------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 0C Model Setup Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -4.731 ; -86.467       ;

+; tick_50000:TICK0|CLK_OUT            ; -2.603 ; -61.065       ;

+; tick_2500:TICK1|CLK_OUT             ; -1.916 ; -17.960       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.373 ; -1.373        ;

++-------------------------------------+--------+---------------+

+

+

++-------------------------------------------------------------+

+; Slow 1100mV 0C Model Hold Summary                           ;

++-------------------------------------+-------+---------------+

+; Clock                               ; Slack ; End Point TNS ;

++-------------------------------------+-------+---------------+

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.283 ; 0.000         ;

+; tick_50000:TICK0|CLK_OUT            ; 0.287 ; 0.000         ;

+; CLOCK_50                            ; 0.389 ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.530 ; 0.000         ;

++-------------------------------------+-------+---------------+

+

+

+-----------------------------------------

+; Slow 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Slow 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.690 ; -23.719       ;

+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -14.868       ;

+; tick_2500:TICK1|CLK_OUT             ; -0.394 ; -5.140        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.384  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+----------------------------------------------

+; Slow 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Setup Summary                          ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -4.046 ; -58.106       ;

+; tick_2500:TICK1|CLK_OUT             ; -1.373 ; -12.517       ;

+; tick_50000:TICK0|CLK_OUT            ; -1.359 ; -32.665       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.480 ; -0.480        ;

++-------------------------------------+--------+---------------+

+

+

++-------------------------------------------------------------+

+; Fast 1100mV 85C Model Hold Summary                          ;

++-------------------------------------+-------+---------------+

+; Clock                               ; Slack ; End Point TNS ;

++-------------------------------------+-------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; 0.023 ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.061 ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.092 ; 0.000         ;

+; CLOCK_50                            ; 0.182 ; 0.000         ;

++-------------------------------------+-------+---------------+

+

+

+------------------------------------------

+; Fast 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Fast 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.760 ; -18.549       ;

+; tick_50000:TICK0|CLK_OUT            ; 0.049  ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.131  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.469  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------------

+; Fast 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Setup Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -3.445 ; -47.547       ;

+; tick_2500:TICK1|CLK_OUT             ; -1.171 ; -10.740       ;

+; tick_50000:TICK0|CLK_OUT            ; -1.164 ; -27.696       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.362 ; -0.362        ;

++-------------------------------------+--------+---------------+

+

+

++-------------------------------------------------------------+

+; Fast 1100mV 0C Model Hold Summary                           ;

++-------------------------------------+-------+---------------+

+; Clock                               ; Slack ; End Point TNS ;

++-------------------------------------+-------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; 0.013 ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.014 ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.024 ; 0.000         ;

+; CLOCK_50                            ; 0.172 ; 0.000         ;

++-------------------------------------+-------+---------------+

+

+

+-----------------------------------------

+; Fast 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Fast 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.812 ; -22.016       ;

+; tick_50000:TICK0|CLK_OUT            ; 0.076  ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.135  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.465  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+----------------------------------------------

+; Fast 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++----------------------------------------------------------------------------------------------------+

+; Multicorner Timing Analysis Summary                                                                ;

++--------------------------------------+----------+-------+----------+---------+---------------------+

+; Clock                                ; Setup    ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;

++--------------------------------------+----------+-------+----------+---------+---------------------+

+; Worst-case Slack                     ; -4.828   ; 0.013 ; N/A      ; N/A     ; -0.812              ;

+;  CLOCK_50                            ; -4.828   ; 0.172 ; N/A      ; N/A     ; -0.812              ;

+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.489   ; 0.014 ; N/A      ; N/A     ; 0.384               ;

+;  tick_2500:TICK1|CLK_OUT             ; -2.004   ; 0.024 ; N/A      ; N/A     ; -0.394              ;

+;  tick_50000:TICK0|CLK_OUT            ; -2.650   ; 0.013 ; N/A      ; N/A     ; -0.394              ;

+; Design-wide TNS                      ; -174.391 ; 0.0   ; 0.0      ; 0.0     ; -45.871             ;

+;  CLOCK_50                            ; -90.826  ; 0.000 ; N/A      ; N/A     ; -25.765             ;

+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.489   ; 0.000 ; N/A      ; N/A     ; 0.000               ;

+;  tick_2500:TICK1|CLK_OUT             ; -18.612  ; 0.000 ; N/A      ; N/A     ; -5.140              ;

+;  tick_50000:TICK0|CLK_OUT            ; -63.464  ; 0.000 ; N/A      ; N/A     ; -14.976             ;

++--------------------------------------+----------+-------+----------+---------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+

+

++-------------------------------------------------------------+

+; Input Transition Times                                      ;

++----------+--------------+-----------------+-----------------+

+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;

++----------+--------------+-----------------+-----------------+

+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

++----------+--------------+-----------------+-----------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------+

+; Setup Transfers                                                                                                       ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; CLOCK_50                            ; CLOCK_50                            ; 548      ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; CLOCK_50                            ; 13       ; 13       ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_2500:TICK1|CLK_OUT             ; 9        ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; 9        ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_2500:TICK1|CLK_OUT             ; 10       ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 26       ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_50000:TICK0|CLK_OUT            ; 20       ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 419      ; 0        ; 0        ; 0        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

++-----------------------------------------------------------------------------------------------------------------------+

+; Hold Transfers                                                                                                        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; CLOCK_50                            ; CLOCK_50                            ; 548      ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; CLOCK_50                            ; 13       ; 13       ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_2500:TICK1|CLK_OUT             ; 9        ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; 9        ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_2500:TICK1|CLK_OUT             ; 10       ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 26       ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_50000:TICK0|CLK_OUT            ; 20       ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 419      ; 0        ; 0        ; 0        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

+---------------

+; Report TCCS ;

+---------------

+No dedicated SERDES Transmitter circuitry present in device or used in design

+

+

+---------------

+; Report RSKM ;

+---------------

+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design

+

+

++------------------------------------------------+

+; Unconstrained Paths Summary                    ;

++---------------------------------+-------+------+

+; Property                        ; Setup ; Hold ;

++---------------------------------+-------+------+

+; Illegal Clocks                  ; 0     ; 0    ;

+; Unconstrained Clocks            ; 0     ; 0    ;

+; Unconstrained Input Ports       ; 1     ; 1    ;

+; Unconstrained Input Port Paths  ; 3     ; 3    ;

+; Unconstrained Output Ports      ; 28    ; 28   ;

+; Unconstrained Output Port Paths ; 121   ; 121  ;

++---------------------------------+-------+------+

+

+

++------------------------------------------------------------------------------------------------+

+; Clock Status Summary                                                                           ;

++-------------------------------------+-------------------------------------+------+-------------+

+; Target                              ; Clock                               ; Type ; Status      ;

++-------------------------------------+-------------------------------------+------+-------------+

+; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;

+; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; Base ; Constrained ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;

++-------------------------------------+-------------------------------------+------+-------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++------------------------------------+

+; TimeQuest Timing Analyzer Messages ;

++------------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime TimeQuest Timing Analyzer

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 10:21:22 2016

+Info: Command: quartus_sta ex8 -c ex8

+Info: qsta_default_script.tcl version: #1

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"

+Info (332105): Deriving Clocks

+    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT

+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50

+    Info (332105): create_clock -period 1.000 -name tick_2500:TICK1|CLK_OUT tick_2500:TICK1|CLK_OUT

+    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON

+Info: Analyzing Slow 1100mV 85C Model

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -4.828

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -4.828             -90.826 CLOCK_50 

+    Info (332119):    -2.650             -63.464 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -2.004             -18.612 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -1.489              -1.489 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is 0.283

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.283               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.376               0.000 CLOCK_50 

+    Info (332119):     0.424               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+    Info (332119):     0.523               0.000 tick_2500:TICK1|CLK_OUT 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.636

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.636             -25.765 CLOCK_50 

+    Info (332119):    -0.394             -14.976 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.394              -5.130 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.404               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Slow 1100mV 0C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -4.731

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -4.731             -86.467 CLOCK_50 

+    Info (332119):    -2.603             -61.065 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -1.916             -17.960 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -1.373              -1.373 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is 0.283

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.283               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+    Info (332119):     0.287               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.389               0.000 CLOCK_50 

+    Info (332119):     0.530               0.000 tick_2500:TICK1|CLK_OUT 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.690

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.690             -23.719 CLOCK_50 

+    Info (332119):    -0.394             -14.868 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.394              -5.140 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.384               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Fast 1100mV 85C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -4.046

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -4.046             -58.106 CLOCK_50 

+    Info (332119):    -1.373             -12.517 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -1.359             -32.665 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.480              -0.480 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is 0.023

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.023               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.061               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.092               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+    Info (332119):     0.182               0.000 CLOCK_50 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.760

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.760             -18.549 CLOCK_50 

+    Info (332119):     0.049               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.131               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.469               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Fast 1100mV 0C Model

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -3.445

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -3.445             -47.547 CLOCK_50 

+    Info (332119):    -1.171             -10.740 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -1.164             -27.696 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.362              -0.362 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is 0.013

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.013               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.014               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+    Info (332119):     0.024               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.172               0.000 CLOCK_50 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.812

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.812             -22.016 CLOCK_50 

+    Info (332119):     0.076               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.135               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.465               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332102): Design is not fully constrained for setup requirements

+Info (332102): Design is not fully constrained for hold requirements

+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings

+    Info: Peak virtual memory: 1209 megabytes

+    Info: Processing ended: Fri Nov 25 10:21:27 2016

+    Info: Elapsed time: 00:00:05

+    Info: Total CPU time (on all processors): 00:00:05

+

+

diff --git a/part_2/ex8/output_files/ex8.sta.summary b/part_2/ex8/output_files/ex8.sta.summary
new file mode 100755
index 0000000..eae3b78
--- /dev/null
+++ b/part_2/ex8/output_files/ex8.sta.summary
@@ -0,0 +1,197 @@
+------------------------------------------------------------

+TimeQuest Timing Analyzer Summary

+------------------------------------------------------------

+

+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'

+Slack : -4.828

+TNS   : -90.826

+

+Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -2.650

+TNS   : -63.464

+

+Type  : Slow 1100mV 85C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -2.004

+TNS   : -18.612

+

+Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -1.489

+TNS   : -1.489

+

+Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.283

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'

+Slack : 0.376

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.424

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.523

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.636

+TNS   : -25.765

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.394

+TNS   : -14.976

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : -0.394

+TNS   : -5.130

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.404

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'

+Slack : -4.731

+TNS   : -86.467

+

+Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -2.603

+TNS   : -61.065

+

+Type  : Slow 1100mV 0C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -1.916

+TNS   : -17.960

+

+Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -1.373

+TNS   : -1.373

+

+Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.283

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.287

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'

+Slack : 0.389

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.530

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.690

+TNS   : -23.719

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.394

+TNS   : -14.868

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : -0.394

+TNS   : -5.140

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.384

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'

+Slack : -4.046

+TNS   : -58.106

+

+Type  : Fast 1100mV 85C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -1.373

+TNS   : -12.517

+

+Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -1.359

+TNS   : -32.665

+

+Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -0.480

+TNS   : -0.480

+

+Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.023

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.061

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.092

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'

+Slack : 0.182

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.760

+TNS   : -18.549

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.049

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.131

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.469

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'

+Slack : -3.445

+TNS   : -47.547

+

+Type  : Fast 1100mV 0C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -1.171

+TNS   : -10.740

+

+Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -1.164

+TNS   : -27.696

+

+Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -0.362

+TNS   : -0.362

+

+Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.013

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.014

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.024

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'

+Slack : 0.172

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.812

+TNS   : -22.016

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.076

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.135

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.465

+TNS   : 0.000

+

+------------------------------------------------------------

diff --git a/part_2/ex8/verilog_files/LFSR.v b/part_2/ex8/verilog_files/LFSR.v
new file mode 100755
index 0000000..46140b2
--- /dev/null
+++ b/part_2/ex8/verilog_files/LFSR.v
@@ -0,0 +1,18 @@
+module LFSR(CLK, en, COUNT);

+

+	input CLK;

+	input en;

+	

+	output [7:1] COUNT;

+	

+	reg [7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		if(en == 1'b1)

+			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		else

+			COUNT <= COUNT;

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/LFSR.v.bak b/part_2/ex8/verilog_files/LFSR.v.bak
new file mode 100755
index 0000000..89ec82a
--- /dev/null
+++ b/part_2/ex8/verilog_files/LFSR.v.bak
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);

+	input CLK;

+	output[7:1] COUNT;

+	reg[7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/add3_ge5.v b/part_2/ex8/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..a3cd6a9
--- /dev/null
+++ b/part_2/ex8/verilog_files/add3_ge5.v
@@ -0,0 +1,34 @@
+//------------------------------

+// Module name: add3_ge5

+// Function: Add 3 to input if it is 5 or above

+// Creator:  Peter Cheung

+// Version:  1.0

+// Date:     21 Jan 2014

+//------------------------------

+

+module add3_ge5(iW,oA);

+

+ input [3:0] iW; 

+ output reg [3:0] oA;  

+ 

+	always @ (iW)

+		case (iW) 

+		//****** input <5, pass to output unchanged ******

+			4'b0000: oA <= 4'b0000; 

+			4'b0001: oA <= 4'b0001; 

+			4'b0010: oA <= 4'b0010; 

+			4'b0011: oA <= 4'b0011; 

+			4'b0100: oA <= 4'b0100;

+			

+		//****** input >=5, output = input + 3	******	

+			4'b0101: oA <= 4'b1000; 

+			4'b0110: oA <= 4'b1001; 

+			4'b0111: oA <= 4'b1010; 

+			4'b1000: oA <= 4'b1011; 

+			4'b1001: oA <= 4'b1100;

+			4'b1010: oA <= 4'b1101;	

+			4'b1011: oA <= 4'b1110;	

+			4'b1100: oA <= 4'b1111;	

+			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow

+		endcase 

+endmodule

diff --git a/part_2/ex8/verilog_files/bin2bcd_16.v b/part_2/ex8/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..b25d0bd
--- /dev/null
+++ b/part_2/ex8/verilog_files/bin2bcd_16.v
@@ -0,0 +1,109 @@
+//------------------------------

+// Module name: bin2bcd_16

+// Function: Converts a 16-bit binary number to 5 digits BCD

+//            .... it uses a shift-and-add3 algorithm

+// Creator:  Peter Cheung

+// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)

+// Date:     24 Nov 2016

+//------------------------------

+//   For more explanation of how this work, see 

+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment

+

+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+

+	input [15:0]	B;		// binary input number

+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD

+	

+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;

+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;

+	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;

+	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;

+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;

+	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;

+

+	// Instantiate a tree of add3-if-greater than or equal to 5 cells

+	//  ... input is w_n, and output is a_n

+	add3_ge5 A1 (w1,a1);

+	add3_ge5 A2 (w2,a2);

+	add3_ge5 A3 (w3,a3);

+	add3_ge5 A4 (w4,a4);

+	add3_ge5 A5 (w5,a5);

+	add3_ge5 A6 (w6,a6);

+	add3_ge5 A7 (w7,a7);

+	add3_ge5 A8 (w8,a8);

+	add3_ge5 A9 (w9,a9);

+	add3_ge5 A10 (w10,a10);

+	add3_ge5 A11 (w11,a11);

+	add3_ge5 A12 (w12,a12);

+	add3_ge5 A13 (w13,a13);

+	add3_ge5 A14 (w14,a14);

+	add3_ge5 A15 (w15,a15);

+	add3_ge5 A16 (w16,a16);

+	add3_ge5 A17 (w17,a17);

+	add3_ge5 A18 (w18,a18);

+	add3_ge5 A19 (w19,a19);

+	add3_ge5 A20 (w20,a20);

+	add3_ge5 A21 (w21,a21);

+	add3_ge5 A22 (w22,a22);

+	add3_ge5 A23 (w23,a23);

+	add3_ge5 A24 (w24,a24);

+	add3_ge5 A25 (w25,a25);

+	add3_ge5 A26 (w26,a26);

+	add3_ge5 A27 (w27,a27);

+	add3_ge5 A28 (w28,a28);

+	add3_ge5 A29 (w29,a29);

+	add3_ge5 A30 (w30,a30);

+	add3_ge5 A31 (w31,a31);

+	add3_ge5 A32 (w32,a32);

+	add3_ge5 A33 (w33,a33);

+	add3_ge5 A34 (w34,a34);

+	add3_ge5 A35 (w35,a35);

+		

+	// wire the tree of add3 modules together

+	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n

+	assign  w2 = {a1[2:0], B[12]};		

+	assign  w3 = {a2[2:0], B[11]};		

+	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};

+	assign  w5 = {a3[2:0], B[10]};

+	assign  w6 = {a4[2:0], a5[3]};

+	assign  w7 = {a5[2:0], B[9]};

+	assign  w8 = {a6[2:0], a7[3]};

+	assign  w9 = {a7[2:0], B[8]};

+	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};

+	assign  w11 = {a8[2:0], a9[3]};

+	assign  w12 = {a9[2:0], B[7]};

+	assign  w13 = {a10[2:0], a11[3]};

+	assign  w14 = {a11[2:0], a12[3]};

+	assign  w15 = {a12[2:0], B[6]};

+	assign  w16 = {a13[2:0], a14[3]};

+	assign  w17 = {a14[2:0], a15[3]};

+	assign  w18 = {a15[2:0], B[5]};

+	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};

+	assign  w20 = {a16[2:0], a17[3]};

+	assign  w21 = {a17[2:0], a18[3]};

+	assign  w22 = {a18[2:0], B[4]};

+	assign  w23 = {a19[2:0], a20[3]};

+	assign  w24 = {a20[2:0], a21[3]};

+	assign  w25 = {a21[2:0], a22[3]};

+	assign  w26 = {a22[2:0], B[3]};

+	assign  w27 = {a23[2:0], a24[3]};

+	assign  w28 = {a24[2:0], a25[3]};

+	assign  w29 = {a25[2:0], a26[3]};

+	assign  w30 = {a26[2:0], B[2]};

+	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};

+	assign  w32 = {a27[2:0], a28[3]};

+	assign  w33 = {a28[2:0], a29[3]};

+	assign  w34 = {a29[2:0], a30[3]};

+	assign  w35 = {a30[2:0], B[1]};

+	

+	// connect up to four BCD digit outputs	

+	assign BCD_0 = {a35[2:0],B[0]};

+	assign BCD_1 = {a34[2:0],a35[3]};

+	assign BCD_2 = {a33[2:0],a34[3]};

+	assign BCD_3 = {a32[2:0],a33[3]};

+	assign BCD_4 = {a31[2:0],a32[3]};	

+endmodule

+

+	

+	

+

diff --git a/part_2/ex8/verilog_files/counter_16.v b/part_2/ex8/verilog_files/counter_16.v
new file mode 100755
index 0000000..c0ec549
--- /dev/null
+++ b/part_2/ex8/verilog_files/counter_16.v
@@ -0,0 +1,21 @@
+`timescale 1ns / 100ps

+

+module counter_16(clock,enable,reset,count);

+

+	parameter BIT_SZ = 16;

+	input clock, enable, reset;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		begin

+			if(enable == 1'b1)

+				count <= count + 1'b1;

+			if(reset == 1'b1)

+				count <= 16'b0;

+		end

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/delay.v b/part_2/ex8/verilog_files/delay.v
new file mode 100755
index 0000000..a983085
--- /dev/null
+++ b/part_2/ex8/verilog_files/delay.v
@@ -0,0 +1,60 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 14;

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+				begin

+					count <= N*128;

+					state <= COUNTING;

+				end

+			COUNTING: 

+				begin

+					if(count == 1'b0)

+						begin

+							state <= TIME_OUT;

+						end

+					else 

+						count <= count - 1'b1;

+				end

+			TIME_OUT: 

+				begin

+					if(trigger == 1'b0)

+						state <= IDLE;

+					else

+						state <= WAIT_LOW;

+				end

+			WAIT_LOW: 

+				if(trigger == 1'b0)

+					state <= IDLE;

+			default: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE:

+					time_out = 1'b0;

+			COUNTING: 

+					time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/delay.v.bak b/part_2/ex8/verilog_files/delay.v.bak
new file mode 100755
index 0000000..7b79342
--- /dev/null
+++ b/part_2/ex8/verilog_files/delay.v.bak
@@ -0,0 +1,47 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 7

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+		count = N-1'b1;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+					state <= COUNTING;

+			COUNTING: if(count == 1'b0) begin

+					count <= n - 1'b1;

+					state <= TIME_OUT;

+				end

+			TIME_OUT: if(trigger == 1'b0)

+					state <= IDLE;

+				else

+					state <= WAIT_LOW;

+			WAIT_LOW: if(trigger == 1'b0)

+					state <= IDLE;

+			defualt: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE: time_out = 1'b0;

+			COUNTING: time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/ex8.v b/part_2/ex8/verilog_files/ex8.v
new file mode 100755
index 0000000..aaa8488
--- /dev/null
+++ b/part_2/ex8/verilog_files/ex8.v
@@ -0,0 +1,23 @@
+module ex8(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/ex8.v.bak b/part_2/ex8/verilog_files/ex8.v.bak
new file mode 100755
index 0000000..ac293e7
--- /dev/null
+++ b/part_2/ex8/verilog_files/ex8.v.bak
@@ -0,0 +1 @@
+module ex8(
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/formula_fsm.v b/part_2/ex8/verilog_files/formula_fsm.v
new file mode 100755
index 0000000..90daa0c
--- /dev/null
+++ b/part_2/ex8/verilog_files/formula_fsm.v
@@ -0,0 +1,66 @@
+module formula_fsm(clk, tick, trigger, time_out, en_lfsr, start_delay, ledr);

+

+input clk, tick, trigger, time_out;

+output en_lfsr, start_delay;

+output [9:0] ledr;

+

+reg [1:0] state;

+reg led_on, en_lfsr, start_delay;

+reg [9:0] ledr;

+

+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;

+

+initial 

+	begin

+		state = WAIT_TRIGGER;

+		en_lfsr = 1'b0;

+		start_delay = 1'b0;

+	end

+

+always @ (posedge clk)

+	case(state)

+		WAIT_TRIGGER: 

+			begin

+				if(trigger == 1'b1)

+					state <= LIGHT_UP_LEDS;

+			end

+		LIGHT_UP_LEDS:

+				if(ledr == 10'h3ff)

+					state <= WAIT_FOR_TIMEOUT;

+		WAIT_FOR_TIMEOUT:

+				if(time_out == 1'b1)

+					 state <= WAIT_TRIGGER;

+		default: ;

+	endcase

+

+always @ (posedge tick)

+	case(state)

+		WAIT_TRIGGER:

+			ledr = 10'b0;

+		LIGHT_UP_LEDS:

+			ledr <= {ledr[8:0], 1'b1};

+		default:

+			ledr <= 10'h3ff;

+	endcase

+	

+always @ (*)

+	case(state)

+		WAIT_TRIGGER:

+			begin

+

+				en_lfsr = 1'b0;

+				start_delay = 1'b0;

+			end

+		LIGHT_UP_LEDS:

+			begin

+				en_lfsr = 1'b1;

+			end

+		WAIT_FOR_TIMEOUT:

+			begin

+				start_delay = 1'b1;

+				en_lfsr = 1'b0;

+			end

+		default: ;

+	endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/formula_fsm.v.bak b/part_2/ex8/verilog_files/formula_fsm.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex8/verilog_files/formula_fsm.v.bak
diff --git a/part_2/ex8/verilog_files/hex_to_7seg.v b/part_2/ex8/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/ex8/verilog_files/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/ex8/verilog_files/tick_2500.v b/part_2/ex8/verilog_files/tick_2500.v
new file mode 100755
index 0000000..e75a131
--- /dev/null
+++ b/part_2/ex8/verilog_files/tick_2500.v
@@ -0,0 +1,35 @@
+module tick_2500(CLOCK_IN, en, CLK_OUT);

+

+	parameter NBIT = 12;

+	

+	input CLOCK_IN, en;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 12'd2499;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		if(en == 1'b1)

+			begin

+				if(count == 1'b0)

+					begin

+						CLK_OUT <= 1'b1;

+						count <= 12'd2499;

+					end

+				else

+					begin

+						count <= count - 1'b1;

+						CLK_OUT <= 1'b0;

+					end

+			end

+		else 

+			CLK_OUT <= 1'b0;

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/tick_2500.v.bak b/part_2/ex8/verilog_files/tick_2500.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex8/verilog_files/tick_2500.v.bak
diff --git a/part_2/ex8/verilog_files/tick_50000.v b/part_2/ex8/verilog_files/tick_50000.v
new file mode 100755
index 0000000..7ccc81b
--- /dev/null
+++ b/part_2/ex8/verilog_files/tick_50000.v
@@ -0,0 +1,32 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd49999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= 1'b1;

+					count <= 16'd49999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+					CLK_OUT <= 1'b0;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex8/verilog_files/tick_50000.v.bak b/part_2/ex8/verilog_files/tick_50000.v.bak
new file mode 100755
index 0000000..45c4166
--- /dev/null
+++ b/part_2/ex8/verilog_files/tick_50000.v.bak
@@ -0,0 +1,31 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd24999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= ~CLK_OUT;

+					count <= 16'd24999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/c5_pin_model_dump.txt b/part_2/ex9_final/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_2/ex9_final/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2

+io_4iomodule_c5_index: 54gpio_index: 465

+io_4iomodule_c5_index: 33gpio_index: 6

+io_4iomodule_c5_index: 51gpio_index: 461

+io_4iomodule_c5_index: 27gpio_index: 10

+io_4iomodule_c5_index: 57gpio_index: 457

+io_4iomodule_c5_index: 34gpio_index: 14

+io_4iomodule_c5_index: 28gpio_index: 453

+io_4iomodule_c5_index: 26gpio_index: 19

+io_4iomodule_c5_index: 47gpio_index: 449

+io_4iomodule_c5_index: 29gpio_index: 22

+io_4iomodule_c5_index: 3gpio_index: 445

+io_4iomodule_c5_index: 16gpio_index: 27

+io_4iomodule_c5_index: 6gpio_index: 441

+io_4iomodule_c5_index: 50gpio_index: 30

+io_4iomodule_c5_index: 35gpio_index: 437

+io_4iomodule_c5_index: 7gpio_index: 35

+io_4iomodule_c5_index: 53gpio_index: 433

+io_4iomodule_c5_index: 12gpio_index: 38

+io_4iomodule_c5_index: 1gpio_index: 429

+io_4iomodule_c5_index: 22gpio_index: 43

+io_4iomodule_c5_index: 8gpio_index: 425

+io_4iomodule_c5_index: 20gpio_index: 46

+io_4iomodule_c5_index: 30gpio_index: 421

+io_4iomodule_c5_index: 2gpio_index: 51

+io_4iomodule_c5_index: 31gpio_index: 417

+io_4iomodule_c5_index: 39gpio_index: 54

+io_4iomodule_c5_index: 18gpio_index: 413

+io_4iomodule_c5_index: 10gpio_index: 59

+io_4iomodule_c5_index: 42gpio_index: 409

+io_4iomodule_c5_index: 5gpio_index: 62

+io_4iomodule_c5_index: 24gpio_index: 405

+io_4iomodule_c5_index: 37gpio_index: 67

+io_4iomodule_c5_index: 13gpio_index: 401

+io_4iomodule_c5_index: 0gpio_index: 70

+io_4iomodule_c5_index: 44gpio_index: 397

+io_4iomodule_c5_index: 38gpio_index: 75

+io_4iomodule_c5_index: 52gpio_index: 393

+io_4iomodule_c5_index: 32gpio_index: 78

+io_4iomodule_c5_index: 56gpio_index: 389

+io_4iomodule_a_index: 13gpio_index: 385

+io_4iomodule_c5_index: 4gpio_index: 83

+io_4iomodule_c5_index: 23gpio_index: 86

+io_4iomodule_a_index: 15gpio_index: 381

+io_4iomodule_a_index: 8gpio_index: 377

+io_4iomodule_c5_index: 46gpio_index: 91

+io_4iomodule_a_index: 5gpio_index: 373

+io_4iomodule_a_index: 11gpio_index: 369

+io_4iomodule_c5_index: 41gpio_index: 94

+io_4iomodule_a_index: 3gpio_index: 365

+io_4iomodule_c5_index: 25gpio_index: 99

+io_4iomodule_a_index: 7gpio_index: 361

+io_4iomodule_c5_index: 9gpio_index: 102

+io_4iomodule_a_index: 0gpio_index: 357

+io_4iomodule_c5_index: 14gpio_index: 107

+io_4iomodule_a_index: 12gpio_index: 353

+io_4iomodule_c5_index: 45gpio_index: 110

+io_4iomodule_c5_index: 17gpio_index: 115

+io_4iomodule_a_index: 4gpio_index: 349

+io_4iomodule_c5_index: 36gpio_index: 118

+io_4iomodule_a_index: 10gpio_index: 345

+io_4iomodule_a_index: 16gpio_index: 341

+io_4iomodule_c5_index: 15gpio_index: 123

+io_4iomodule_a_index: 14gpio_index: 337

+io_4iomodule_c5_index: 43gpio_index: 126

+io_4iomodule_c5_index: 19gpio_index: 131

+io_4iomodule_a_index: 1gpio_index: 333

+io_4iomodule_c5_index: 59gpio_index: 134

+io_4iomodule_a_index: 2gpio_index: 329

+io_4iomodule_a_index: 9gpio_index: 325

+io_4iomodule_c5_index: 48gpio_index: 139

+io_4iomodule_a_index: 6gpio_index: 321

+io_4iomodule_a_index: 17gpio_index: 317

+io_4iomodule_c5_index: 40gpio_index: 142

+io_4iomodule_c5_index: 11gpio_index: 147

+io_4iomodule_c5_index: 58gpio_index: 150

+io_4iomodule_c5_index: 21gpio_index: 155

+io_4iomodule_c5_index: 49gpio_index: 158

+io_4iomodule_h_c5_index: 0gpio_index: 161

+io_4iomodule_h_c5_index: 6gpio_index: 165

+io_4iomodule_h_c5_index: 10gpio_index: 169

+io_4iomodule_h_c5_index: 3gpio_index: 173

+io_4iomodule_h_c5_index: 8gpio_index: 176

+io_4iomodule_h_c5_index: 11gpio_index: 180

+io_4iomodule_h_c5_index: 7gpio_index: 184

+io_4iomodule_h_c5_index: 5gpio_index: 188

+io_4iomodule_h_c5_index: 1gpio_index: 192

+io_4iomodule_h_c5_index: 2gpio_index: 196

+io_4iomodule_h_c5_index: 9gpio_index: 200

+io_4iomodule_h_c5_index: 4gpio_index: 204

+io_4iomodule_h_index: 15gpio_index: 208

+io_4iomodule_h_index: 1gpio_index: 212

+io_4iomodule_h_index: 3gpio_index: 216

+io_4iomodule_h_index: 2gpio_index: 220

+io_4iomodule_h_index: 11gpio_index: 224

+io_4iomodule_vref_h_index: 1gpio_index: 228

+io_4iomodule_h_index: 20gpio_index: 231

+io_4iomodule_h_index: 8gpio_index: 235

+io_4iomodule_h_index: 6gpio_index: 239

+io_4iomodule_h_index: 10gpio_index: 243

+io_4iomodule_h_index: 23gpio_index: 247

+io_4iomodule_h_index: 7gpio_index: 251

+io_4iomodule_h_index: 22gpio_index: 255

+io_4iomodule_h_index: 5gpio_index: 259

+io_4iomodule_h_index: 24gpio_index: 263

+io_4iomodule_h_index: 0gpio_index: 267

+io_4iomodule_h_index: 13gpio_index: 271

+io_4iomodule_h_index: 21gpio_index: 275

+io_4iomodule_h_index: 16gpio_index: 279

+io_4iomodule_vref_h_index: 0gpio_index: 283

+io_4iomodule_h_index: 12gpio_index: 286

+io_4iomodule_h_index: 4gpio_index: 290

+io_4iomodule_h_index: 19gpio_index: 294

+io_4iomodule_h_index: 18gpio_index: 298

+io_4iomodule_h_index: 17gpio_index: 302

+io_4iomodule_h_index: 25gpio_index: 306

+io_4iomodule_h_index: 14gpio_index: 310

+io_4iomodule_h_index: 9gpio_index: 314

diff --git a/part_2/ex9_final/db/.cmp.kpt b/part_2/ex9_final/db/.cmp.kpt
new file mode 100755
index 0000000..a67a742
--- /dev/null
+++ b/part_2/ex9_final/db/.cmp.kpt
diff --git a/part_2/ex9_final/db/ex9.(0).cnf.cdb b/part_2/ex9_final/db/ex9.(0).cnf.cdb
new file mode 100755
index 0000000..2a49e3b
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(0).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(0).cnf.hdb b/part_2/ex9_final/db/ex9.(0).cnf.hdb
new file mode 100755
index 0000000..f90ac91
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(0).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(1).cnf.cdb b/part_2/ex9_final/db/ex9.(1).cnf.cdb
new file mode 100755
index 0000000..6fa5bfa
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(1).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(1).cnf.hdb b/part_2/ex9_final/db/ex9.(1).cnf.hdb
new file mode 100755
index 0000000..829c3df
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(1).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(2).cnf.cdb b/part_2/ex9_final/db/ex9.(2).cnf.cdb
new file mode 100755
index 0000000..43aabd2
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(2).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(2).cnf.hdb b/part_2/ex9_final/db/ex9.(2).cnf.hdb
new file mode 100755
index 0000000..a2fe649
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(2).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(3).cnf.cdb b/part_2/ex9_final/db/ex9.(3).cnf.cdb
new file mode 100755
index 0000000..dbd336f
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(3).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(3).cnf.hdb b/part_2/ex9_final/db/ex9.(3).cnf.hdb
new file mode 100755
index 0000000..ac9f5e9
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(3).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(4).cnf.cdb b/part_2/ex9_final/db/ex9.(4).cnf.cdb
new file mode 100755
index 0000000..13f6ae2
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(4).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(4).cnf.hdb b/part_2/ex9_final/db/ex9.(4).cnf.hdb
new file mode 100755
index 0000000..b7d17a9
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(4).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(5).cnf.cdb b/part_2/ex9_final/db/ex9.(5).cnf.cdb
new file mode 100755
index 0000000..53d103c
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(5).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(5).cnf.hdb b/part_2/ex9_final/db/ex9.(5).cnf.hdb
new file mode 100755
index 0000000..01910af
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(5).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(6).cnf.cdb b/part_2/ex9_final/db/ex9.(6).cnf.cdb
new file mode 100755
index 0000000..3c6c09e
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(6).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(6).cnf.hdb b/part_2/ex9_final/db/ex9.(6).cnf.hdb
new file mode 100755
index 0000000..1c167a7
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(6).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(7).cnf.cdb b/part_2/ex9_final/db/ex9.(7).cnf.cdb
new file mode 100755
index 0000000..604867e
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(7).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(7).cnf.hdb b/part_2/ex9_final/db/ex9.(7).cnf.hdb
new file mode 100755
index 0000000..da601fb
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(7).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(8).cnf.cdb b/part_2/ex9_final/db/ex9.(8).cnf.cdb
new file mode 100755
index 0000000..97e595e
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(8).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(8).cnf.hdb b/part_2/ex9_final/db/ex9.(8).cnf.hdb
new file mode 100755
index 0000000..42ab8b5
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(8).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(9).cnf.cdb b/part_2/ex9_final/db/ex9.(9).cnf.cdb
new file mode 100755
index 0000000..e219d8b
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(9).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(9).cnf.hdb b/part_2/ex9_final/db/ex9.(9).cnf.hdb
new file mode 100755
index 0000000..0bbfa6a
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.(9).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.asm.qmsg b/part_2/ex9_final/db/ex9.asm.qmsg
new file mode 100755
index 0000000..7acd89c
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075862814 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075862816 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:11:02 2016 " "Processing started: Fri Nov 25 12:11:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075862816 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480075862816 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480075862816 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480075863791 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480075868447 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075868793 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:11:08 2016 " "Processing ended: Fri Nov 25 12:11:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075868793 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075868793 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075868793 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480075868793 ""}

diff --git a/part_2/ex9_final/db/ex9.asm.rdb b/part_2/ex9_final/db/ex9.asm.rdb
new file mode 100755
index 0000000..ece1ac9
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.asm.rdb
diff --git a/part_2/ex9_final/db/ex9.cbx.xml b/part_2/ex9_final/db/ex9.cbx.xml
new file mode 100755
index 0000000..9156ad4
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex9">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex9_final/db/ex9.cmp.ammdb b/part_2/ex9_final/db/ex9.cmp.ammdb
new file mode 100755
index 0000000..b640a2a
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp.ammdb
diff --git a/part_2/ex9_final/db/ex9.cmp.bpm b/part_2/ex9_final/db/ex9.cmp.bpm
new file mode 100755
index 0000000..3cb4242
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp.bpm
diff --git a/part_2/ex9_final/db/ex9.cmp.cdb b/part_2/ex9_final/db/ex9.cmp.cdb
new file mode 100755
index 0000000..5e2cdbb
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp.cdb
diff --git a/part_2/ex9_final/db/ex9.cmp.hdb b/part_2/ex9_final/db/ex9.cmp.hdb
new file mode 100755
index 0000000..3baae81
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp.hdb
diff --git a/part_2/ex9_final/db/ex9.cmp.idb b/part_2/ex9_final/db/ex9.cmp.idb
new file mode 100755
index 0000000..5cbf640
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp.idb
diff --git a/part_2/ex9_final/db/ex9.cmp.logdb b/part_2/ex9_final/db/ex9.cmp.logdb
new file mode 100755
index 0000000..b4567d7
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp.logdb
@@ -0,0 +1,96 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex9_final/db/ex9.cmp.rdb b/part_2/ex9_final/db/ex9.cmp.rdb
new file mode 100755
index 0000000..7298c0d
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp.rdb
diff --git a/part_2/ex9_final/db/ex9.cmp_merge.kpt b/part_2/ex9_final/db/ex9.cmp_merge.kpt
new file mode 100755
index 0000000..fdd3bfe
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cmp_merge.kpt
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..da61997
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..acc52a8
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex9_final/db/ex9.db_info b/part_2/ex9_final/db/ex9.db_info
new file mode 100755
index 0000000..1ce7f97
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Fri Nov 25 11:34:26 2016

diff --git a/part_2/ex9_final/db/ex9.fit.qmsg b/part_2/ex9_final/db/ex9.fit.qmsg
new file mode 100755
index 0000000..c1dd335
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480075828268 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480075828268 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480075828528 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075828590 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075828590 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480075828981 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480075829117 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480075839247 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480075839355 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480075839355 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075839355 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480075839359 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075839359 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075839360 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480075839361 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480075839361 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480075839361 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480075839990 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480075839991 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480075839991 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480075839995 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480075839995 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480075839996 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480075839999 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480075840000 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480075840000 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480075840050 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075840051 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480075845081 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480075845350 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075846139 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480075847006 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480075847947 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075847947 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480075849115 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480075853750 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480075853750 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480075855521 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480075855521 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075855525 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480075857019 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075857059 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075857529 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075857530 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075857977 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075860733 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480075860987 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480075861050 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2592 " "Peak virtual memory: 2592 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075861521 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:11:01 2016 " "Processing ended: Fri Nov 25 12:11:01 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075861521 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075861521 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:01 " "Total CPU time (on all processors): 00:01:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075861521 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480075861521 ""}

diff --git a/part_2/ex9_final/db/ex9.hier_info b/part_2/ex9_final/db/ex9.hier_info
new file mode 100755
index 0000000..2ac051e
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.hier_info
@@ -0,0 +1,784 @@
+|ex9

+CLOCK_50 => CLOCK_50.IN1

+KEY[0] => _.IN1

+KEY[1] => ~NO_FANOUT~

+KEY[2] => ~NO_FANOUT~

+KEY[3] => _.IN1

+HEX0[0] << hex_to_7seg:SEG0.port0

+HEX0[1] << hex_to_7seg:SEG0.port0

+HEX0[2] << hex_to_7seg:SEG0.port0

+HEX0[3] << hex_to_7seg:SEG0.port0

+HEX0[4] << hex_to_7seg:SEG0.port0

+HEX0[5] << hex_to_7seg:SEG0.port0

+HEX0[6] << hex_to_7seg:SEG0.port0

+HEX1[0] << hex_to_7seg:SEG1.port0

+HEX1[1] << hex_to_7seg:SEG1.port0

+HEX1[2] << hex_to_7seg:SEG1.port0

+HEX1[3] << hex_to_7seg:SEG1.port0

+HEX1[4] << hex_to_7seg:SEG1.port0

+HEX1[5] << hex_to_7seg:SEG1.port0

+HEX1[6] << hex_to_7seg:SEG1.port0

+HEX2[0] << hex_to_7seg:SEG2.port0

+HEX2[1] << hex_to_7seg:SEG2.port0

+HEX2[2] << hex_to_7seg:SEG2.port0

+HEX2[3] << hex_to_7seg:SEG2.port0

+HEX2[4] << hex_to_7seg:SEG2.port0

+HEX2[5] << hex_to_7seg:SEG2.port0

+HEX2[6] << hex_to_7seg:SEG2.port0

+HEX3[0] << hex_to_7seg:SEG3.port0

+HEX3[1] << hex_to_7seg:SEG3.port0

+HEX3[2] << hex_to_7seg:SEG3.port0

+HEX3[3] << hex_to_7seg:SEG3.port0

+HEX3[4] << hex_to_7seg:SEG3.port0

+HEX3[5] << hex_to_7seg:SEG3.port0

+HEX3[6] << hex_to_7seg:SEG3.port0

+HEX4[0] << hex_to_7seg:SEG4.port0

+HEX4[1] << hex_to_7seg:SEG4.port0

+HEX4[2] << hex_to_7seg:SEG4.port0

+HEX4[3] << hex_to_7seg:SEG4.port0

+HEX4[4] << hex_to_7seg:SEG4.port0

+HEX4[5] << hex_to_7seg:SEG4.port0

+HEX4[6] << hex_to_7seg:SEG4.port0

+HEX5[0] << hex_to_7seg:SEG5.port0

+HEX5[1] << hex_to_7seg:SEG5.port0

+HEX5[2] << hex_to_7seg:SEG5.port0

+HEX5[3] << hex_to_7seg:SEG5.port0

+HEX5[4] << hex_to_7seg:SEG5.port0

+HEX5[5] << hex_to_7seg:SEG5.port0

+HEX5[6] << hex_to_7seg:SEG5.port0

+LEDR[0] << formula_fsm:FSM.port5

+LEDR[1] << formula_fsm:FSM.port5

+LEDR[2] << formula_fsm:FSM.port5

+LEDR[3] << formula_fsm:FSM.port5

+LEDR[4] << formula_fsm:FSM.port5

+LEDR[5] << formula_fsm:FSM.port5

+LEDR[6] << formula_fsm:FSM.port5

+LEDR[7] << formula_fsm:FSM.port5

+LEDR[8] << formula_fsm:FSM.port5

+LEDR[9] << formula_fsm:FSM.port5

+

+

+|ex9|tick_50000:TICK0

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => count[12].CLK

+CLOCK_IN => count[13].CLK

+CLOCK_IN => count[14].CLK

+CLOCK_IN => count[15].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|formula_fsm:FSM

+clk => count[0].CLK

+clk => count[1].CLK

+clk => count[2].CLK

+clk => count[3].CLK

+clk => count[4].CLK

+clk => count[5].CLK

+clk => count[6].CLK

+clk => count[7].CLK

+clk => count[8].CLK

+clk => count[9].CLK

+clk => count[10].CLK

+clk => count[11].CLK

+clk => ledr[0]~reg0.CLK

+clk => ledr[1]~reg0.CLK

+clk => ledr[2]~reg0.CLK

+clk => ledr[3]~reg0.CLK

+clk => ledr[4]~reg0.CLK

+clk => ledr[5]~reg0.CLK

+clk => ledr[6]~reg0.CLK

+clk => ledr[7]~reg0.CLK

+clk => ledr[8]~reg0.CLK

+clk => ledr[9]~reg0.CLK

+clk => state~3.DATAIN

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE

+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE

+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|LFSR:LFSR0

+CLK => COUNT[1]~reg0.CLK

+CLK => COUNT[2]~reg0.CLK

+CLK => COUNT[3]~reg0.CLK

+CLK => COUNT[4]~reg0.CLK

+CLK => COUNT[5]~reg0.CLK

+CLK => COUNT[6]~reg0.CLK

+CLK => COUNT[7]~reg0.CLK

+en => COUNT[1]~reg0.ENA

+en => COUNT[2]~reg0.ENA

+en => COUNT[3]~reg0.ENA

+en => COUNT[4]~reg0.ENA

+en => COUNT[5]~reg0.ENA

+en => COUNT[6]~reg0.ENA

+en => COUNT[7]~reg0.ENA

+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|delay:DEL0

+clk => count[0].CLK

+clk => count[1].CLK

+clk => count[2].CLK

+clk => count[3].CLK

+clk => count[4].CLK

+clk => count[5].CLK

+clk => count[6].CLK

+clk => count[7].CLK

+clk => count[8].CLK

+clk => count[9].CLK

+clk => count[10].CLK

+clk => count[11].CLK

+clk => count[12].CLK

+clk => count[13].CLK

+clk => state~4.DATAIN

+N[0] => count.DATAB

+N[1] => count.DATAB

+N[2] => count.DATAB

+N[3] => count.DATAB

+N[4] => count.DATAB

+N[5] => count.DATAB

+N[6] => count.DATAB

+N[7] => ~NO_FANOUT~

+N[8] => ~NO_FANOUT~

+N[9] => ~NO_FANOUT~

+N[10] => ~NO_FANOUT~

+N[11] => ~NO_FANOUT~

+N[12] => ~NO_FANOUT~

+N[13] => ~NO_FANOUT~

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector17.IN3

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector14.IN2

+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|counter_16:COUNT0

+clock => count[0]~reg0.CLK

+clock => count[1]~reg0.CLK

+clock => count[2]~reg0.CLK

+clock => count[3]~reg0.CLK

+clock => count[4]~reg0.CLK

+clock => count[5]~reg0.CLK

+clock => count[6]~reg0.CLK

+clock => count[7]~reg0.CLK

+clock => count[8]~reg0.CLK

+clock => count[9]~reg0.CLK

+clock => count[10]~reg0.CLK

+clock => count[11]~reg0.CLK

+clock => count[12]~reg0.CLK

+clock => count[13]~reg0.CLK

+clock => count[14]~reg0.CLK

+clock => count[15]~reg0.CLK

+clock => state.CLK

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => state.OUTPUTSELECT

+stop => state.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD

+B[0] => BCD_0[0].DATAIN

+B[1] => w35[0].IN1

+B[2] => w30[0].IN1

+B[3] => w26[0].IN1

+B[4] => w22[0].IN1

+B[5] => w18[0].IN1

+B[6] => w15[0].IN1

+B[7] => w12[0].IN1

+B[8] => w9[0].IN1

+B[9] => w7[0].IN1

+B[10] => w5[0].IN1

+B[11] => w3[0].IN1

+B[12] => w2[0].IN1

+B[13] => w1[0].IN1

+B[14] => w1[1].IN1

+B[15] => w1[2].IN1

+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE

+BCD_0[1] <= add3_ge5:A35.port1

+BCD_0[2] <= add3_ge5:A35.port1

+BCD_0[3] <= add3_ge5:A35.port1

+BCD_1[0] <= add3_ge5:A35.port1

+BCD_1[1] <= add3_ge5:A34.port1

+BCD_1[2] <= add3_ge5:A34.port1

+BCD_1[3] <= add3_ge5:A34.port1

+BCD_2[0] <= add3_ge5:A34.port1

+BCD_2[1] <= add3_ge5:A33.port1

+BCD_2[2] <= add3_ge5:A33.port1

+BCD_2[3] <= add3_ge5:A33.port1

+BCD_3[0] <= add3_ge5:A33.port1

+BCD_3[1] <= add3_ge5:A32.port1

+BCD_3[2] <= add3_ge5:A32.port1

+BCD_3[3] <= add3_ge5:A32.port1

+BCD_4[0] <= add3_ge5:A32.port1

+BCD_4[1] <= add3_ge5:A31.port1

+BCD_4[2] <= add3_ge5:A31.port1

+BCD_4[3] <= add3_ge5:A31.port1

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A1

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A2

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A3

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A4

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A5

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A6

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A7

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A8

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A9

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A10

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A11

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A12

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A13

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A14

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A15

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A16

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A17

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A18

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A19

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A20

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A21

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A22

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A23

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A24

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A25

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A26

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A27

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A28

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A29

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A30

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A31

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A32

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A33

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A34

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A35

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|hex_to_7seg:SEG0

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG1

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG2

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG3

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG4

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG5

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

diff --git a/part_2/ex9_final/db/ex9.hif b/part_2/ex9_final/db/ex9.hif
new file mode 100755
index 0000000..928d6f7
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.hif
diff --git a/part_2/ex9_final/db/ex9.lpc.html b/part_2/ex9_final/db/ex9.lpc.html
new file mode 100755
index 0000000..795349d
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.lpc.html
@@ -0,0 +1,770 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+<TR >

+<TD >SEG5</TD>

+<TD >4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >7</TD>

+<TD >4</TD>

+<TD >4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG3</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG1</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A35</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A34</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A33</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A32</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A31</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A30</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A29</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A28</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A27</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A26</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A25</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A24</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A23</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A22</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A21</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A20</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A19</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A18</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A17</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A16</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A15</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A14</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A13</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A12</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A11</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A10</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A9</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A8</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A7</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A6</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A5</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A4</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A3</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD</TD>

+<TD >16</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >20</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >COUNT0</TD>

+<TD >3</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >16</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >DEL0</TD>

+<TD >16</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >1</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >LFSR0</TD>

+<TD >2</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >FSM</TD>

+<TD >3</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >12</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >TICK0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+</TABLE>

diff --git a/part_2/ex9_final/db/ex9.lpc.rdb b/part_2/ex9_final/db/ex9.lpc.rdb
new file mode 100755
index 0000000..9db0391
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.lpc.rdb
diff --git a/part_2/ex9_final/db/ex9.lpc.txt b/part_2/ex9_final/db/ex9.lpc.txt
new file mode 100755
index 0000000..538b3bf
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.lpc.txt
@@ -0,0 +1,53 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; FSM       ; 3     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex9_final/db/ex9.map.ammdb b/part_2/ex9_final/db/ex9.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.ammdb
diff --git a/part_2/ex9_final/db/ex9.map.bpm b/part_2/ex9_final/db/ex9.map.bpm
new file mode 100755
index 0000000..6ecfd55
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.bpm
diff --git a/part_2/ex9_final/db/ex9.map.cdb b/part_2/ex9_final/db/ex9.map.cdb
new file mode 100755
index 0000000..61f1857
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.cdb
diff --git a/part_2/ex9_final/db/ex9.map.hdb b/part_2/ex9_final/db/ex9.map.hdb
new file mode 100755
index 0000000..de65f19
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.hdb
diff --git a/part_2/ex9_final/db/ex9.map.kpt b/part_2/ex9_final/db/ex9.map.kpt
new file mode 100755
index 0000000..dc1f7e5
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.kpt
diff --git a/part_2/ex9_final/db/ex9.map.logdb b/part_2/ex9_final/db/ex9.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex9_final/db/ex9.map.qmsg b/part_2/ex9_final/db/ex9.map.qmsg
new file mode 100755
index 0000000..9efa221
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.qmsg
@@ -0,0 +1,74 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075816461 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075816463 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:10:16 2016 " "Processing started: Fri Nov 25 12:10:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075816463 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075816463 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075816464 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480075816957 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480075816958 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825232 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825232 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825233 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825233 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825234 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825234 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075825237 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825238 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825238 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825239 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825239 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825239 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075825241 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825241 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825241 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825244 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825244 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825245 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825245 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825246 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825246 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480075825275 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825276 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "C:/New folder/ex9/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825277 ""}

+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480075825278 "|ex9|formula_fsm:FSM"}

+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480075825278 "|ex9|formula_fsm:FSM"}

+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825278 "|ex9|formula_fsm:FSM"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825285 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825286 ""}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480075825286 "|ex9|delay:DEL0"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825287 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "C:/New folder/ex9/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825288 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825289 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825294 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480075825850 ""}

+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480075826014 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480075826091 ""}

+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480075826405 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075826430 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480075826519 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075826519 ""}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075826562 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075826562 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480075826562 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480075826563 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480075826563 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480075826563 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480075826563 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "898 " "Peak virtual memory: 898 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075826577 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:10:26 2016 " "Processing ended: Fri Nov 25 12:10:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075826577 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075826577 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075826577 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075826577 ""}

diff --git a/part_2/ex9_final/db/ex9.map.rdb b/part_2/ex9_final/db/ex9.map.rdb
new file mode 100755
index 0000000..7d9ef6e
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map.rdb
diff --git a/part_2/ex9_final/db/ex9.map_bb.cdb b/part_2/ex9_final/db/ex9.map_bb.cdb
new file mode 100755
index 0000000..a961dfd
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map_bb.cdb
diff --git a/part_2/ex9_final/db/ex9.map_bb.hdb b/part_2/ex9_final/db/ex9.map_bb.hdb
new file mode 100755
index 0000000..d42ddcf
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map_bb.hdb
diff --git a/part_2/ex9_final/db/ex9.map_bb.logdb b/part_2/ex9_final/db/ex9.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex9_final/db/ex9.pre_map.hdb b/part_2/ex9_final/db/ex9.pre_map.hdb
new file mode 100755
index 0000000..b01e48d
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.pre_map.hdb
diff --git a/part_2/ex9_final/db/ex9.root_partition.map.reg_db.cdb b/part_2/ex9_final/db/ex9.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..c515539
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.root_partition.map.reg_db.cdb
diff --git a/part_2/ex9_final/db/ex9.routing.rdb b/part_2/ex9_final/db/ex9.routing.rdb
new file mode 100755
index 0000000..e96d120
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.routing.rdb
diff --git a/part_2/ex9_final/db/ex9.rtlv.hdb b/part_2/ex9_final/db/ex9.rtlv.hdb
new file mode 100755
index 0000000..210b835
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.rtlv.hdb
diff --git a/part_2/ex9_final/db/ex9.rtlv_sg.cdb b/part_2/ex9_final/db/ex9.rtlv_sg.cdb
new file mode 100755
index 0000000..bdf2cf1
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.rtlv_sg.cdb
diff --git a/part_2/ex9_final/db/ex9.rtlv_sg_swap.cdb b/part_2/ex9_final/db/ex9.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..b2375d1
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.rtlv_sg_swap.cdb
diff --git a/part_2/ex9_final/db/ex9.sld_design_entry.sci b/part_2/ex9_final/db/ex9.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.sld_design_entry.sci
diff --git a/part_2/ex9_final/db/ex9.sld_design_entry_dsc.sci b/part_2/ex9_final/db/ex9.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.sld_design_entry_dsc.sci
diff --git a/part_2/ex9_final/db/ex9.smart_action.txt b/part_2/ex9_final/db/ex9.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex9_final/db/ex9.smp_dump.txt b/part_2/ex9_final/db/ex9.smp_dump.txt
new file mode 100755
index 0000000..26e74f6
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.smp_dump.txt
@@ -0,0 +1,13 @@
+

+State Machine - |ex9|delay:DEL0|state

+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 

+state.IDLE 0 0 0 0 

+state.COUNTING 0 0 1 1 

+state.TIME_OUT 0 1 0 1 

+state.WAIT_LOW 1 0 0 1 

+

+State Machine - |ex9|formula_fsm:FSM|state

+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 

+state.WAIT_TRIGGER 0 0 0 

+state.LIGHT_UP_LEDS 1 0 1 

+state.WAIT_FOR_TIMEOUT 1 1 0 

diff --git a/part_2/ex9_final/db/ex9.sta.qmsg b/part_2/ex9_final/db/ex9.sta.qmsg
new file mode 100755
index 0000000..d471141
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.sta.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075870370 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075870371 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:11:09 2016 " "Processing started: Fri Nov 25 12:11:09 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075870371 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075870371 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075870371 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075870501 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871062 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871062 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871118 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871118 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871628 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871651 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871651 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075871652 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075871652 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075871652 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871652 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871654 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871669 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075871670 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075871678 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075871702 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871702 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT  " "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.047             -40.775 CLOCK_50  " "   -2.047             -40.775 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871704 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.179               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871707 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871709 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871710 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.637             -18.132 CLOCK_50  " "   -0.637             -18.132 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871712 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075871723 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871759 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872664 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872745 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075872753 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872753 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT  " "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.323             -41.799 CLOCK_50  " "   -2.323             -41.799 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872755 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.193               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 CLOCK_50  " "    0.405               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872759 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872761 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872762 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.689             -16.816 CLOCK_50  " "   -0.689             -16.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872764 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075872775 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872921 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873695 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873765 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075873769 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873769 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT  " "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.918             -13.912 CLOCK_50  " "   -0.918             -13.912 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873771 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT  " "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873775 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873776 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873778 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.740             -12.957 CLOCK_50  " "   -0.740             -12.957 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT  " "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873779 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075873791 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873956 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075873959 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873959 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT  " "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.868             -11.639 CLOCK_50  " "   -0.868             -11.639 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873960 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT  " "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873964 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873965 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873967 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.789             -15.486 CLOCK_50  " "   -0.789             -15.486 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.024               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873968 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075875504 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075875506 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1213 " "Peak virtual memory: 1213 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075875553 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:11:15 2016 " "Processing ended: Fri Nov 25 12:11:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075875553 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075875553 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075875553 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075875553 ""}

diff --git a/part_2/ex9_final/db/ex9.sta.rdb b/part_2/ex9_final/db/ex9.sta.rdb
new file mode 100755
index 0000000..4e60cb5
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.sta.rdb
diff --git a/part_2/ex9_final/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex9_final/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..6b64eb8
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex9_final/db/ex9.tis_db_list.ddb b/part_2/ex9_final/db/ex9.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.tis_db_list.ddb
diff --git a/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_0c.ddb b/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..8021c27
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_85c.ddb b/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..f050a53
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_0c.ddb b/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..820cefc
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_85c.ddb b/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..8f07a04
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex9_final/db/ex9.tmw_info b/part_2/ex9_final/db/ex9.tmw_info
new file mode 100755
index 0000000..436c9e2
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:01:01

+start_analysis_synthesis:s:00:00:12-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:00:35-start_full_compilation

+start_assembler:s:00:00:07-start_full_compilation

+start_timing_analyzer:s:00:00:07-start_full_compilation

diff --git a/part_2/ex9_final/db/ex9.vpr.ammdb b/part_2/ex9_final/db/ex9.vpr.ammdb
new file mode 100755
index 0000000..51295de
--- /dev/null
+++ b/part_2/ex9_final/db/ex9.vpr.ammdb
diff --git a/part_2/ex9_final/db/ex9_partition_pins.json b/part_2/ex9_final/db/ex9_partition_pins.json
new file mode 100755
index 0000000..701d3b6
--- /dev/null
+++ b/part_2/ex9_final/db/ex9_partition_pins.json
@@ -0,0 +1,201 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "HEX0[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[6]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[0]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[1]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[2]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[3]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[4]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[5]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[6]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[7]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[8]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[9]",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[0]",

+					"strict" : false

+				},

+				{

+					"name" : "CLOCK_50",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[3]",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex9_final/db/prev_cmp_ex9.qmsg b/part_2/ex9_final/db/prev_cmp_ex9.qmsg
new file mode 100755
index 0000000..ba5a172
--- /dev/null
+++ b/part_2/ex9_final/db/prev_cmp_ex9.qmsg
@@ -0,0 +1,186 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075580936 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075580938 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:06:20 2016 " "Processing started: Fri Nov 25 12:06:20 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075580938 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075580938 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075580938 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480075581376 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480075581377 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590051 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590051 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590053 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590053 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590054 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590054 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075590057 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590057 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590057 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590059 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590059 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590059 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075590060 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590061 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590061 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590065 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590065 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590066 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480075590096 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590103 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "C:/New folder/ex9/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590104 ""}

+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480075590105 "|ex9|formula_fsm:FSM"}

+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480075590105 "|ex9|formula_fsm:FSM"}

+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590105 "|ex9|formula_fsm:FSM"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590111 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590112 ""}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480075590112 "|ex9|delay:DEL0"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590113 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "C:/New folder/ex9/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590113 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590115 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590120 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480075590684 ""}

+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480075590850 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480075590927 ""}

+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480075591254 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075591280 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480075591369 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075591369 ""}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075591413 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075591413 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480075591413 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "350 " "Implemented 350 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480075591414 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480075591414 ""} { "Info" "ICUT_CUT_TM_LCELLS" "293 " "Implemented 293 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480075591414 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480075591414 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "897 " "Peak virtual memory: 897 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075591427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:06:31 2016 " "Processing ended: Fri Nov 25 12:06:31 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075591427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075591427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075591427 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075591427 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1480075593013 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075593013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:06:32 2016 " "Processing started: Fri Nov 25 12:06:32 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075593013 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480075593013 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480075593014 ""}

+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480075593132 ""}

+{ "Info" "0" "" "Project  = ex9" {  } {  } 0 0 "Project  = ex9" 0 0 "Fitter" 0 0 1480075593133 ""}

+{ "Info" "0" "" "Revision = ex9" {  } {  } 0 0 "Revision = ex9" 0 0 "Fitter" 0 0 1480075593133 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480075593245 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480075593245 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480075593510 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075593600 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075593600 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480075593986 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480075594120 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480075604181 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480075604289 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480075604289 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075604289 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480075604293 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075604294 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075604295 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480075604295 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480075604295 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480075604296 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480075604931 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480075604932 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480075604932 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480075604936 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480075604936 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480075604937 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480075604941 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480075604942 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480075604942 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480075604990 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075604991 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480075610020 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480075610281 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075611109 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480075611804 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480075612838 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075612839 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480075614028 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480075618515 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480075618515 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480075620193 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480075620193 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075620197 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.54 " "Total time spent on timing analysis during the Fitter is 0.54 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480075621681 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075621719 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075622162 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075622162 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075622601 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075625362 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480075625612 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480075625677 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2607 " "Peak virtual memory: 2607 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075626138 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:07:06 2016 " "Processing ended: Fri Nov 25 12:07:06 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075626138 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075626138 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:59 " "Total CPU time (on all processors): 00:00:59" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075626138 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480075626138 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480075627439 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075627441 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:07:07 2016 " "Processing started: Fri Nov 25 12:07:07 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075627441 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480075627441 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480075627442 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480075628223 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480075632816 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "894 " "Peak virtual memory: 894 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075633154 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:07:13 2016 " "Processing ended: Fri Nov 25 12:07:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075633154 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075633154 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075633154 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480075633154 ""}

+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480075633850 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480075634664 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075634665 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:07:14 2016 " "Processing started: Fri Nov 25 12:07:14 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075634665 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075634665 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075634665 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075634795 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635355 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635356 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635402 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635403 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635903 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635926 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635927 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075635928 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075635928 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075635928 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635928 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635930 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635943 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075635944 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075635952 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075635977 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635977 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.283 " "Worst-case setup slack is -3.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.283            -151.754 tick_50000:TICK0\|CLK_OUT  " "   -3.283            -151.754 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.079             -36.052 CLOCK_50  " "   -2.079             -36.052 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.282              -1.282 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.282              -1.282 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635979 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.277 " "Worst-case hold slack is 0.277" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.277               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.277               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.373               0.000 CLOCK_50  " "    0.373               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.487               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.487               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635983 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635985 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635986 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.616 " "Worst-case minimum pulse width slack is -0.616" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.616             -16.865 CLOCK_50  " "   -0.616             -16.865 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -36.356 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -36.356 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.359               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635988 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075635999 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075636036 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075636936 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637008 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075637015 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637015 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.254 " "Worst-case setup slack is -3.254" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.254            -146.749 tick_50000:TICK0\|CLK_OUT  " "   -3.254            -146.749 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.349             -36.643 CLOCK_50  " "   -2.349             -36.643 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.195              -1.195 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.195              -1.195 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637016 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.280 " "Worst-case hold slack is 0.280" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.280               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.280               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.388               0.000 CLOCK_50  " "    0.388               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.418               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.418               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637020 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637022 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637023 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.666 " "Worst-case minimum pulse width slack is -0.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.666             -15.553 CLOCK_50  " "   -0.666             -15.553 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -35.612 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -35.612 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.378               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.378               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637025 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075637036 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637177 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637956 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638023 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075638026 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638026 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.803 " "Worst-case setup slack is -1.803" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.803             -80.359 tick_50000:TICK0\|CLK_OUT  " "   -1.803             -80.359 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.941             -12.107 CLOCK_50  " "   -0.941             -12.107 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.396              -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.396              -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638028 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.069 " "Worst-case hold slack is 0.069" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.069               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.069               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.104               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.104               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180               0.000 CLOCK_50  " "    0.180               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638032 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638034 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638035 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.749 " "Worst-case minimum pulse width slack is -0.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.749             -12.120 CLOCK_50  " "   -0.749             -12.120 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.047               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.047               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.348               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.348               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638037 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075638049 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638209 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075638212 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638212 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.560 " "Worst-case setup slack is -1.560" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.560             -68.840 tick_50000:TICK0\|CLK_OUT  " "   -1.560             -68.840 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.917              -9.973 CLOCK_50  " "   -0.917              -9.973 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.288              -0.288 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.288              -0.288 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638213 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.046 " "Worst-case hold slack is 0.046" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.046               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.046               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.065               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.065               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.174               0.000 CLOCK_50  " "    0.174               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638217 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638219 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638220 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.797 " "Worst-case minimum pulse width slack is -0.797" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.797             -14.383 CLOCK_50  " "   -0.797             -14.383 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.077               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.077               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.383               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.383               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638222 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075639780 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075639782 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1211 " "Peak virtual memory: 1211 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075639829 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:07:19 2016 " "Processing ended: Fri Nov 25 12:07:19 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075639829 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075639829 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075639829 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075639829 ""}

+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 53 s " "Quartus Prime Full Compilation was successful. 0 errors, 53 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075640590 ""}

diff --git a/part_2/ex9_final/ex9.qpf b/part_2/ex9_final/ex9.qpf
new file mode 100755
index 0000000..28b4ce8
--- /dev/null
+++ b/part_2/ex9_final/ex9.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 10:28:00  November 25, 2016

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "16.0"

+DATE = "10:28:00  November 25, 2016"

+

+# Revisions

+

+PROJECT_REVISION = "ex9"

diff --git a/part_2/ex9_final/ex9.qsf b/part_2/ex9_final/ex9.qsf
new file mode 100755
index 0000000..af789d5
--- /dev/null
+++ b/part_2/ex9_final/ex9.qsf
@@ -0,0 +1,274 @@
+#============================================================

+# CLOCK

+#============================================================

+set_location_assignment PIN_AF14 -to CLOCK_50

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50

+

+#============================================================

+# Add-on Card Interface Pins

+#============================================================

+set_location_assignment PIN_AJ20 -to PWM_OUT

+set_location_assignment PIN_AK21 -to DAC_LD

+set_location_assignment PIN_AD20 -to DAC_CS

+set_location_assignment PIN_AF20 -to DAC_SCK

+set_location_assignment PIN_AF21 -to ADC_SCK

+set_location_assignment PIN_AG21 -to ADC_SDI

+set_location_assignment PIN_AG20 -to ADC_CS

+set_location_assignment PIN_AG18 -to DAC_SDI

+set_location_assignment PIN_AJ21 -to ADC_SDO

+set_location_assignment PIN_Y17 -to OLED_CS

+set_location_assignment PIN_Y18 -to OLED_RST

+set_location_assignment PIN_AK18 -to OLED_DC

+set_location_assignment PIN_AJ19 -to OLED_CLK

+set_location_assignment PIN_AJ16 -to OLED_DATA

+

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO

+

+

+#============================================================

+# HEX0

+#============================================================

+set_location_assignment PIN_AE26 -to HEX0[0]

+set_location_assignment PIN_AE27 -to HEX0[1]

+set_location_assignment PIN_AE28 -to HEX0[2]

+set_location_assignment PIN_AG27 -to HEX0[3]

+set_location_assignment PIN_AF28 -to HEX0[4]

+set_location_assignment PIN_AG28 -to HEX0[5]

+set_location_assignment PIN_AH28 -to HEX0[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]

+

+#============================================================

+# HEX1

+#============================================================

+set_location_assignment PIN_AJ29 -to HEX1[0]

+set_location_assignment PIN_AH29 -to HEX1[1]

+set_location_assignment PIN_AH30 -to HEX1[2]

+set_location_assignment PIN_AG30 -to HEX1[3]

+set_location_assignment PIN_AF29 -to HEX1[4]

+set_location_assignment PIN_AF30 -to HEX1[5]

+set_location_assignment PIN_AD27 -to HEX1[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]

+

+#============================================================

+# HEX2

+#============================================================

+set_location_assignment PIN_AB23 -to HEX2[0]

+set_location_assignment PIN_AE29 -to HEX2[1]

+set_location_assignment PIN_AD29 -to HEX2[2]

+set_location_assignment PIN_AC28 -to HEX2[3]

+set_location_assignment PIN_AD30 -to HEX2[4]

+set_location_assignment PIN_AC29 -to HEX2[5]

+set_location_assignment PIN_AC30 -to HEX2[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]

+

+#============================================================

+# HEX3

+#============================================================

+set_location_assignment PIN_AD26 -to HEX3[0]

+set_location_assignment PIN_AC27 -to HEX3[1]

+set_location_assignment PIN_AD25 -to HEX3[2]

+set_location_assignment PIN_AC25 -to HEX3[3]

+set_location_assignment PIN_AB28 -to HEX3[4]

+set_location_assignment PIN_AB25 -to HEX3[5]

+set_location_assignment PIN_AB22 -to HEX3[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]

+

+#============================================================

+# HEX4

+#============================================================

+set_location_assignment PIN_AA24 -to HEX4[0]

+set_location_assignment PIN_Y23 -to HEX4[1]

+set_location_assignment PIN_Y24 -to HEX4[2]

+set_location_assignment PIN_W22 -to HEX4[3]

+set_location_assignment PIN_W24 -to HEX4[4]

+set_location_assignment PIN_V23 -to HEX4[5]

+set_location_assignment PIN_W25 -to HEX4[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]

+

+#============================================================

+# HEX5

+#============================================================

+set_location_assignment PIN_V25 -to HEX5[0]

+set_location_assignment PIN_AA28 -to HEX5[1]

+set_location_assignment PIN_Y27 -to HEX5[2]

+set_location_assignment PIN_AB27 -to HEX5[3]

+set_location_assignment PIN_AB26 -to HEX5[4]

+set_location_assignment PIN_AA26 -to HEX5[5]

+set_location_assignment PIN_AA25 -to HEX5[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]

+

+#============================================================

+# KEY

+#============================================================

+set_location_assignment PIN_AA14 -to KEY[0]

+set_location_assignment PIN_AA15 -to KEY[1]

+set_location_assignment PIN_W15 -to KEY[2]

+set_location_assignment PIN_Y16 -to KEY[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]

+

+#============================================================

+# LEDR

+#============================================================

+set_location_assignment PIN_V16 -to LEDR[0]

+set_location_assignment PIN_W16 -to LEDR[1]

+set_location_assignment PIN_V17 -to LEDR[2]

+set_location_assignment PIN_V18 -to LEDR[3]

+set_location_assignment PIN_W17 -to LEDR[4]

+set_location_assignment PIN_W19 -to LEDR[5]

+set_location_assignment PIN_Y19 -to LEDR[6]

+set_location_assignment PIN_W20 -to LEDR[7]

+set_location_assignment PIN_W21 -to LEDR[8]

+set_location_assignment PIN_Y21 -to LEDR[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]

+

+#============================================================

+# SW

+#============================================================

+set_location_assignment PIN_AB12 -to SW[0]

+set_location_assignment PIN_AC12 -to SW[1]

+set_location_assignment PIN_AF9 -to SW[2]

+set_location_assignment PIN_AF10 -to SW[3]

+set_location_assignment PIN_AD11 -to SW[4]

+set_location_assignment PIN_AD12 -to SW[5]

+set_location_assignment PIN_AE11 -to SW[6]

+set_location_assignment PIN_AC9 -to SW[7]

+set_location_assignment PIN_AD10 -to SW[8]

+set_location_assignment PIN_AE12 -to SW[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]

+

+#============================================================

+# End of pin and io_standard assignments

+#============================================================# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 10:28:00  November 25, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex9_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex9

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v

+set_global_assignment -name VERILOG_FILE verilog_files/delay.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name VERILOG_FILE verilog_files/ex9.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex9_final/ex9.qsf.bak b/part_2/ex9_final/ex9.qsf.bak
new file mode 100755
index 0000000..d4eef07
--- /dev/null
+++ b/part_2/ex9_final/ex9.qsf.bak
@@ -0,0 +1,65 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 10:28:00  November 25, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex9_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex9

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

+set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v

+set_global_assignment -name VERILOG_FILE verilog_files/delay.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name VERILOG_FILE verilog_files/ex9.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex9_final/ex9.qws b/part_2/ex9_final/ex9.qws
new file mode 100755
index 0000000..5ba0123
--- /dev/null
+++ b/part_2/ex9_final/ex9.qws
diff --git a/part_2/ex9_final/incremental_db/README b/part_2/ex9_final/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.

+

+The compiled_partitions sub-folder contains previous compilation results for each partition.

+As long as this folder is preserved, incremental compilation results from earlier compiles

+can be re-used.  To perform a clean compilation from source files for all partitions, both

+the db and incremental_db folder should be removed.

+

+The imported_partitions sub-folder contains the last imported QXP for each imported partition.

+As long as this folder is preserved, imported partitions will be automatically re-imported

+when the db or incremental_db/compiled_partitions folders are removed.

+

diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.db_info b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.db_info
new file mode 100755
index 0000000..f84b742
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Fri Nov 25 10:41:49 2016

diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
new file mode 100755
index 0000000..5548723
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
new file mode 100755
index 0000000..f0b13b5
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..ab08a4f
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..45da527
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
new file mode 100755
index 0000000..d5fd8e6
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..614de49
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
new file mode 100755
index 0000000..658e9a5
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.dpi b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
new file mode 100755
index 0000000..604edf2
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..50abb6e
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..cbb0e03
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
new file mode 100755
index 0000000..4ce95ae
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.kpt b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
new file mode 100755
index 0000000..0fd0d41
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
new file mode 100755
index 0000000..26d62d0
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
new file mode 100755
index 0000000..b6b0e17
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
new file mode 100755
index 0000000..5bc7cd4
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.opi b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.opi
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
new file mode 100755
index 0000000..26d62d0
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
new file mode 100755
index 0000000..c171a97
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
new file mode 100755
index 0000000..a55899b
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
new file mode 100755
index 0000000..658e9a5
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..50abb6e
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..cbb0e03
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
new file mode 100755
index 0000000..4ce95ae
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
new file mode 100755
index 0000000..0fd0d41
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrp.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrp.hdb
new file mode 100755
index 0000000..093f3cf
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrp.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrs.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrs.cdb
new file mode 100755
index 0000000..f715ca1
--- /dev/null
+++ b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrs.cdb
diff --git a/part_2/ex9_final/output_files/ex9.asm.rpt b/part_2/ex9_final/output_files/ex9.asm.rpt
new file mode 100755
index 0000000..3fcae64
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex9

+Fri Nov 25 12:11:08 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Assembler Summary

+  3. Assembler Settings

+  4. Assembler Generated Files

+  5. Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof

+  6. Assembler Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------+

+; Assembler Summary                                             ;

++-----------------------+---------------------------------------+

+; Assembler Status      ; Successful - Fri Nov 25 12:11:08 2016 ;

+; Revision Name         ; ex9                                   ;

+; Top-level Entity Name ; ex9                                   ;

+; Family                ; Cyclone V                             ;

+; Device                ; 5CSEMA5F31C6                          ;

++-----------------------+---------------------------------------+

+

+

++----------------------------------+

+; Assembler Settings               ;

++--------+---------+---------------+

+; Option ; Setting ; Default Value ;

++--------+---------+---------------+

+

+

++----------------------------------------+

+; Assembler Generated Files              ;

++----------------------------------------+

+; File Name                              ;

++----------------------------------------+

+; C:/New folder/ex9/output_files/ex9.sof ;

++----------------------------------------+

+

+

++------------------------------------------------------------------+

+; Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof ;

++----------------+-------------------------------------------------+

+; Option         ; Setting                                         ;

++----------------+-------------------------------------------------+

+; Device         ; 5CSEMA5F31C6                                    ;

+; JTAG usercode  ; 0x00B4D80C                                      ;

+; Checksum       ; 0x00B4D80C                                      ;

++----------------+-------------------------------------------------+

+

+

++--------------------+

+; Assembler Messages ;

++--------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Assembler

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 12:11:02 2016

+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (115030): Assembler is generating device programming files

+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 895 megabytes

+    Info: Processing ended: Fri Nov 25 12:11:08 2016

+    Info: Elapsed time: 00:00:06

+    Info: Total CPU time (on all processors): 00:00:06

+

+

diff --git a/part_2/ex9_final/output_files/ex9.done b/part_2/ex9_final/output_files/ex9.done
new file mode 100755
index 0000000..42f2bb6
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.done
@@ -0,0 +1 @@
+Fri Nov 25 12:11:16 2016

diff --git a/part_2/ex9_final/output_files/ex9.fit.rpt b/part_2/ex9_final/output_files/ex9.fit.rpt
new file mode 100755
index 0000000..06c3ae1
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.fit.rpt
@@ -0,0 +1,2129 @@
+Fitter report for ex9

+Fri Nov 25 12:11:01 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Fitter Summary

+  3. Fitter Settings

+  4. Parallel Compilation

+  5. I/O Assignment Warnings

+  6. Fitter Netlist Optimizations

+  7. Ignored Assignments

+  8. Incremental Compilation Preservation Summary

+  9. Incremental Compilation Partition Settings

+ 10. Incremental Compilation Placement Preservation

+ 11. Pin-Out File

+ 12. Fitter Resource Usage Summary

+ 13. Fitter Partition Statistics

+ 14. Input Pins

+ 15. Output Pins

+ 16. I/O Bank Usage

+ 17. All Package Pins

+ 18. Fitter Resource Utilization by Entity

+ 19. Delay Chain Summary

+ 20. Pad To Core Delay Chain Fanout

+ 21. Control Signals

+ 22. Global & Other Fast Signals

+ 23. Routing Usage Summary

+ 24. I/O Rules Summary

+ 25. I/O Rules Details

+ 26. I/O Rules Matrix

+ 27. Fitter Device Options

+ 28. Operating Settings and Conditions

+ 29. Estimated Delay Added for Hold Timing Summary

+ 30. Estimated Delay Added for Hold Timing Details

+ 31. Fitter Messages

+ 32. Fitter Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Fitter Summary                                                                    ;

++---------------------------------+-------------------------------------------------+

+; Fitter Status                   ; Successful - Fri Nov 25 12:11:01 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex9                                             ;

+; Top-level Entity Name           ; ex9                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;

+; Total registers                 ; 95                                              ;

+; Total pins                      ; 57 / 457 ( 12 % )                               ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Settings                                                                                                                                            ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Option                                                                     ; Setting                               ; Default Value                         ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;

+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;

+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;

+; Use smart compilation                                                      ; Off                                   ; Off                                   ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;

+; Enable compact report table                                                ; Off                                   ; Off                                   ;

+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;

+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;

+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;

+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;

+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;

+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;

+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;

+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;

+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;

+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;

+; SSN Optimization                                                           ; Off                                   ; Off                                   ;

+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;

+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;

+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;

+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;

+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;

+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;

+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;

+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;

+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;

+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;

+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;

+; Auto Delay Chains                                                          ; On                                    ; On                                    ;

+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;

+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;

+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;

+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;

+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;

+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;

+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;

+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;

+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;

+; Auto Global Clock                                                          ; On                                    ; On                                    ;

+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;

+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;

+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;

+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;

+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;

+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;

+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;

+; Clamping Diode                                                             ; Off                                   ; Off                                   ;

+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;

+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.02        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.9%      ;

+;     Processor 3            ;   0.8%      ;

+;     Processor 4            ;   0.8%      ;

++----------------------------+-------------+

+

+

++-------------------------------------------------+

+; I/O Assignment Warnings                         ;

++----------+--------------------------------------+

+; Pin Name ; Reason                               ;

++----------+--------------------------------------+

+; HEX0[0]  ; Missing drive strength and slew rate ;

+; HEX0[1]  ; Missing drive strength and slew rate ;

+; HEX0[2]  ; Missing drive strength and slew rate ;

+; HEX0[3]  ; Missing drive strength and slew rate ;

+; HEX0[4]  ; Missing drive strength and slew rate ;

+; HEX0[5]  ; Missing drive strength and slew rate ;

+; HEX0[6]  ; Missing drive strength and slew rate ;

+; HEX1[0]  ; Missing drive strength and slew rate ;

+; HEX1[1]  ; Missing drive strength and slew rate ;

+; HEX1[2]  ; Missing drive strength and slew rate ;

+; HEX1[3]  ; Missing drive strength and slew rate ;

+; HEX1[4]  ; Missing drive strength and slew rate ;

+; HEX1[5]  ; Missing drive strength and slew rate ;

+; HEX1[6]  ; Missing drive strength and slew rate ;

+; HEX2[0]  ; Missing drive strength and slew rate ;

+; HEX2[1]  ; Missing drive strength and slew rate ;

+; HEX2[2]  ; Missing drive strength and slew rate ;

+; HEX2[3]  ; Missing drive strength and slew rate ;

+; HEX2[4]  ; Missing drive strength and slew rate ;

+; HEX2[5]  ; Missing drive strength and slew rate ;

+; HEX2[6]  ; Missing drive strength and slew rate ;

+; HEX3[0]  ; Missing drive strength and slew rate ;

+; HEX3[1]  ; Missing drive strength and slew rate ;

+; HEX3[2]  ; Missing drive strength and slew rate ;

+; HEX3[3]  ; Missing drive strength and slew rate ;

+; HEX3[4]  ; Missing drive strength and slew rate ;

+; HEX3[5]  ; Missing drive strength and slew rate ;

+; HEX3[6]  ; Missing drive strength and slew rate ;

+; HEX4[0]  ; Missing drive strength and slew rate ;

+; HEX4[1]  ; Missing drive strength and slew rate ;

+; HEX4[2]  ; Missing drive strength and slew rate ;

+; HEX4[3]  ; Missing drive strength and slew rate ;

+; HEX4[4]  ; Missing drive strength and slew rate ;

+; HEX4[5]  ; Missing drive strength and slew rate ;

+; HEX4[6]  ; Missing drive strength and slew rate ;

+; HEX5[0]  ; Missing drive strength and slew rate ;

+; HEX5[1]  ; Missing drive strength and slew rate ;

+; HEX5[2]  ; Missing drive strength and slew rate ;

+; HEX5[3]  ; Missing drive strength and slew rate ;

+; HEX5[4]  ; Missing drive strength and slew rate ;

+; HEX5[5]  ; Missing drive strength and slew rate ;

+; HEX5[6]  ; Missing drive strength and slew rate ;

+; LEDR[0]  ; Missing drive strength and slew rate ;

+; LEDR[1]  ; Missing drive strength and slew rate ;

+; LEDR[2]  ; Missing drive strength and slew rate ;

+; LEDR[3]  ; Missing drive strength and slew rate ;

+; LEDR[4]  ; Missing drive strength and slew rate ;

+; LEDR[5]  ; Missing drive strength and slew rate ;

+; LEDR[6]  ; Missing drive strength and slew rate ;

+; LEDR[7]  ; Missing drive strength and slew rate ;

+; LEDR[8]  ; Missing drive strength and slew rate ;

+; LEDR[9]  ; Missing drive strength and slew rate ;

++----------+--------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Netlist Optimizations                                                                                                                                                                                                            ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;

+; formula_fsm:FSM|count[6]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[6]~DUPLICATE   ;                  ;                       ;

+; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+

+

++--------------------------------------------------------------------------------------------+

+; Ignored Assignments                                                                        ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;

+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;

+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;

++--------------+----------------+--------------+------------+---------------+----------------+

+

+

++--------------------------------------------------------------------------------------------------+

+; Incremental Compilation Preservation Summary                                                     ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Placement (by node) ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;

+;     -- Achieved     ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;

+;                     ;                    ;                            ;                          ;

+; Routing (by net)    ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

++---------------------+--------------------+----------------------------+--------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Partition Settings                                                                                                                                             ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;

+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Placement Preservation                                                                                     ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Top                            ; 0.00 % ( 0 / 489 )    ; N/A                     ; Source File       ; N/A                 ;       ;

+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+

+

++--------------+

+; Pin-Out File ;

++--------------+

+The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.

+

+

++------------------------------------------------------------------------------------------+

+; Fitter Resource Usage Summary                                                            ;

++-------------------------------------------------------------+--------------------+-------+

+; Resource                                                    ; Usage              ; %     ;

++-------------------------------------------------------------+--------------------+-------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32,070       ; < 1 % ;

+; ALMs needed [=A-B+C]                                        ; 159                ;       ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32,070       ; < 1 % ;

+;         [a] ALMs used for LUT logic and registers           ; 36                 ;       ;

+;         [b] ALMs used for LUT logic                         ; 120                ;       ;

+;         [c] ALMs used for registers                         ; 6                  ;       ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32,070         ; < 1 % ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;

+;         [a] Due to location constrained logic               ; 0                  ;       ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;

+;         [c] Due to LAB input limits                         ; 0                  ;       ;

+;         [d] Due to virtual I/Os                             ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Difficulty packing design                                   ; Low                ;       ;

+;                                                             ;                    ;       ;

+; Total LABs:  partially or completely used                   ; 19 / 3,207         ; < 1 % ;

+;     -- Logic LABs                                           ; 19                 ;       ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Combinational ALUT usage for logic                          ; 290                ;       ;

+;     -- 7 input functions                                    ; 0                  ;       ;

+;     -- 6 input functions                                    ; 41                 ;       ;

+;     -- 5 input functions                                    ; 5                  ;       ;

+;     -- 4 input functions                                    ; 157                ;       ;

+;     -- <=3 input functions                                  ; 87                 ;       ;

+; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;

+; Dedicated logic registers                                   ; 95                 ;       ;

+;     -- By type:                                             ;                    ;       ;

+;         -- Primary logic registers                          ; 84 / 64,140        ; < 1 % ;

+;         -- Secondary logic registers                        ; 11 / 64,140        ; < 1 % ;

+;     -- By function:                                         ;                    ;       ;

+;         -- Design implementation registers                  ; 84                 ;       ;

+;         -- Routing optimization registers                   ; 11                 ;       ;

+;                                                             ;                    ;       ;

+; Virtual pins                                                ; 0                  ;       ;

+; I/O pins                                                    ; 57 / 457           ; 12 %  ;

+;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;

+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Hard processor system peripheral utilization                ;                    ;       ;

+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;

+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;

+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;

+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;

+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;

+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;

+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;

+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;

+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;

+;                                                             ;                    ;       ;

+; Global signals                                              ; 1                  ;       ;

+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;

+; Total MLAB memory bits                                      ; 0                  ;       ;

+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;

+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;

+;                                                             ;                    ;       ;

+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;

+; Global clocks                                               ; 1 / 16             ; 6 %   ;

+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;

+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;

+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;

+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;

+; JTAGs                                                       ; 0 / 1              ; 0 %   ;

+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;

+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;

+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;

+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;

+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;

+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;

+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;

+; Peak interconnect usage (total/H/V)                         ; 2.7% / 3.0% / 1.9% ;       ;

+; Maximum fan-out                                             ; 68                 ;       ;

+; Highest non-global fan-out                                  ; 68                 ;       ;

+; Total fan-out                                               ; 1448               ;       ;

+; Average fan-out                                             ; 2.89               ;       ;

++-------------------------------------------------------------+--------------------+-------+

+

+

++----------------------------------------------------------------------------------------------------------------------+

+; Fitter Partition Statistics                                                                                          ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+; ALMs needed [=A-B+C]                                        ; 159                   ; 0                              ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+;         [a] ALMs used for LUT logic and registers           ; 36                    ; 0                              ;

+;         [b] ALMs used for LUT logic                         ; 120                   ; 0                              ;

+;         [c] ALMs used for registers                         ; 6                     ; 0                              ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;

+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;

+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;

+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Difficulty packing design                                   ; Low                   ; Low                            ;

+;                                                             ;                       ;                                ;

+; Total LABs:  partially or completely used                   ; 19 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;

+;     -- Logic LABs                                           ; 19                    ; 0                              ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Combinational ALUT usage for logic                          ; 290                   ; 0                              ;

+;     -- 7 input functions                                    ; 0                     ; 0                              ;

+;     -- 6 input functions                                    ; 41                    ; 0                              ;

+;     -- 5 input functions                                    ; 5                     ; 0                              ;

+;     -- 4 input functions                                    ; 157                   ; 0                              ;

+;     -- <=3 input functions                                  ; 87                    ; 0                              ;

+; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;

+; Memory ALUT usage                                           ; 0                     ; 0                              ;

+;     -- 64-address deep                                      ; 0                     ; 0                              ;

+;     -- 32-address deep                                      ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Dedicated logic registers                                   ; 0                     ; 0                              ;

+;     -- By type:                                             ;                       ;                                ;

+;         -- Primary logic registers                          ; 84 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;         -- Secondary logic registers                        ; 11 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;     -- By function:                                         ;                       ;                                ;

+;         -- Design implementation registers                  ; 84                    ; 0                              ;

+;         -- Routing optimization registers                   ; 11                    ; 0                              ;

+;                                                             ;                       ;                                ;

+;                                                             ;                       ;                                ;

+; Virtual pins                                                ; 0                     ; 0                              ;

+; I/O pins                                                    ; 57                    ; 0                              ;

+; I/O registers                                               ; 0                     ; 0                              ;

+; Total block memory bits                                     ; 0                     ; 0                              ;

+; Total block memory implementation bits                      ; 0                     ; 0                              ;

+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;

+;                                                             ;                       ;                                ;

+; Connections                                                 ;                       ;                                ;

+;     -- Input Connections                                    ; 0                     ; 0                              ;

+;     -- Registered Input Connections                         ; 0                     ; 0                              ;

+;     -- Output Connections                                   ; 0                     ; 0                              ;

+;     -- Registered Output Connections                        ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Internal Connections                                        ;                       ;                                ;

+;     -- Total Connections                                    ; 1448                  ; 0                              ;

+;     -- Registered Connections                               ; 438                   ; 0                              ;

+;                                                             ;                       ;                                ;

+; External Connections                                        ;                       ;                                ;

+;     -- Top                                                  ; 0                     ; 0                              ;

+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Partition Interface                                         ;                       ;                                ;

+;     -- Input Ports                                          ; 5                     ; 0                              ;

+;     -- Output Ports                                         ; 52                    ; 0                              ;

+;     -- Bidir Ports                                          ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Registered Ports                                            ;                       ;                                ;

+;     -- Registered Input Ports                               ; 0                     ; 0                              ;

+;     -- Registered Output Ports                              ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Port Connectivity                                           ;                       ;                                ;

+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;

+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;

+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;

+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;

+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;

+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;

+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;

+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Input Pins                                                                                                                                                                                                                                                                              ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 27                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+

+

++-----------------------------------------------------------------------------+

+; I/O Bank Usage                                                              ;

++----------+-------------------+---------------+--------------+---------------+

+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;

++----------+-------------------+---------------+--------------+---------------+

+; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;

+; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;

+; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;

+; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;

+; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;

+; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;

+; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

++----------+-------------------+---------------+--------------+---------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; All Package Pins                                                                                                                                                                  ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;

+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;

+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+Note: Pin directions (input, output or bidir) are based on device operating in user mode.

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+; |ex9                       ; 158.5 (0.5)          ; 161.5 (0.5)                      ; 3.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 290 (1)             ; 95 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;

+;    |LFSR:LFSR0|            ; 3.0 (3.0)            ; 3.3 (3.3)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;

+;    |bin2bcd_16:BCD|        ; 67.7 (0.0)           ; 68.0 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 124 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;

+;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;

+;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;

+;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;

+;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;

+;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;

+;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;

+;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;

+;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;

+;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;

+;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;

+;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;

+;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;

+;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;

+;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;

+;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;

+;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;

+;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;

+;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;

+;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;

+;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;

+;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;

+;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;

+;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;

+;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;

+;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;

+;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;

+;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;

+;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;

+;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;

+;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;

+;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 8.6 (8.6)                        ; 0.1 (0.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;

+;    |delay:DEL0|            ; 14.3 (14.3)          ; 15.4 (15.4)                      ; 1.1 (1.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;

+;    |formula_fsm:FSM|       ; 24.5 (24.5)          ; 25.3 (25.3)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 43 (43)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;

+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;

+;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 18.9 (18.9)                      ; 0.4 (0.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Delay Chain Summary                                                                                                     ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; KEY[0]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+

+

++-------------------------------------------------------------------------------+

+; Pad To Core Delay Chain Fanout                                                ;

++-------------------------------------------------+-------------------+---------+

+; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;

++-------------------------------------------------+-------------------+---------+

+; KEY[1]                                          ;                   ;         ;

+; KEY[2]                                          ;                   ;         ;

+; KEY[0]                                          ;                   ;         ;

+;      - counter_16:COUNT0|count~0                ; 1                 ; 0       ;

+; CLOCK_50                                        ;                   ;         ;

+;      - tick_50000:TICK0|CLK_OUT                 ; 1                 ; 0       ;

+; KEY[3]                                          ;                   ;         ;

+;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;

+;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1                 ; 0       ;

+;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;

++-------------------------------------------------+-------------------+---------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Control Signals                                                                                                                                                                ;

++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+; CLOCK_50                            ; PIN_AF14           ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;

+; CLOCK_50                            ; PIN_AF14           ; 26      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;

+; counter_16:COUNT0|count~0           ; LABCELL_X60_Y4_N30 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;

+; counter_16:COUNT0|state             ; FF_X59_Y4_N14      ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;

+; delay:DEL0|count[5]~0               ; LABCELL_X62_Y4_N51 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;

+; delay:DEL0|state.COUNTING           ; FF_X63_Y4_N56      ; 19      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X62_Y4_N56      ; 26      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;

+; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X61_Y4_N2       ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;

+; tick_50000:TICK0|CLK_OUT            ; FF_X60_Y4_N2       ; 68      ; Clock                      ; no     ; --                   ; --               ; --                        ;

++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Global & Other Fast Signals                                                                         ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; CLOCK_50 ; PIN_AF14 ; 26      ; Global Clock         ; GCLK6            ; --                        ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------+

+; Routing Usage Summary                                                 ;

++---------------------------------------------+-------------------------+

+; Routing Resource Type                       ; Usage                   ;

++---------------------------------------------+-------------------------+

+; Block interconnects                         ; 375 / 289,320 ( < 1 % ) ;

+; C12 interconnects                           ; 2 / 13,420 ( < 1 % )    ;

+; C2 interconnects                            ; 132 / 119,108 ( < 1 % ) ;

+; C4 interconnects                            ; 84 / 56,300 ( < 1 % )   ;

+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;

+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;

+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;

+; Direct links                                ; 62 / 289,320 ( < 1 % )  ;

+; Global clocks                               ; 1 / 16 ( 6 % )          ;

+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;

+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;

+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;

+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;

+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;

+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;

+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;

+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;

+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;

+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;

+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;

+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;

+; Local interconnects                         ; 147 / 84,580 ( < 1 % )  ;

+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;

+; R14 interconnects                           ; 25 / 12,676 ( < 1 % )   ;

+; R14/C12 interconnect drivers                ; 26 / 20,720 ( < 1 % )   ;

+; R3 interconnects                            ; 160 / 130,992 ( < 1 % ) ;

+; R6 interconnects                            ; 252 / 266,960 ( < 1 % ) ;

+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;

+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;

++---------------------------------------------+-------------------------+

+

+

++------------------------------------------+

+; I/O Rules Summary                        ;

++----------------------------------+-------+

+; I/O Rules Statistic              ; Total ;

++----------------------------------+-------+

+; Total I/O Rules                  ; 28    ;

+; Number of I/O Rules Passed       ; 6     ;

+; Number of I/O Rules Failed       ; 0     ;

+; Number of I/O Rules Unchecked    ; 0     ;

+; Number of I/O Rules Inapplicable ; 22    ;

++----------------------------------+-------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Details                                                                                                                                                                                                                                                  ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;

+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;

+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;

+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;

+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;

+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Total Pass         ; 57        ; 0            ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Inapplicable ; 0         ; 57           ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ;

+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+

+

++------------------------------------------------------------------------------------------------+

+; Fitter Device Options                                                                          ;

++------------------------------------------------------------------+-----------------------------+

+; Option                                                           ; Setting                     ;

++------------------------------------------------------------------+-----------------------------+

+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;

+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;

+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;

+; Enable INIT_DONE output                                          ; Off                         ;

+; Configuration scheme                                             ; Passive Serial              ;

+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;

+; Enable CvP_CONFDONE pin                                          ; Off                         ;

+; Enable open drain on CRC_ERROR pin                               ; On                          ;

+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;

+; Enable open drain on INIT_DONE pin                               ; On                          ;

+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;

+; Enable open drain on nCEO pin                                    ; On                          ;

+; Enable Partial Reconfiguration pins                              ; Off                         ;

+; Enable input tri-state on active configuration pins in user mode ; Off                         ;

+; Enable internal scrubbing                                        ; Off                         ;

+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;

+; Device initialization clock source                               ; Internal Oscillator         ;

+; Configuration via Protocol                                       ; Off                         ;

+; Configuration Voltage Level                                      ; Auto                        ;

+; Force Configuration Voltage Level                                ; Off                         ;

+; Enable nCEO output                                               ; Off                         ;

+; Data[15..8]                                                      ; Unreserved                  ;

+; Data[7..5]                                                       ; Unreserved                  ;

+; Base pin-out file on sameframe device                            ; Off                         ;

++------------------------------------------------------------------+-----------------------------+

+

+

++------------------------------------+

+; Operating Settings and Conditions  ;

++---------------------------+--------+

+; Setting                   ; Value  ;

++---------------------------+--------+

+; Nominal Core Voltage      ; 1.10 V ;

+; Low Junction Temperature  ; 0 °C   ;

+; High Junction Temperature ; 85 °C  ;

++---------------------------+--------+

+

+

++-------------------------------------------------------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Summary                                                               ;

++--------------------------------------------------------------+--------------------------+-------------------+

+; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;

++--------------------------------------------------------------+--------------------------+-------------------+

+; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 62.3              ;

+; CLOCK_50                                                     ; CLOCK_50                 ; 9.8               ;

+; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.7               ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 3.2               ;

+; tick_50000:TICK0|CLK_OUT,I/O                                 ; tick_50000:TICK0|CLK_OUT ; 1.6               ;

++--------------------------------------------------------------+--------------------------+-------------------+

+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.

+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.

+

+

++--------------------------------------------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Details                                                    ;

++----------------------------------------+-------------------------------------+-------------------+

+; Source Register                        ; Destination Register                ; Delay Added in ns ;

++----------------------------------------+-------------------------------------+-------------------+

+; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[3]             ; 2.057             ;

+; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE               ; 1.568             ;

+; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT            ; 1.369             ;

+; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT            ; 1.341             ;

+; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;

+; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;

+; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT            ; 1.267             ;

+; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT            ; 1.232             ;

+; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT            ; 1.227             ;

+; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT            ; 1.224             ;

+; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT            ; 1.214             ;

+; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT            ; 1.207             ;

+; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT            ; 1.206             ;

+; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT            ; 1.192             ;

+; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT            ; 1.189             ;

+; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT            ; 1.170             ;

+; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT            ; 1.169             ;

+; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT            ; 1.155             ;

+; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                ; 0.995             ;

+; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|count[1]            ; 0.879             ;

+; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|count[5]            ; 0.876             ;

+; formula_fsm:FSM|count[9]               ; formula_fsm:FSM|count[5]            ; 0.866             ;

+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[3]             ; 0.865             ;

+; delay:DEL0|state.IDLE                  ; delay:DEL0|state.COUNTING           ; 0.863             ;

+; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|count[1]            ; 0.855             ;

+; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|count[5]            ; 0.852             ;

+; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                ; 0.851             ;

+; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                ; 0.848             ;

+; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                ; 0.836             ;

+; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                ; 0.833             ;

+; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                ; 0.830             ;

+; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; KEY[3]                                 ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; delay:DEL0|state.TIME_OUT              ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;

+; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                ; 0.820             ;

+; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE               ; 0.805             ;

+; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|count[1]            ; 0.801             ;

+; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                ; 0.800             ;

+; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE               ; 0.784             ;

+; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                ; 0.779             ;

+; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|count[10]           ; 0.751             ;

+; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                ; 0.743             ;

+; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|count[1]            ; 0.743             ;

+; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|count[1]            ; 0.743             ;

+; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|count[1]            ; 0.743             ;

+; formula_fsm:FSM|count[10]              ; formula_fsm:FSM|count[5]            ; 0.741             ;

+; formula_fsm:FSM|count[11]              ; formula_fsm:FSM|count[5]            ; 0.741             ;

+; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                ; 0.720             ;

+; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                ; 0.714             ;

+; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                ; 0.714             ;

+; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;

+; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;

+; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                ; 0.673             ;

+; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                 ; 0.631             ;

+; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                 ; 0.626             ;

+; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                 ; 0.613             ;

+; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                 ; 0.613             ;

+; LFSR:LFSR0|COUNT[2]                    ; delay:DEL0|count[8]                 ; 0.610             ;

+; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]         ; 0.249             ;

+; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]         ; 0.239             ;

+; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]         ; 0.238             ;

+; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]         ; 0.237             ;

+; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]         ; 0.236             ;

+; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]         ; 0.236             ;

+; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]         ; 0.232             ;

+; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]         ; 0.231             ;

+; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]         ; 0.228             ;

+; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]         ; 0.227             ;

+; counter_16:COUNT0|state                ; counter_16:COUNT0|state             ; 0.140             ;

+; KEY[0]                                 ; counter_16:COUNT0|state             ; 0.089             ;

+; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]         ; 0.053             ;

+; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]         ; 0.047             ;

+; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]         ; 0.046             ;

+; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]         ; 0.043             ;

+; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]         ; 0.043             ;

+; tick_50000:TICK0|CLK_OUT               ; counter_16:COUNT0|state             ; 0.036             ;

++----------------------------------------+-------------------------------------+-------------------+

+Note: This table only shows the top 86 path(s) that have the largest delay added for hold.

+

+

++-----------------+

+; Fitter Messages ;

++-----------------+

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

+Info (184020): Starting Fitter periphery placement operations

+Info (11191): Automatically promoted 1 clock (1 global)

+    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6

+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

+Info (176233): Starting register packing

+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332144): No user constrained base clocks found in the design

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.

+Info (176235): Finished register packing

+    Extra Info (176219): No registers were packed into other blocks

+Warning (15705): Ignored locations or region assignments to the following nodes

+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design

+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11

+Info (170189): Fitter placement preparation operations beginning

+Info (14951): The Fitter is using Advanced Physical Optimization.

+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01

+Info (170191): Fitter placement operations beginning

+Info (170137): Fitter placement was successful

+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02

+Info (170193): Fitter routing operations beginning

+Info (170195): Router estimated average interconnect usage is 0% of the available device resources

+    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10

+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.

+    Info (170201): Optimizations that may affect the design's routability were skipped

+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02

+Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03

+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

+Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg

+Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings

+    Info: Peak virtual memory: 2592 megabytes

+    Info: Processing ended: Fri Nov 25 12:11:01 2016

+    Info: Elapsed time: 00:00:34

+    Info: Total CPU time (on all processors): 00:01:01

+

+

++----------------------------+

+; Fitter Suppressed Messages ;

++----------------------------+

+The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.fit.smsg.

+

+

diff --git a/part_2/ex9_final/output_files/ex9.fit.smsg b/part_2/ex9_final/output_files/ex9.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing

+Extra Info (176237): Finished Fast Input/Output/OE register processing

+Extra Info (176238): Start inferring scan chains for DSP blocks

+Extra Info (176239): Inferring scan chains for DSP blocks is complete

+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density

+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

diff --git a/part_2/ex9_final/output_files/ex9.fit.summary b/part_2/ex9_final/output_files/ex9.fit.summary
new file mode 100755
index 0000000..34358c6
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Fri Nov 25 12:11:01 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex9

+Top-level Entity Name : ex9

+Family : Cyclone V

+Device : 5CSEMA5F31C6

+Timing Models : Final

+Logic utilization (in ALMs) : 159 / 32,070 ( < 1 % )

+Total registers : 95

+Total pins : 57 / 457 ( 12 % )

+Total virtual pins : 0

+Total block memory bits : 0 / 4,065,280 ( 0 % )

+Total RAM Blocks : 0 / 397 ( 0 % )

+Total DSP Blocks : 0 / 87 ( 0 % )

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0 / 6 ( 0 % )

+Total DLLs : 0 / 4 ( 0 % )

diff --git a/part_2/ex9_final/output_files/ex9.flow.rpt b/part_2/ex9_final/output_files/ex9.flow.rpt
new file mode 100755
index 0000000..f4ca16c
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.flow.rpt
@@ -0,0 +1,128 @@
+Flow report for ex9

+Fri Nov 25 12:11:15 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Flow Summary

+  3. Flow Settings

+  4. Flow Non-Default Global Settings

+  5. Flow Elapsed Time

+  6. Flow OS Summary

+  7. Flow Log

+  8. Flow Messages

+  9. Flow Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Flow Summary                                                                      ;

++---------------------------------+-------------------------------------------------+

+; Flow Status                     ; Successful - Fri Nov 25 12:11:08 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex9                                             ;

+; Top-level Entity Name           ; ex9                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;

+; Total registers                 ; 95                                              ;

+; Total pins                      ; 57 / 457 ( 12 % )                               ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++-----------------------------------------+

+; Flow Settings                           ;

++-------------------+---------------------+

+; Option            ; Setting             ;

++-------------------+---------------------+

+; Start date & time ; 11/25/2016 12:10:16 ;

+; Main task         ; Compilation         ;

+; Revision Name     ; ex9                 ;

++-------------------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------+

+; Flow Non-Default Global Settings                                                                                       ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; COMPILER_SIGNATURE_ID               ; 260248564297095.148007581608608       ; --            ; --          ; --         ;

+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;

+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;

+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;

+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;

+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;

+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;

+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;

+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------+

+; Flow Elapsed Time                                                                                                             ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 898 MB              ; 00:00:22                           ;

+; Fitter                    ; 00:00:34     ; 1.0                     ; 2592 MB             ; 00:01:01                           ;

+; Assembler                 ; 00:00:06     ; 1.0                     ; 894 MB              ; 00:00:06                           ;

+; TimeQuest Timing Analyzer ; 00:00:06     ; 1.1                     ; 1213 MB             ; 00:00:06                           ;

+; Total                     ; 00:00:56     ; --                      ; --                  ; 00:01:35                           ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+

+

++----------------------------------------------------------------------------------------+

+; Flow OS Summary                                                                        ;

++---------------------------+------------------+-----------+------------+----------------+

+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;

++---------------------------+------------------+-----------+------------+----------------+

+; Analysis & Synthesis      ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; Fitter                    ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; Assembler                 ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; TimeQuest Timing Analyzer ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

++---------------------------+------------------+-----------+------------+----------------+

+

+

+------------

+; Flow Log ;

+------------

+quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9

+quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9

+quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9

+quartus_sta ex9 -c ex9

+

+

+

diff --git a/part_2/ex9_final/output_files/ex9.jdi b/part_2/ex9_final/output_files/ex9.jdi
new file mode 100755
index 0000000..98be503
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>

+  <project>

+    <hash md5_digest_80b="a5a1d44468e3c5ecef42"/>

+  </project>

+  <file_info>

+    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>

+  </file_info>

+</sld_project_info>

diff --git a/part_2/ex9_final/output_files/ex9.map.rpt b/part_2/ex9_final/output_files/ex9.map.rpt
new file mode 100755
index 0000000..363df6b
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.map.rpt
@@ -0,0 +1,615 @@
+Analysis & Synthesis report for ex9

+Fri Nov 25 12:10:26 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Analysis & Synthesis Summary

+  3. Analysis & Synthesis Settings

+  4. Parallel Compilation

+  5. Analysis & Synthesis Source Files Read

+  6. Analysis & Synthesis Resource Usage Summary

+  7. Analysis & Synthesis Resource Utilization by Entity

+  8. State Machine - |ex9|delay:DEL0|state

+  9. State Machine - |ex9|formula_fsm:FSM|state

+ 10. User-Specified and Inferred Latches

+ 11. Registers Removed During Synthesis

+ 12. General Register Statistics

+ 13. Inverted Register Statistics

+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)

+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0

+ 16. Parameter Settings for User Entity Instance: formula_fsm:FSM

+ 17. Parameter Settings for User Entity Instance: delay:DEL0

+ 18. Parameter Settings for User Entity Instance: counter_16:COUNT0

+ 19. Port Connectivity Checks: "hex_to_7seg:SEG5"

+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"

+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"

+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"

+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"

+ 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"

+ 25. Port Connectivity Checks: "delay:DEL0"

+ 26. Post-Synthesis Netlist Statistics for Top Partition

+ 27. Elapsed Time Per Partition

+ 28. Analysis & Synthesis Messages

+ 29. Analysis & Synthesis Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Analysis & Synthesis Summary                                                      ;

++---------------------------------+-------------------------------------------------+

+; Analysis & Synthesis Status     ; Successful - Fri Nov 25 12:10:26 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex9                                             ;

+; Top-level Entity Name           ; ex9                                             ;

+; Family                          ; Cyclone V                                       ;

+; Logic utilization (in ALMs)     ; N/A                                             ;

+; Total registers                 ; 84                                              ;

+; Total pins                      ; 57                                              ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0                                               ;

+; Total DSP Blocks                ; 0                                               ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0                                               ;

+; Total DLLs                      ; 0                                               ;

++---------------------------------+-------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Settings                                                                                             ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Option                                                                          ; Setting            ; Default Value      ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;

+; Top-level entity name                                                           ; ex9                ; ex9                ;

+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;

+; Use smart compilation                                                           ; Off                ; Off                ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;

+; Enable compact report table                                                     ; Off                ; Off                ;

+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;

+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;

+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;

+; Preserve fewer node names                                                       ; On                 ; On                 ;

+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;

+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;

+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;

+; State Machine Processing                                                        ; Auto               ; Auto               ;

+; Safe State Machine                                                              ; Off                ; Off                ;

+; Extract Verilog State Machines                                                  ; On                 ; On                 ;

+; Extract VHDL State Machines                                                     ; On                 ; On                 ;

+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;

+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;

+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;

+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;

+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;

+; Parallel Synthesis                                                              ; On                 ; On                 ;

+; DSP Block Balancing                                                             ; Auto               ; Auto               ;

+; NOT Gate Push-Back                                                              ; On                 ; On                 ;

+; Power-Up Don't Care                                                             ; On                 ; On                 ;

+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;

+; Remove Duplicate Registers                                                      ; On                 ; On                 ;

+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;

+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;

+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;

+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;

+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;

+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;

+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;

+; Optimization Technique                                                          ; Balanced           ; Balanced           ;

+; Carry Chain Length                                                              ; 70                 ; 70                 ;

+; Auto Carry Chains                                                               ; On                 ; On                 ;

+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;

+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;

+; Auto ROM Replacement                                                            ; On                 ; On                 ;

+; Auto RAM Replacement                                                            ; On                 ; On                 ;

+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;

+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;

+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;

+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;

+; Strict RAM Replacement                                                          ; Off                ; Off                ;

+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;

+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;

+; Auto Resource Sharing                                                           ; Off                ; Off                ;

+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;

+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;

+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;

+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;

+; Report Parameter Settings                                                       ; On                 ; On                 ;

+; Report Source Assignments                                                       ; On                 ; On                 ;

+; Report Connectivity Checks                                                      ; On                 ; On                 ;

+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;

+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;

+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;

+; HDL message level                                                               ; Level2             ; Level2             ;

+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;

+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;

+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;

+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;

+; Clock MUX Protection                                                            ; On                 ; On                 ;

+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;

+; Block Design Naming                                                             ; Auto               ; Auto               ;

+; SDC constraint protection                                                       ; Off                ; Off                ;

+; Synthesis Effort                                                                ; Auto               ; Auto               ;

+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;

+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;

+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;

+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;

+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;

+; Synthesis Seed                                                                  ; 1                  ; 1                  ;

+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;

+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.0%      ;

+;     Processors 3-4         ;   0.0%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Source Files Read                                                                                                ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ; Library ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/tick_50000.v  ;         ;

+; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/LFSR.v        ;         ;

+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/hex_to_7seg.v ;         ;

+; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/formula_fsm.v ;         ;

+; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/delay.v       ;         ;

+; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/counter_16.v  ;         ;

+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/bin2bcd_16.v  ;         ;

+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/add3_ge5.v    ;         ;

+; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/ex9.v         ;         ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+

+

++------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Usage Summary                            ;

++---------------------------------------------+--------------------------+

+; Resource                                    ; Usage                    ;

++---------------------------------------------+--------------------------+

+; Estimate of Logic utilization (ALMs needed) ; 166                      ;

+;                                             ;                          ;

+; Combinational ALUT usage for logic          ; 290                      ;

+;     -- 7 input functions                    ; 0                        ;

+;     -- 6 input functions                    ; 41                       ;

+;     -- 5 input functions                    ; 5                        ;

+;     -- 4 input functions                    ; 157                      ;

+;     -- <=3 input functions                  ; 87                       ;

+;                                             ;                          ;

+; Dedicated logic registers                   ; 84                       ;

+;                                             ;                          ;

+; I/O pins                                    ; 57                       ;

+;                                             ;                          ;

+; Total DSP Blocks                            ; 0                        ;

+;                                             ;                          ;

+; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;

+; Maximum fan-out                             ; 67                       ;

+; Total fan-out                               ; 1423                     ;

+; Average fan-out                             ; 2.92                     ;

++---------------------------------------------+--------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+; |ex9                       ; 290 (1)           ; 84 (0)       ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;

+;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;

+;    |bin2bcd_16:BCD|        ; 124 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A10|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;

+;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;

+;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;

+;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;

+;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;

+;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;

+;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;

+;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;

+;       |add3_ge5:A18|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;

+;       |add3_ge5:A19|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;

+;       |add3_ge5:A1|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;

+;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;

+;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;

+;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;

+;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;

+;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;

+;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;

+;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;

+;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;

+;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;

+;       |add3_ge5:A32|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;

+;       |add3_ge5:A33|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;

+;       |add3_ge5:A34|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;

+;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;

+;       |add3_ge5:A3|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;

+;       |add3_ge5:A4|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;

+;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;

+;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;

+;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;

+;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;

+;       |add3_ge5:A9|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;

+;    |counter_16:COUNT0|     ; 17 (17)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;

+;    |delay:DEL0|            ; 25 (25)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;

+;    |formula_fsm:FSM|       ; 43 (43)           ; 25 (25)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;

+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG4|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;

+;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

+Encoding Type:  One-Hot

++--------------------------------------------------------------------------------+

+; State Machine - |ex9|delay:DEL0|state                                          ;

++----------------+----------------+----------------+----------------+------------+

+; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;

++----------------+----------------+----------------+----------------+------------+

+; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;

+; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;

+; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;

+; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;

++----------------+----------------+----------------+----------------+------------+

+

+

+Encoding Type:  One-Hot

++--------------------------------------------------------------------------------------------+

+; State Machine - |ex9|formula_fsm:FSM|state                                                 ;

++------------------------+--------------------+------------------------+---------------------+

+; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;

++------------------------+--------------------+------------------------+---------------------+

+; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;

+; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;

+; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;

++------------------------+--------------------+------------------------+---------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------+

+; User-Specified and Inferred Latches                                                                               ;

++----------------------------------------------------+-------------------------------------+------------------------+

+; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;

++----------------------------------------------------+-------------------------------------+------------------------+

+; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;

+; Number of user-specified and inferred latches = 1  ;                                     ;                        ;

++----------------------------------------------------+-------------------------------------+------------------------+

+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.

+

+

++------------------------------------------------------------+

+; Registers Removed During Synthesis                         ;

++---------------------------------------+--------------------+

+; Register name                         ; Reason for Removal ;

++---------------------------------------+--------------------+

+; delay:DEL0|state~5                    ; Lost fanout        ;

+; delay:DEL0|state~6                    ; Lost fanout        ;

+; Total Number of Removed Registers = 2 ;                    ;

++---------------------------------------+--------------------+

+

+

++------------------------------------------------------+

+; General Register Statistics                          ;

++----------------------------------------------+-------+

+; Statistic                                    ; Value ;

++----------------------------------------------+-------+

+; Total registers                              ; 84    ;

+; Number of registers using Synchronous Clear  ; 16    ;

+; Number of registers using Synchronous Load   ; 15    ;

+; Number of registers using Asynchronous Clear ; 0     ;

+; Number of registers using Asynchronous Load  ; 0     ;

+; Number of registers using Clock Enable       ; 42    ;

+; Number of registers using Preset             ; 0     ;

++----------------------------------------------+-------+

+

+

++---------------------------------------------------+

+; Inverted Register Statistics                      ;

++-----------------------------------------+---------+

+; Inverted Register                       ; Fan out ;

++-----------------------------------------+---------+

+; formula_fsm:FSM|count[1]                ; 2       ;

+; formula_fsm:FSM|count[0]                ; 2       ;

+; formula_fsm:FSM|count[6]                ; 2       ;

+; formula_fsm:FSM|count[7]                ; 2       ;

+; formula_fsm:FSM|count[8]                ; 2       ;

+; formula_fsm:FSM|count[11]               ; 2       ;

+; tick_50000:TICK0|count[14]              ; 2       ;

+; tick_50000:TICK0|count[15]              ; 2       ;

+; tick_50000:TICK0|count[0]               ; 2       ;

+; tick_50000:TICK0|count[1]               ; 2       ;

+; tick_50000:TICK0|count[2]               ; 2       ;

+; tick_50000:TICK0|count[3]               ; 2       ;

+; tick_50000:TICK0|count[6]               ; 2       ;

+; tick_50000:TICK0|count[8]               ; 2       ;

+; tick_50000:TICK0|count[9]               ; 2       ;

+; LFSR:LFSR0|COUNT[1]                     ; 3       ;

+; Total number of inverted registers = 16 ;         ;

++-----------------------------------------+---------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------+

+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+

+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+

+; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[0] ;

+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[5]        ;

+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[13]       ;

+; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |ex9|formula_fsm:FSM|count[0]   ;

+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector3  ;

+; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;

+; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+

+

+

++---------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;

++----------------+-------+--------------------------------------+

+; Parameter Name ; Value ; Type                                 ;

++----------------+-------+--------------------------------------+

+; NBIT           ; 16    ; Signed Integer                       ;

++----------------+-------+--------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++--------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;

++------------------+-------+-----------------------------------+

+; Parameter Name   ; Value ; Type                              ;

++------------------+-------+-----------------------------------+

+; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;

+; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;

+; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;

++------------------+-------+-----------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++---------------------------------------------------------+

+; Parameter Settings for User Entity Instance: delay:DEL0 ;

++----------------+-------+--------------------------------+

+; Parameter Name ; Value ; Type                           ;

++----------------+-------+--------------------------------+

+; BIT_SZ         ; 14    ; Signed Integer                 ;

+; IDLE           ; 00    ; Unsigned Binary                ;

+; COUNTING       ; 01    ; Unsigned Binary                ;

+; TIME_OUT       ; 10    ; Unsigned Binary                ;

+; WAIT_LOW       ; 11    ; Unsigned Binary                ;

++----------------+-------+--------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++----------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;

++----------------+-------+---------------------------------------+

+; Parameter Name ; Value ; Type                                  ;

++----------------+-------+---------------------------------------+

+; BIT_SZ         ; 16    ; Signed Integer                        ;

+; COUNTING       ; 1     ; Unsigned Binary                       ;

+; IDLE           ; 0     ; Unsigned Binary                       ;

++----------------+-------+---------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++----------------------------------------------+

+; Port Connectivity Checks: "hex_to_7seg:SEG5" ;

++------+-------+----------+--------------------+

+; Port ; Type  ; Severity ; Details            ;

++------+-------+----------+--------------------+

+; in   ; Input ; Info     ; Stuck at GND       ;

++------+-------+----------+--------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+; Port  ; Type   ; Severity ; Details                                                                             ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;

+; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+

+

++---------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;

++-------+-------+----------+------------------------------+

+; Port  ; Type  ; Severity ; Details                      ;

++-------+-------+----------+------------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                 ;

++-------+-------+----------+------------------------------+

+

+

++---------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;

++-------+-------+----------+------------------------------+

+; Port  ; Type  ; Severity ; Details                      ;

++-------+-------+----------+------------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                 ;

++-------+-------+----------+------------------------------+

+

+

++--------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;

++-------+-------+----------+-----------------------------+

+; Port  ; Type  ; Severity ; Details                     ;

++-------+-------+----------+-----------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                ;

++-------+-------+----------+-----------------------------+

+

+

++--------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;

++-------+-------+----------+-----------------------------+

+; Port  ; Type  ; Severity ; Details                     ;

++-------+-------+----------+-----------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                ;

++-------+-------+----------+-----------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; Port ; Type  ; Severity ; Details                                                                                                                                     ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------+

+; Post-Synthesis Netlist Statistics for Top Partition ;

++-----------------------+-----------------------------+

+; Type                  ; Count                       ;

++-----------------------+-----------------------------+

+; arriav_ff             ; 84                          ;

+;     ENA               ; 12                          ;

+;     ENA SCLR          ; 16                          ;

+;     ENA SLD           ; 14                          ;

+;     SLD               ; 1                           ;

+;     plain             ; 41                          ;

+; arriav_lcell_comb     ; 308                         ;

+;     arith             ; 58                          ;

+;         1 data inputs ; 58                          ;

+;     normal            ; 250                         ;

+;         0 data inputs ; 2                           ;

+;         1 data inputs ; 28                          ;

+;         2 data inputs ; 8                           ;

+;         3 data inputs ; 9                           ;

+;         4 data inputs ; 157                         ;

+;         5 data inputs ; 5                           ;

+;         6 data inputs ; 41                          ;

+; boundary_port         ; 57                          ;

+;                       ;                             ;

+; Max LUT depth         ; 15.00                       ;

+; Average LUT depth     ; 7.32                        ;

++-----------------------+-----------------------------+

+

+

++-------------------------------+

+; Elapsed Time Per Partition    ;

++----------------+--------------+

+; Partition Name ; Elapsed Time ;

++----------------+--------------+

+; Top            ; 00:00:00     ;

++----------------+--------------+

+

+

++-------------------------------+

+; Analysis & Synthesis Messages ;

++-------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Analysis & Synthesis

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 12:10:16 2016

+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v

+    Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex9/verilog_files/tick_50000.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v

+    Info (12023): Found entity 1: LFSR File: C:/New folder/ex9/verilog_files/LFSR.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v

+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex9/verilog_files/hex_to_7seg.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v

+    Info (12023): Found entity 1: formula_fsm File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v

+    Info (12023): Found entity 1: delay File: C:/New folder/ex9/verilog_files/delay.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v

+    Info (12023): Found entity 1: counter_16 File: C:/New folder/ex9/verilog_files/counter_16.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v

+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 12

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v

+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex9/verilog_files/add3_ge5.v Line: 9

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v

+    Info (12023): Found entity 1: ex9 File: C:/New folder/ex9/verilog_files/ex9.v Line: 1

+Info (12127): Elaborating entity "ex9" for the top level hierarchy

+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 14

+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: C:/New folder/ex9/verilog_files/ex9.v Line: 16

+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 39

+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 58

+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 58

+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 18

+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 20

+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: C:/New folder/ex9/verilog_files/delay.v Line: 24

+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 22

+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: C:/New folder/ex9/verilog_files/ex9.v Line: 24

+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 26

+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 26

+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder

+Warning (13024): Output pins are stuck at VCC or GND

+    Warning (13410): Pin "HEX5[0]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[1]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[2]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[3]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[4]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[5]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+Info (286030): Timing-Driven Synthesis is running

+Info (17049): 2 registers lost all their fanouts during netlist optimizations.

+Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg

+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

+Warning (21074): Design contains 2 input pin(s) that do not drive logic

+    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4

+    Warning (15610): No output dependent on input pin "KEY[2]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4

+Info (21057): Implemented 354 device resources after synthesis - the final resource count might be different

+    Info (21058): Implemented 5 input pins

+    Info (21059): Implemented 52 output pins

+    Info (21061): Implemented 297 logic cells

+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings

+    Info: Peak virtual memory: 898 megabytes

+    Info: Processing ended: Fri Nov 25 12:10:26 2016

+    Info: Elapsed time: 00:00:10

+    Info: Total CPU time (on all processors): 00:00:22

+

+

++------------------------------------------+

+; Analysis & Synthesis Suppressed Messages ;

++------------------------------------------+

+The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.map.smsg.

+

+

diff --git a/part_2/ex9_final/output_files/ex9.map.smsg b/part_2/ex9_final/output_files/ex9.map.smsg
new file mode 100755
index 0000000..e17538c
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.map.smsg
@@ -0,0 +1,38 @@
+Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 38

+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: C:/New folder/ex9/verilog_files/delay.v Line: 7

+Warning (10268): Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/counter_16.v Line: 16

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

diff --git a/part_2/ex9_final/output_files/ex9.map.summary b/part_2/ex9_final/output_files/ex9.map.summary
new file mode 100755
index 0000000..87824a5
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Fri Nov 25 12:10:26 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex9

+Top-level Entity Name : ex9

+Family : Cyclone V

+Logic utilization (in ALMs) : N/A

+Total registers : 84

+Total pins : 57

+Total virtual pins : 0

+Total block memory bits : 0

+Total DSP Blocks : 0

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0

+Total DLLs : 0

diff --git a/part_2/ex9_final/output_files/ex9.pin b/part_2/ex9_final/output_files/ex9.pin
new file mode 100755
index 0000000..6b2c6db
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+ -- Your use of Altera Corporation's design tools, logic functions 

+ -- and other software and tools, and its AMPP partner logic 

+ -- functions, and any output files from any of the foregoing 

+ -- (including device programming or simulation files), and any 

+ -- associated documentation or information are expressly subject 

+ -- to the terms and conditions of the Altera Program License 

+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,

+ -- the Altera MegaCore Function License Agreement, or other 

+ -- applicable license agreement, including, without limitation, 

+ -- that your use is for the sole purpose of programming logic 

+ -- devices manufactured by Altera and sold by Altera or its 

+ -- authorized distributors.  Please refer to the applicable 

+ -- agreement for further details.

+ -- 

+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is

+ -- not intended for use as a Quartus Prime input file. This file cannot be used

+ -- to make Quartus Prime pin assignments - for instructions on how to make pin

+ -- assignments, please see Quartus Prime help.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- NC            : No Connect. This pin has no internal connection to the device.

+ -- DNU           : Do Not Use. This pin MUST NOT be connected.

+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.

+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).

+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC

+ --                 of its bank.

+ --                  Bank 3A:       2.5V

+ --                  Bank 3B:       3.3V

+ --                  Bank 4A:       3.3V

+ --                  Bank 5A:       3.3V

+ --                  Bank 5B:       3.3V

+ --                  Bank 6B:       2.5V

+ --                  Bank 6A:  2.5V

+ --                  Bank 7A:  2.5V

+ --                  Bank 7B:  2.5V

+ --                  Bank 7C:  2.5V

+ --                  Bank 7D:  2.5V

+ --                  Bank 8A:  2.5V

+ -- RREF          : External reference resistor for the quad, MUST be connected to

+ --                 GND via a 2k Ohm resistor.

+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.

+ --                  It can also be used to report unused dedicated pins. The connection

+ --                  on the board for unused dedicated pins depends on whether this will

+ --                  be used in a future design. One example is device migration. When

+ --                  using device migration, refer to the device pin-tables. If it is a

+ --                  GND pin in the pin table or if it will not be used in a future design

+ --                  for another purpose the it MUST be connected to GND. If it is an unused

+ --                  dedicated pin, then it can be connected to a valid signal on the board

+ --                  (low, high, or toggling) if that signal is required for a different

+ --                  revision of the design.

+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.

+ --                  This pin should be connected to GND. It may also be connected  to a

+ --                  valid signal  on the board  (low, high, or toggling)  if that signal

+ --                  is required for a different revision of the design.

+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND

+ --                  or leave it unconnected.

+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.

+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.

+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.

+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.

+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.

+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin

+ --                 must not be connected.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- Pin directions (input, output or bidir) are based on device operating in user mode.

+ ---------------------------------------------------------------------------------

+

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6

+

+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

+-------------------------------------------------------------------------------------------------------------

+GND                          : A2        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                

+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                

+GND                          : A12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                

+GND                          : A17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                

+GND                          : A22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                

+GND                          : A26       :        :                   :         : 7A        :                

+GND                          : A27       : gnd    :                   :         :           :                

+HPS_TRST                     : A28       :        :                   :         : 7A        :                

+HPS_TMS                      : A29       :        :                   :         : 7A        :                

+GND                          : AA1       : gnd    :                   :         :           :                

+GND                          : AA2       : gnd    :                   :         :           :                

+GND                          : AA3       : gnd    :                   :         :           :                

+GND                          : AA4       : gnd    :                   :         :           :                

+VCC                          : AA5       : power  :                   : 1.1V    :           :                

+GND                          : AA6       : gnd    :                   :         :           :                

+DNU                          : AA7       :        :                   :         :           :                

+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                

+GND                          : AA9       : gnd    :                   :         :           :                

+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                

+GND                          : AA11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                

+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                

+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                

+GND                          : AA22      : gnd    :                   :         :           :                

+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                

+HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                

+GND                          : AB1       : gnd    :                   :         :           :                

+GND                          : AB2       : gnd    :                   :         :           :                

+DNU                          : AB3       :        :                   :         :           :                

+DNU                          : AB4       :        :                   :         :           :                

+GND                          : AB5       : gnd    :                   :         :           :                

+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                

+GND                          : AB7       : gnd    :                   :         :           :                

+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                

+TDO                          : AB9       : output :                   :         : 3A        :                

+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                

+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                

+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AB19      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                

+HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                

+HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AB29      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                

+GND                          : AC1       : gnd    :                   :         :           :                

+GND                          : AC2       : gnd    :                   :         :           :                

+GND                          : AC3       : gnd    :                   :         :           :                

+GND                          : AC4       : gnd    :                   :         :           :                

+TCK                          : AC5       : input  :                   :         : 3A        :                

+GND                          : AC6       : gnd    :                   :         :           :                

+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                

+GND                          : AC8       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                

+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                

+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                

+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                

+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AC16      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                

+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                

+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                

+HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AC26      : gnd    :                   :         :           :                

+HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AD1       : gnd    :                   :         :           :                

+GND                          : AD2       : gnd    :                   :         :           :                

+DNU                          : AD3       :        :                   :         :           :                

+DNU                          : AD4       :        :                   :         :           :                

+GND                          : AD5       : gnd    :                   :         :           :                

+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                

+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                

+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                

+DNU                          : AD15      :        :                   :         :           :                

+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                

+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                

+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                

+GND                          : AD23      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                

+HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                

+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AE1       : gnd    :                   :         :           :                

+GND                          : AE2       : gnd    :                   :         :           :                

+GND                          : AE3       : gnd    :                   :         :           :                

+GND                          : AE4       : gnd    :                   :         :           :                

+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                

+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                

+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                

+GND                          : AE10      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                

+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                

+GND                          : AE20      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                

+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                

+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                

+GND                          : AF1       : gnd    :                   :         :           :                

+GND                          : AF2       : gnd    :                   :         :           :                

+GND                          : AF3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                

+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                

+GND                          : AF12      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                

+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                

+GND                          : AF17      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                

+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                

+GND                          : AF27      : gnd    :                   :         :           :                

+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                

+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                

+GND                          : AG9       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                

+GND                          : AG14      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                

+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                

+GND                          : AG24      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                

+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                

+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AH1       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                

+GND                          : AH6       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                

+GND                          : AH11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                

+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                

+GND                          : AH21      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                

+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                

+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                

+GND                          : AJ3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                

+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                

+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                

+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                

+GND                          : AJ18      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                

+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                

+GND                          : AJ28      : gnd    :                   :         :           :                

+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AJ30      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                

+GND                          : AK5       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                

+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                

+GND                          : AK15      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                

+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                

+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                

+GND                          : AK25      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                

+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                

+GND                          : B9        : gnd    :                   :         :           :                

+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                

+GND                          : B14       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                

+GND                          : B19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                

+GND                          : B24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                

+HPS_TDI                      : B27       :        :                   :         : 7A        :                

+HPS_TDO                      : B28       :        :                   :         : 7A        :                

+GND                          : B29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                

+GND                          : C1        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                

+GND                          : C6        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                

+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                

+GND                          : C16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                

+GND                          : C21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                

+GND                          : C26       : gnd    :                   :         :           :                

+HPS_nRST                     : C27       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                

+GND                          : D3        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                

+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                

+GND                          : D13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                

+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                

+GND                          : D23       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                

+HPS_CLK1                     : D25       :        :                   :         : 7A        :                

+GND                          : D26       :        :                   :         : 7A        :                

+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                

+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                

+GND                          : E10       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                

+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                

+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                

+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                

+GND                          : E25       : gnd    :                   :         :           :                

+DNU                          : E26       :        :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                

+GND                          : E30       : gnd    :                   :         :           :                

+DNU                          : F1        :        :                   :         :           :                

+GND                          : F2        : gnd    :                   :         :           :                

+CONF_DONE                    : F3        :        :                   :         : 9A        :                

+nSTATUS                      : F4        :        :                   :         : 9A        :                

+GND                          : F5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                

+GND                          : F7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                

+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                

+GND                          : F17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                

+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                

+HPS_nPOR                     : F23       :        :                   :         : 7A        :                

+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                

+HPS_CLK2                     : F25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                

+GND                          : F27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                

+GND                          : G1        :        :                   :         :           :                

+DNU                          : G2        :        :                   :         :           :                

+GND                          : G3        : gnd    :                   :         :           :                

+GND                          : G4        : gnd    :                   :         :           :                

+nCE                          : G5        :        :                   :         : 9A        :                

+MSEL2                        : G6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                

+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                

+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                

+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                

+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                

+GND                          : G24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                

+GND                          : H1        : gnd    :                   :         :           :                

+GND                          : H2        : gnd    :                   :         :           :                

+DNU                          : H3        :        :                   :         :           :                

+DNU                          : H4        :        :                   :         :           :                

+GND                          : H5        : gnd    :                   :         :           :                

+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                

+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                

+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                

+GND                          : H11       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                

+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                

+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                

+HPS_TCK                      : H22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                

+GND                          : J1        : gnd    :                   :         :           :                

+GND                          : J2        : gnd    :                   :         :           :                

+GND                          : J3        : gnd    :                   :         :           :                

+GND                          : J4        : gnd    :                   :         :           :                

+nCONFIG                      : J5        :        :                   :         : 9A        :                

+GND                          : J6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                

+GND                          : J8        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                

+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                

+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                

+DNU                          : J15       :        :                   :         :           :                

+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                

+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                

+GND                          : J18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                

+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                

+GND                          : J22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                

+GND                          : J28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                

+GND                          : K1        : gnd    :                   :         :           :                

+GND                          : K2        : gnd    :                   :         :           :                

+DNU                          : K3        :        :                   :         :           :                

+DNU                          : K4        :        :                   :         :           :                

+GND                          : K5        : gnd    :                   :         :           :                

+MSEL1                        : K6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                

+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                

+GND                          : K10       : gnd    :                   :         :           :                

+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                

+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                

+GND                          : K15       : gnd    :                   :         :           :                

+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                

+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                

+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                

+GND                          : K20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                

+GND                          : K25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                

+GND                          : L1        : gnd    :                   :         :           :                

+GND                          : L2        : gnd    :                   :         :           :                

+GND                          : L3        : gnd    :                   :         :           :                

+GND                          : L4        : gnd    :                   :         :           :                

+VCC                          : L5        : power  :                   : 1.1V    :           :                

+GND                          : L6        : gnd    :                   :         :           :                

+MSEL3                        : L7        :        :                   :         : 9A        :                

+MSEL0                        : L8        :        :                   :         : 9A        :                

+MSEL4                        : L9        :        :                   :         : 9A        :                

+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                

+GND                          : L11       : gnd    :                   :         :           :                

+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                

+GND                          : L13       : gnd    :                   :         :           :                

+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                

+GND                          : L15       : gnd    :                   :         :           :                

+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                

+GND                          : L17       : gnd    :                   :         :           :                

+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                

+GND                          : L19       : gnd    :                   :         :           :                

+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                

+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                

+GND                          : L22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                

+GND                          : M1        : gnd    :                   :         :           :                

+GND                          : M2        : gnd    :                   :         :           :                

+DNU                          : M3        :        :                   :         :           :                

+DNU                          : M4        :        :                   :         :           :                

+GND                          : M5        : gnd    :                   :         :           :                

+VCC                          : M6        : power  :                   : 1.1V    :           :                

+GND                          : M7        : gnd    :                   :         :           :                

+GND                          : M8        : gnd    :                   :         :           :                

+VCC                          : M9        : power  :                   : 1.1V    :           :                

+GND                          : M10       : gnd    :                   :         :           :                

+VCC                          : M11       : power  :                   : 1.1V    :           :                

+GND                          : M12       : gnd    :                   :         :           :                

+VCC                          : M13       : power  :                   : 1.1V    :           :                

+GND                          : M14       : gnd    :                   :         :           :                

+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                

+GND                          : M16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                

+GND                          : M18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                

+GND                          : M20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                

+GND                          : M29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                

+GND                          : N1        : gnd    :                   :         :           :                

+GND                          : N2        : gnd    :                   :         :           :                

+GND                          : N3        : gnd    :                   :         :           :                

+GND                          : N4        : gnd    :                   :         :           :                

+VCC                          : N5        : power  :                   : 1.1V    :           :                

+GND                          : N6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                

+GND                          : N8        : gnd    :                   :         :           :                

+GND                          : N9        : gnd    :                   :         :           :                

+VCC                          : N10       : power  :                   : 1.1V    :           :                

+GND                          : N11       : gnd    :                   :         :           :                

+VCC                          : N12       : power  :                   : 1.1V    :           :                

+GND                          : N13       : gnd    :                   :         :           :                

+VCC                          : N14       : power  :                   : 1.1V    :           :                

+GND                          : N15       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                

+GND                          : N17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                

+GND                          : N19       : gnd    :                   :         :           :                

+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                

+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                

+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                

+GND                          : N26       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                

+GND                          : P1        : gnd    :                   :         :           :                

+GND                          : P2        : gnd    :                   :         :           :                

+DNU                          : P3        :        :                   :         :           :                

+DNU                          : P4        :        :                   :         :           :                

+GND                          : P5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                

+GND                          : P7        : gnd    :                   :         :           :                

+GND                          : P8        : gnd    :                   :         :           :                

+GND                          : P9        : gnd    :                   :         :           :                

+GND                          : P10       : gnd    :                   :         :           :                

+VCC                          : P11       : power  :                   : 1.1V    :           :                

+GND                          : P12       : gnd    :                   :         :           :                

+VCC                          : P13       : power  :                   : 1.1V    :           :                

+GND                          : P14       : gnd    :                   :         :           :                

+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                

+GND                          : P16       : gnd    :                   :         :           :                

+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                

+GND                          : P18       : gnd    :                   :         :           :                

+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                

+GND                          : P20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                

+GND                          : R1        : gnd    :                   :         :           :                

+GND                          : R2        : gnd    :                   :         :           :                

+GND                          : R3        : gnd    :                   :         :           :                

+GND                          : R4        : gnd    :                   :         :           :                

+VCC                          : R5        : power  :                   : 1.1V    :           :                

+GND                          : R6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                

+GND                          : R8        : gnd    :                   :         :           :                

+GND                          : R9        : gnd    :                   :         :           :                

+VCC                          : R10       : power  :                   : 1.1V    :           :                

+GND                          : R11       : gnd    :                   :         :           :                

+VCC                          : R12       : power  :                   : 1.1V    :           :                

+GND                          : R13       : gnd    :                   :         :           :                

+VCC                          : R14       : power  :                   : 1.1V    :           :                

+GND                          : R15       : gnd    :                   :         :           :                

+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                

+GND                          : R17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                

+GND                          : R30       : gnd    :                   :         :           :                

+GND                          : T1        : gnd    :                   :         :           :                

+GND                          : T2        : gnd    :                   :         :           :                

+DNU                          : T3        :        :                   :         :           :                

+DNU                          : T4        :        :                   :         :           :                

+GND                          : T5        : gnd    :                   :         :           :                

+VCC                          : T6        : power  :                   : 1.1V    :           :                

+GND                          : T7        : gnd    :                   :         :           :                

+GND                          : T8        : gnd    :                   :         :           :                

+GND                          : T9        : gnd    :                   :         :           :                

+GND                          : T10       : gnd    :                   :         :           :                

+VCC                          : T11       : power  :                   : 1.1V    :           :                

+GND                          : T12       : gnd    :                   :         :           :                

+VCC                          : T13       : power  :                   : 1.1V    :           :                

+GND                          : T14       : gnd    :                   :         :           :                

+GND                          : T15       : gnd    :                   :         :           :                

+GND                          : T16       : gnd    :                   :         :           :                

+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                

+GND                          : T18       : gnd    :                   :         :           :                

+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                

+GND                          : T20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                

+GND                          : T27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                

+GND                          : U1        : gnd    :                   :         :           :                

+GND                          : U2        : gnd    :                   :         :           :                

+GND                          : U3        : gnd    :                   :         :           :                

+GND                          : U4        : gnd    :                   :         :           :                

+VCC                          : U5        : power  :                   : 1.1V    :           :                

+GND                          : U6        : gnd    :                   :         :           :                

+DCLK                         : U7        :        :                   :         : 3A        :                

+TDI                          : U8        : input  :                   :         : 3A        :                

+GND                          : U9        : gnd    :                   :         :           :                

+VCC                          : U10       : power  :                   : 1.1V    :           :                

+GND                          : U11       : gnd    :                   :         :           :                

+VCC                          : U12       : power  :                   : 1.1V    :           :                

+GND                          : U13       : gnd    :                   :         :           :                

+VCC                          : U14       : power  :                   : 1.1V    :           :                

+GND                          : U15       : gnd    :                   :         :           :                

+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                

+GND                          : U17       : gnd    :                   :         :           :                

+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                

+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                

+VCC                          : U21       : power  :                   : 1.1V    :           :                

+GND                          : U22       : gnd    :                   :         :           :                

+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                

+GND                          : U24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                

+GND                          : U29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                

+GND                          : V1        : gnd    :                   :         :           :                

+GND                          : V2        : gnd    :                   :         :           :                

+DNU                          : V3        :        :                   :         :           :                

+DNU                          : V4        :        :                   :         :           :                

+GND                          : V5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                

+GND                          : V7        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                

+TMS                          : V9        : input  :                   :         : 3A        :                

+GND                          : V10       : gnd    :                   :         :           :                

+VCC                          : V11       : power  :                   : 1.1V    :           :                

+GND                          : V12       : gnd    :                   :         :           :                

+VCC                          : V13       : power  :                   : 1.1V    :           :                

+GND                          : V14       : gnd    :                   :         :           :                

+VCC                          : V15       : power  :                   : 1.1V    :           :                

+LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : V19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                

+GND                          : V21       : gnd    :                   :         :           :                

+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                

+HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                

+HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                

+GND                          : W1        : gnd    :                   :         :           :                

+GND                          : W2        : gnd    :                   :         :           :                

+GND                          : W3        : gnd    :                   :         :           :                

+GND                          : W4        : gnd    :                   :         :           :                

+VCC                          : W5        : power  :                   : 1.1V    :           :                

+GND                          : W6        : gnd    :                   :         :           :                

+GND                          : W7        : gnd    :                   :         :           :                

+GND                          : W8        : gnd    :                   :         :           :                

+GND                          : W9        : gnd    :                   :         :           :                

+VCC                          : W10       : power  :                   : 1.1V    :           :                

+GND                          : W11       : gnd    :                   :         :           :                

+VCC                          : W12       : power  :                   : 1.1V    :           :                

+GND                          : W13       : gnd    :                   :         :           :                

+VCC                          : W14       : power  :                   : 1.1V    :           :                

+KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              

+LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : W18       : gnd    :                   :         :           :                

+LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              

+LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                

+HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                

+GND                          : W28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                

+GND                          : Y1        : gnd    :                   :         :           :                

+GND                          : Y2        : gnd    :                   :         :           :                

+DNU                          : Y3        :        :                   :         :           :                

+DNU                          : Y4        :        :                   :         :           :                

+GND                          : Y5        : gnd    :                   :         :           :                

+VCC                          : Y6        : power  :                   : 1.1V    :           :                

+GND                          : Y7        : gnd    :                   :         :           :                

+GND                          : Y8        : gnd    :                   :         :           :                

+VCC                          : Y9        : power  :                   : 1.1V    :           :                

+GND                          : Y10       : gnd    :                   :         :           :                

+VCC                          : Y11       : power  :                   : 1.1V    :           :                

+GND                          : Y12       : gnd    :                   :         :           :                

+VCC                          : Y13       : power  :                   : 1.1V    :           :                

+GND                          : Y14       : gnd    :                   :         :           :                

+GND                          : Y15       : gnd    :                   :         :           :                

+KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                

+LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : Y20       : gnd    :                   :         :           :                

+LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                

+HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : Y25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                

+HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                

+GND                          : Y30       : gnd    :                   :         :           :                

diff --git a/part_2/ex9_final/output_files/ex9.sld b/part_2/ex9_final/output_files/ex9.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.sld
@@ -0,0 +1 @@
+<sld_project_info/>

diff --git a/part_2/ex9_final/output_files/ex9.sof b/part_2/ex9_final/output_files/ex9.sof
new file mode 100755
index 0000000..a73135f
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.sof
diff --git a/part_2/ex9_final/output_files/ex9.sta.rpt b/part_2/ex9_final/output_files/ex9.sta.rpt
new file mode 100755
index 0000000..49ef994
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.sta.rpt
@@ -0,0 +1,1005 @@
+TimeQuest Timing Analyzer report for ex9

+Fri Nov 25 12:11:15 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. TimeQuest Timing Analyzer Summary

+  3. Parallel Compilation

+  4. Clocks

+  5. Slow 1100mV 85C Model Fmax Summary

+  6. Timing Closure Recommendations

+  7. Slow 1100mV 85C Model Setup Summary

+  8. Slow 1100mV 85C Model Hold Summary

+  9. Slow 1100mV 85C Model Recovery Summary

+ 10. Slow 1100mV 85C Model Removal Summary

+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary

+ 12. Slow 1100mV 85C Model Metastability Summary

+ 13. Slow 1100mV 0C Model Fmax Summary

+ 14. Slow 1100mV 0C Model Setup Summary

+ 15. Slow 1100mV 0C Model Hold Summary

+ 16. Slow 1100mV 0C Model Recovery Summary

+ 17. Slow 1100mV 0C Model Removal Summary

+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary

+ 19. Slow 1100mV 0C Model Metastability Summary

+ 20. Fast 1100mV 85C Model Setup Summary

+ 21. Fast 1100mV 85C Model Hold Summary

+ 22. Fast 1100mV 85C Model Recovery Summary

+ 23. Fast 1100mV 85C Model Removal Summary

+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary

+ 25. Fast 1100mV 85C Model Metastability Summary

+ 26. Fast 1100mV 0C Model Setup Summary

+ 27. Fast 1100mV 0C Model Hold Summary

+ 28. Fast 1100mV 0C Model Recovery Summary

+ 29. Fast 1100mV 0C Model Removal Summary

+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary

+ 31. Fast 1100mV 0C Model Metastability Summary

+ 32. Multicorner Timing Analysis Summary

+ 33. Board Trace Model Assignments

+ 34. Input Transition Times

+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)

+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)

+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)

+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)

+ 39. Setup Transfers

+ 40. Hold Transfers

+ 41. Report TCCS

+ 42. Report RSKM

+ 43. Unconstrained Paths Summary

+ 44. Clock Status Summary

+ 45. Unconstrained Input Ports

+ 46. Unconstrained Output Ports

+ 47. Unconstrained Input Ports

+ 48. Unconstrained Output Ports

+ 49. TimeQuest Timing Analyzer Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------------------------+

+; TimeQuest Timing Analyzer Summary                                               ;

++-----------------------+---------------------------------------------------------+

+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Timing Analyzer       ; TimeQuest                                               ;

+; Revision Name         ; ex9                                                     ;

+; Device Family         ; Cyclone V                                               ;

+; Device Name           ; 5CSEMA5F31C6                                            ;

+; Timing Models         ; Final                                                   ;

+; Delay Model           ; Combined                                                ;

+; Rise/Fall Delays      ; Enabled                                                 ;

++-----------------------+---------------------------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.14        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   4.8%      ;

+;     Processor 3            ;   4.8%      ;

+;     Processor 4            ;   4.7%      ;

++----------------------------+-------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Clocks                                                                                                                                                                                                                                   ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;

+; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+

+

++----------------------------------------------------------------+

+; Slow 1100mV 85C Model Fmax Summary                             ;

++------------+-----------------+--------------------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;

++------------+-----------------+--------------------------+------+

+; 224.11 MHz ; 224.11 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;

+; 328.19 MHz ; 328.19 MHz      ; CLOCK_50                 ;      ;

++------------+-----------------+--------------------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

+----------------------------------

+; Timing Closure Recommendations ;

+----------------------------------

+HTML report is unavailable in plain text report export.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 85C Model Setup Summary                          ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; -3.462 ; -161.413      ;

+; CLOCK_50                            ; -2.047 ; -40.775       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; -1.675        ;

++-------------------------------------+--------+---------------+

+

+

++-------------------------------------------------------------+

+; Slow 1100mV 85C Model Hold Summary                          ;

++-------------------------------------+-------+---------------+

+; Clock                               ; Slack ; End Point TNS ;

++-------------------------------------+-------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; 0.179 ; 0.000         ;

+; CLOCK_50                            ; 0.385 ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.629 ; 0.000         ;

++-------------------------------------+-------+---------------+

+

+

+------------------------------------------

+; Slow 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Slow 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.637 ; -18.132       ;

+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.762       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.459  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------------

+; Slow 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++----------------------------------------------------------------+

+; Slow 1100mV 0C Model Fmax Summary                              ;

++------------+-----------------+--------------------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;

++------------+-----------------+--------------------------+------+

+; 226.45 MHz ; 226.45 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;

+; 300.93 MHz ; 300.93 MHz      ; CLOCK_50                 ;      ;

++------------+-----------------+--------------------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 0C Model Setup Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; -3.416 ; -157.230      ;

+; CLOCK_50                            ; -2.323 ; -41.799       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.568 ; -1.568        ;

++-------------------------------------+--------+---------------+

+

+

++-------------------------------------------------------------+

+; Slow 1100mV 0C Model Hold Summary                           ;

++-------------------------------------+-------+---------------+

+; Clock                               ; Slack ; End Point TNS ;

++-------------------------------------+-------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; 0.193 ; 0.000         ;

+; CLOCK_50                            ; 0.405 ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.501 ; 0.000         ;

++-------------------------------------+-------+---------------+

+

+

+-----------------------------------------

+; Slow 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Slow 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.689 ; -16.816       ;

+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.286       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.412  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+----------------------------------------------

+; Slow 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Setup Summary                          ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; -1.794 ; -79.872       ;

+; CLOCK_50                            ; -0.918 ; -13.912       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.572 ; -0.572        ;

++-------------------------------------+--------+---------------+

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Hold Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; -0.020 ; -0.037        ;

+; CLOCK_50                            ; 0.185  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.202  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+------------------------------------------

+; Fast 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Fast 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.740 ; -12.957       ;

+; tick_50000:TICK0|CLK_OUT            ; -0.012 ; -0.190        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.478  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------------

+; Fast 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Setup Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; -1.581 ; -69.264       ;

+; CLOCK_50                            ; -0.868 ; -11.639       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.462 ; -0.462        ;

++-------------------------------------+--------+---------------+

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Hold Summary                            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; tick_50000:TICK0|CLK_OUT            ; -0.021 ; -0.052        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.122  ; 0.000         ;

+; CLOCK_50                            ; 0.177  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------

+; Fast 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Fast 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.789 ; -15.486       ;

+; tick_50000:TICK0|CLK_OUT            ; 0.024  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+----------------------------------------------

+; Fast 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++-----------------------------------------------------------------------------------------------------+

+; Multicorner Timing Analysis Summary                                                                 ;

++--------------------------------------+----------+--------+----------+---------+---------------------+

+; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;

++--------------------------------------+----------+--------+----------+---------+---------------------+

+; Worst-case Slack                     ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.789              ;

+;  CLOCK_50                            ; -2.323   ; 0.177  ; N/A      ; N/A     ; -0.789              ;

+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.122  ; N/A      ; N/A     ; 0.412               ;

+;  tick_50000:TICK0|CLK_OUT            ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.394              ;

+; Design-wide TNS                      ; -203.863 ; -0.052 ; 0.0      ; 0.0     ; -56.894             ;

+;  CLOCK_50                            ; -41.799  ; 0.000  ; N/A      ; N/A     ; -18.132             ;

+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.000  ; N/A      ; N/A     ; 0.000               ;

+;  tick_50000:TICK0|CLK_OUT            ; -161.413 ; -0.052 ; N/A      ; N/A     ; -38.762             ;

++--------------------------------------+----------+--------+----------+---------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+

+

++-------------------------------------------------------------+

+; Input Transition Times                                      ;

++----------+--------------+-----------------+-----------------+

+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;

++----------+--------------+-----------------+-----------------+

+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

++----------+--------------+-----------------+-----------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------+

+; Setup Transfers                                                                                                       ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

++-----------------------------------------------------------------------------------------------------------------------+

+; Hold Transfers                                                                                                        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

+---------------

+; Report TCCS ;

+---------------

+No dedicated SERDES Transmitter circuitry present in device or used in design

+

+

+---------------

+; Report RSKM ;

+---------------

+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design

+

+

++------------------------------------------------+

+; Unconstrained Paths Summary                    ;

++---------------------------------+-------+------+

+; Property                        ; Setup ; Hold ;

++---------------------------------+-------+------+

+; Illegal Clocks                  ; 0     ; 0    ;

+; Unconstrained Clocks            ; 0     ; 0    ;

+; Unconstrained Input Ports       ; 2     ; 2    ;

+; Unconstrained Input Port Paths  ; 20    ; 20   ;

+; Unconstrained Output Ports      ; 45    ; 45   ;

+; Unconstrained Output Port Paths ; 500   ; 500  ;

++---------------------------------+-------+------+

+

+

++------------------------------------------------------------------------------------------------+

+; Clock Status Summary                                                                           ;

++-------------------------------------+-------------------------------------+------+-------------+

+; Target                              ; Clock                               ; Type ; Status      ;

++-------------------------------------+-------------------------------------+------+-------------+

+; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;

++-------------------------------------+-------------------------------------+------+-------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++------------------------------------+

+; TimeQuest Timing Analyzer Messages ;

++------------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime TimeQuest Timing Analyzer

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 12:11:09 2016

+Info: Command: quartus_sta ex9 -c ex9

+Info: qsta_default_script.tcl version: #1

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"

+Info (332105): Deriving Clocks

+    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT

+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50

+    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON

+Info: Analyzing Slow 1100mV 85C Model

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -3.462

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -3.462            -161.413 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -2.047             -40.775 CLOCK_50 

+    Info (332119):    -1.675              -1.675 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is 0.179

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.179               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.385               0.000 CLOCK_50 

+    Info (332119):     0.629               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.637

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.637             -18.132 CLOCK_50 

+    Info (332119):    -0.394             -38.762 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.459               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Slow 1100mV 0C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -3.416

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -3.416            -157.230 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -2.323             -41.799 CLOCK_50 

+    Info (332119):    -1.568              -1.568 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is 0.193

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):     0.193               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.405               0.000 CLOCK_50 

+    Info (332119):     0.501               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.689

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.689             -16.816 CLOCK_50 

+    Info (332119):    -0.394             -38.286 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.412               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Fast 1100mV 85C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -1.794

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -1.794             -79.872 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.918             -13.912 CLOCK_50 

+    Info (332119):    -0.572              -0.572 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is -0.020

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.020              -0.037 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.185               0.000 CLOCK_50 

+    Info (332119):     0.202               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.740

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.740             -12.957 CLOCK_50 

+    Info (332119):    -0.012              -0.190 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.478               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Fast 1100mV 0C Model

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -1.581

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -1.581             -69.264 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.868             -11.639 CLOCK_50 

+    Info (332119):    -0.462              -0.462 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is -0.021

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.021              -0.052 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.122               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+    Info (332119):     0.177               0.000 CLOCK_50 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.789

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.789             -15.486 CLOCK_50 

+    Info (332119):     0.024               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.468               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332102): Design is not fully constrained for setup requirements

+Info (332102): Design is not fully constrained for hold requirements

+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings

+    Info: Peak virtual memory: 1213 megabytes

+    Info: Processing ended: Fri Nov 25 12:11:15 2016

+    Info: Elapsed time: 00:00:06

+    Info: Total CPU time (on all processors): 00:00:06

+

+

diff --git a/part_2/ex9_final/output_files/ex9.sta.summary b/part_2/ex9_final/output_files/ex9.sta.summary
new file mode 100755
index 0000000..87e925d
--- /dev/null
+++ b/part_2/ex9_final/output_files/ex9.sta.summary
@@ -0,0 +1,149 @@
+------------------------------------------------------------

+TimeQuest Timing Analyzer Summary

+------------------------------------------------------------

+

+Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -3.462

+TNS   : -161.413

+

+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'

+Slack : -2.047

+TNS   : -40.775

+

+Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -1.675

+TNS   : -1.675

+

+Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.179

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'

+Slack : 0.385

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.629

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.637

+TNS   : -18.132

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.394

+TNS   : -38.762

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.459

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -3.416

+TNS   : -157.230

+

+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'

+Slack : -2.323

+TNS   : -41.799

+

+Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -1.568

+TNS   : -1.568

+

+Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.193

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'

+Slack : 0.405

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.501

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.689

+TNS   : -16.816

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.394

+TNS   : -38.286

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.412

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -1.794

+TNS   : -79.872

+

+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'

+Slack : -0.918

+TNS   : -13.912

+

+Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -0.572

+TNS   : -0.572

+

+Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.020

+TNS   : -0.037

+

+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'

+Slack : 0.185

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.202

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.740

+TNS   : -12.957

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.012

+TNS   : -0.190

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.478

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -1.581

+TNS   : -69.264

+

+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'

+Slack : -0.868

+TNS   : -11.639

+

+Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -0.462

+TNS   : -0.462

+

+Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.021

+TNS   : -0.052

+

+Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.122

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'

+Slack : 0.177

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.789

+TNS   : -15.486

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.024

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.468

+TNS   : 0.000

+

+------------------------------------------------------------

diff --git a/part_2/ex9_final/verilog_files/LFSR.v b/part_2/ex9_final/verilog_files/LFSR.v
new file mode 100755
index 0000000..46140b2
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/LFSR.v
@@ -0,0 +1,18 @@
+module LFSR(CLK, en, COUNT);

+

+	input CLK;

+	input en;

+	

+	output [7:1] COUNT;

+	

+	reg [7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		if(en == 1'b1)

+			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		else

+			COUNT <= COUNT;

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/LFSR.v.bak b/part_2/ex9_final/verilog_files/LFSR.v.bak
new file mode 100755
index 0000000..89ec82a
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/LFSR.v.bak
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);

+	input CLK;

+	output[7:1] COUNT;

+	reg[7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/add3_ge5.v b/part_2/ex9_final/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..a3cd6a9
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/add3_ge5.v
@@ -0,0 +1,34 @@
+//------------------------------

+// Module name: add3_ge5

+// Function: Add 3 to input if it is 5 or above

+// Creator:  Peter Cheung

+// Version:  1.0

+// Date:     21 Jan 2014

+//------------------------------

+

+module add3_ge5(iW,oA);

+

+ input [3:0] iW; 

+ output reg [3:0] oA;  

+ 

+	always @ (iW)

+		case (iW) 

+		//****** input <5, pass to output unchanged ******

+			4'b0000: oA <= 4'b0000; 

+			4'b0001: oA <= 4'b0001; 

+			4'b0010: oA <= 4'b0010; 

+			4'b0011: oA <= 4'b0011; 

+			4'b0100: oA <= 4'b0100;

+			

+		//****** input >=5, output = input + 3	******	

+			4'b0101: oA <= 4'b1000; 

+			4'b0110: oA <= 4'b1001; 

+			4'b0111: oA <= 4'b1010; 

+			4'b1000: oA <= 4'b1011; 

+			4'b1001: oA <= 4'b1100;

+			4'b1010: oA <= 4'b1101;	

+			4'b1011: oA <= 4'b1110;	

+			4'b1100: oA <= 4'b1111;	

+			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow

+		endcase 

+endmodule

diff --git a/part_2/ex9_final/verilog_files/bin2bcd_16.v b/part_2/ex9_final/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..b25d0bd
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/bin2bcd_16.v
@@ -0,0 +1,109 @@
+//------------------------------

+// Module name: bin2bcd_16

+// Function: Converts a 16-bit binary number to 5 digits BCD

+//            .... it uses a shift-and-add3 algorithm

+// Creator:  Peter Cheung

+// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)

+// Date:     24 Nov 2016

+//------------------------------

+//   For more explanation of how this work, see 

+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment

+

+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+

+	input [15:0]	B;		// binary input number

+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD

+	

+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;

+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;

+	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;

+	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;

+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;

+	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;

+

+	// Instantiate a tree of add3-if-greater than or equal to 5 cells

+	//  ... input is w_n, and output is a_n

+	add3_ge5 A1 (w1,a1);

+	add3_ge5 A2 (w2,a2);

+	add3_ge5 A3 (w3,a3);

+	add3_ge5 A4 (w4,a4);

+	add3_ge5 A5 (w5,a5);

+	add3_ge5 A6 (w6,a6);

+	add3_ge5 A7 (w7,a7);

+	add3_ge5 A8 (w8,a8);

+	add3_ge5 A9 (w9,a9);

+	add3_ge5 A10 (w10,a10);

+	add3_ge5 A11 (w11,a11);

+	add3_ge5 A12 (w12,a12);

+	add3_ge5 A13 (w13,a13);

+	add3_ge5 A14 (w14,a14);

+	add3_ge5 A15 (w15,a15);

+	add3_ge5 A16 (w16,a16);

+	add3_ge5 A17 (w17,a17);

+	add3_ge5 A18 (w18,a18);

+	add3_ge5 A19 (w19,a19);

+	add3_ge5 A20 (w20,a20);

+	add3_ge5 A21 (w21,a21);

+	add3_ge5 A22 (w22,a22);

+	add3_ge5 A23 (w23,a23);

+	add3_ge5 A24 (w24,a24);

+	add3_ge5 A25 (w25,a25);

+	add3_ge5 A26 (w26,a26);

+	add3_ge5 A27 (w27,a27);

+	add3_ge5 A28 (w28,a28);

+	add3_ge5 A29 (w29,a29);

+	add3_ge5 A30 (w30,a30);

+	add3_ge5 A31 (w31,a31);

+	add3_ge5 A32 (w32,a32);

+	add3_ge5 A33 (w33,a33);

+	add3_ge5 A34 (w34,a34);

+	add3_ge5 A35 (w35,a35);

+		

+	// wire the tree of add3 modules together

+	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n

+	assign  w2 = {a1[2:0], B[12]};		

+	assign  w3 = {a2[2:0], B[11]};		

+	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};

+	assign  w5 = {a3[2:0], B[10]};

+	assign  w6 = {a4[2:0], a5[3]};

+	assign  w7 = {a5[2:0], B[9]};

+	assign  w8 = {a6[2:0], a7[3]};

+	assign  w9 = {a7[2:0], B[8]};

+	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};

+	assign  w11 = {a8[2:0], a9[3]};

+	assign  w12 = {a9[2:0], B[7]};

+	assign  w13 = {a10[2:0], a11[3]};

+	assign  w14 = {a11[2:0], a12[3]};

+	assign  w15 = {a12[2:0], B[6]};

+	assign  w16 = {a13[2:0], a14[3]};

+	assign  w17 = {a14[2:0], a15[3]};

+	assign  w18 = {a15[2:0], B[5]};

+	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};

+	assign  w20 = {a16[2:0], a17[3]};

+	assign  w21 = {a17[2:0], a18[3]};

+	assign  w22 = {a18[2:0], B[4]};

+	assign  w23 = {a19[2:0], a20[3]};

+	assign  w24 = {a20[2:0], a21[3]};

+	assign  w25 = {a21[2:0], a22[3]};

+	assign  w26 = {a22[2:0], B[3]};

+	assign  w27 = {a23[2:0], a24[3]};

+	assign  w28 = {a24[2:0], a25[3]};

+	assign  w29 = {a25[2:0], a26[3]};

+	assign  w30 = {a26[2:0], B[2]};

+	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};

+	assign  w32 = {a27[2:0], a28[3]};

+	assign  w33 = {a28[2:0], a29[3]};

+	assign  w34 = {a29[2:0], a30[3]};

+	assign  w35 = {a30[2:0], B[1]};

+	

+	// connect up to four BCD digit outputs	

+	assign BCD_0 = {a35[2:0],B[0]};

+	assign BCD_1 = {a34[2:0],a35[3]};

+	assign BCD_2 = {a33[2:0],a34[3]};

+	assign BCD_3 = {a32[2:0],a33[3]};

+	assign BCD_4 = {a31[2:0],a32[3]};	

+endmodule

+

+	

+	

+

diff --git a/part_2/ex9_final/verilog_files/counter_16.v b/part_2/ex9_final/verilog_files/counter_16.v
new file mode 100755
index 0000000..79c144c
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/counter_16.v
@@ -0,0 +1,31 @@
+module counter_16(clock, start, stop, count);

+

+	parameter BIT_SZ = 16;

+	input clock, start, stop;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	reg state;

+	

+	parameter COUNTING = 1'b1, IDLE = 1'b0;

+	

+	initial count = 0;

+	initial state = IDLE;

+	

+	always @ (posedge clock)

+		case(state)

+			IDLE:

+				if(start == 1'b1)

+					begin

+						count = 0;

+						state = COUNTING;

+					end

+			COUNTING:

+				if(stop == 1'b1)

+					state <= IDLE;

+				else

+					count <= count + 1'b1;

+		endcase

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/counter_16.v.bak b/part_2/ex9_final/verilog_files/counter_16.v.bak
new file mode 100755
index 0000000..c0ec549
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/counter_16.v.bak
@@ -0,0 +1,21 @@
+`timescale 1ns / 100ps

+

+module counter_16(clock,enable,reset,count);

+

+	parameter BIT_SZ = 16;

+	input clock, enable, reset;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		begin

+			if(enable == 1'b1)

+				count <= count + 1'b1;

+			if(reset == 1'b1)

+				count <= 16'b0;

+		end

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/delay.v b/part_2/ex9_final/verilog_files/delay.v
new file mode 100755
index 0000000..a983085
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/delay.v
@@ -0,0 +1,60 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 14;

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+				begin

+					count <= N*128;

+					state <= COUNTING;

+				end

+			COUNTING: 

+				begin

+					if(count == 1'b0)

+						begin

+							state <= TIME_OUT;

+						end

+					else 

+						count <= count - 1'b1;

+				end

+			TIME_OUT: 

+				begin

+					if(trigger == 1'b0)

+						state <= IDLE;

+					else

+						state <= WAIT_LOW;

+				end

+			WAIT_LOW: 

+				if(trigger == 1'b0)

+					state <= IDLE;

+			default: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE:

+					time_out = 1'b0;

+			COUNTING: 

+					time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/delay.v.bak b/part_2/ex9_final/verilog_files/delay.v.bak
new file mode 100755
index 0000000..7b79342
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/delay.v.bak
@@ -0,0 +1,47 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 7

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+		count = N-1'b1;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+					state <= COUNTING;

+			COUNTING: if(count == 1'b0) begin

+					count <= n - 1'b1;

+					state <= TIME_OUT;

+				end

+			TIME_OUT: if(trigger == 1'b0)

+					state <= IDLE;

+				else

+					state <= WAIT_LOW;

+			WAIT_LOW: if(trigger == 1'b0)

+					state <= IDLE;

+			defualt: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE: time_out = 1'b0;

+			COUNTING: time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex8.v b/part_2/ex9_final/verilog_files/ex8.v
new file mode 100755
index 0000000..6ca51d6
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex8.v
@@ -0,0 +1,23 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex8.v.bak b/part_2/ex9_final/verilog_files/ex8.v.bak
new file mode 100755
index 0000000..ac293e7
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex8.v.bak
@@ -0,0 +1 @@
+module ex8(
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex9.v b/part_2/ex9_final/verilog_files/ex9.v
new file mode 100755
index 0000000..15446c2
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex9.v
@@ -0,0 +1,33 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	wire [15:0] count_out;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	

+	formula_fsm FSM(tick_ms, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	

+	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);

+	

+	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	hex_to_7seg SEG3(HEX3, BCD_3);

+	hex_to_7seg SEG4(HEX4, BCD_4);

+	hex_to_7seg SEG5(HEX5, 4'b0);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex9.v.bak b/part_2/ex9_final/verilog_files/ex9.v.bak
new file mode 100755
index 0000000..6ca51d6
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex9.v.bak
@@ -0,0 +1,23 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/formula_fsm.v b/part_2/ex9_final/verilog_files/formula_fsm.v
new file mode 100755
index 0000000..2a79785
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/formula_fsm.v
@@ -0,0 +1,76 @@
+module formula_fsm(clk, trigger, time_out, en_lfsr, start_delay, ledr);

+

+input clk, time_out, trigger;

+output en_lfsr, start_delay;

+output [9:0] ledr;

+

+reg [1:0] state;

+reg led_on, en_lfsr, start_delay;

+reg [9:0] ledr;

+reg [11:0] count;

+

+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;

+

+initial 

+	begin

+		state = WAIT_TRIGGER;

+		en_lfsr = 1'b0;

+		start_delay = 1'b0;

+		count = 12'd2499;

+	end

+

+always @ (posedge clk)

+	case(state)

+		WAIT_TRIGGER: 

+			begin

+				if(trigger == 1'b1)

+					state <= LIGHT_UP_LEDS;

+			end

+		LIGHT_UP_LEDS:

+				if(ledr == 10'h3ff)

+					state <= WAIT_FOR_TIMEOUT;

+		WAIT_FOR_TIMEOUT:

+				if(time_out == 1'b1)

+					 state <= WAIT_TRIGGER;

+		default: ;

+	endcase

+

+always @ (posedge clk)

+	case(state)

+		WAIT_TRIGGER:

+			ledr = 0;

+		LIGHT_UP_LEDS:

+			begin

+				if(count == 1'b0)

+					begin

+						ledr <= {ledr[8:0], 1'b1};

+						count <= 12'd2499;

+					end

+				else

+					begin

+						count <= count - 1'b1;

+					end

+			end

+		default: count <= 12'd2499;

+	endcase

+	

+always @ (*)

+	case(state)

+		WAIT_TRIGGER:

+			begin

+				en_lfsr = 1'b0;

+				start_delay = 1'b0;

+			end

+		LIGHT_UP_LEDS:

+			begin

+				en_lfsr = 1'b1;

+			end

+		WAIT_FOR_TIMEOUT:

+			begin

+				start_delay = 1'b1;

+				en_lfsr = 1'b0;

+			end

+		default: ;

+	endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/formula_fsm.v.bak b/part_2/ex9_final/verilog_files/formula_fsm.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/formula_fsm.v.bak
diff --git a/part_2/ex9_final/verilog_files/hex_to_7seg.v b/part_2/ex9_final/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/ex9_final/verilog_files/tick_2500.v b/part_2/ex9_final/verilog_files/tick_2500.v
new file mode 100755
index 0000000..e75a131
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_2500.v
@@ -0,0 +1,35 @@
+module tick_2500(CLOCK_IN, en, CLK_OUT);

+

+	parameter NBIT = 12;

+	

+	input CLOCK_IN, en;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 12'd2499;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		if(en == 1'b1)

+			begin

+				if(count == 1'b0)

+					begin

+						CLK_OUT <= 1'b1;

+						count <= 12'd2499;

+					end

+				else

+					begin

+						count <= count - 1'b1;

+						CLK_OUT <= 1'b0;

+					end

+			end

+		else 

+			CLK_OUT <= 1'b0;

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/tick_2500.v.bak b/part_2/ex9_final/verilog_files/tick_2500.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_2500.v.bak
diff --git a/part_2/ex9_final/verilog_files/tick_50000.v b/part_2/ex9_final/verilog_files/tick_50000.v
new file mode 100755
index 0000000..7ccc81b
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_50000.v
@@ -0,0 +1,32 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd49999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= 1'b1;

+					count <= 16'd49999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+					CLK_OUT <= 1'b0;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/tick_50000.v.bak b/part_2/ex9_final/verilog_files/tick_50000.v.bak
new file mode 100755
index 0000000..45c4166
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_50000.v.bak
@@ -0,0 +1,31 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd24999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= ~CLK_OUT;

+					count <= 16'd24999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/c5_pin_model_dump.txt b/part_2/ex9_partially_working/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_2/ex9_partially_working/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2

+io_4iomodule_c5_index: 54gpio_index: 465

+io_4iomodule_c5_index: 33gpio_index: 6

+io_4iomodule_c5_index: 51gpio_index: 461

+io_4iomodule_c5_index: 27gpio_index: 10

+io_4iomodule_c5_index: 57gpio_index: 457

+io_4iomodule_c5_index: 34gpio_index: 14

+io_4iomodule_c5_index: 28gpio_index: 453

+io_4iomodule_c5_index: 26gpio_index: 19

+io_4iomodule_c5_index: 47gpio_index: 449

+io_4iomodule_c5_index: 29gpio_index: 22

+io_4iomodule_c5_index: 3gpio_index: 445

+io_4iomodule_c5_index: 16gpio_index: 27

+io_4iomodule_c5_index: 6gpio_index: 441

+io_4iomodule_c5_index: 50gpio_index: 30

+io_4iomodule_c5_index: 35gpio_index: 437

+io_4iomodule_c5_index: 7gpio_index: 35

+io_4iomodule_c5_index: 53gpio_index: 433

+io_4iomodule_c5_index: 12gpio_index: 38

+io_4iomodule_c5_index: 1gpio_index: 429

+io_4iomodule_c5_index: 22gpio_index: 43

+io_4iomodule_c5_index: 8gpio_index: 425

+io_4iomodule_c5_index: 20gpio_index: 46

+io_4iomodule_c5_index: 30gpio_index: 421

+io_4iomodule_c5_index: 2gpio_index: 51

+io_4iomodule_c5_index: 31gpio_index: 417

+io_4iomodule_c5_index: 39gpio_index: 54

+io_4iomodule_c5_index: 18gpio_index: 413

+io_4iomodule_c5_index: 10gpio_index: 59

+io_4iomodule_c5_index: 42gpio_index: 409

+io_4iomodule_c5_index: 5gpio_index: 62

+io_4iomodule_c5_index: 24gpio_index: 405

+io_4iomodule_c5_index: 37gpio_index: 67

+io_4iomodule_c5_index: 13gpio_index: 401

+io_4iomodule_c5_index: 0gpio_index: 70

+io_4iomodule_c5_index: 44gpio_index: 397

+io_4iomodule_c5_index: 38gpio_index: 75

+io_4iomodule_c5_index: 52gpio_index: 393

+io_4iomodule_c5_index: 32gpio_index: 78

+io_4iomodule_c5_index: 56gpio_index: 389

+io_4iomodule_a_index: 13gpio_index: 385

+io_4iomodule_c5_index: 4gpio_index: 83

+io_4iomodule_c5_index: 23gpio_index: 86

+io_4iomodule_a_index: 15gpio_index: 381

+io_4iomodule_a_index: 8gpio_index: 377

+io_4iomodule_c5_index: 46gpio_index: 91

+io_4iomodule_a_index: 5gpio_index: 373

+io_4iomodule_a_index: 11gpio_index: 369

+io_4iomodule_c5_index: 41gpio_index: 94

+io_4iomodule_a_index: 3gpio_index: 365

+io_4iomodule_c5_index: 25gpio_index: 99

+io_4iomodule_a_index: 7gpio_index: 361

+io_4iomodule_c5_index: 9gpio_index: 102

+io_4iomodule_a_index: 0gpio_index: 357

+io_4iomodule_c5_index: 14gpio_index: 107

+io_4iomodule_a_index: 12gpio_index: 353

+io_4iomodule_c5_index: 45gpio_index: 110

+io_4iomodule_c5_index: 17gpio_index: 115

+io_4iomodule_a_index: 4gpio_index: 349

+io_4iomodule_c5_index: 36gpio_index: 118

+io_4iomodule_a_index: 10gpio_index: 345

+io_4iomodule_a_index: 16gpio_index: 341

+io_4iomodule_c5_index: 15gpio_index: 123

+io_4iomodule_a_index: 14gpio_index: 337

+io_4iomodule_c5_index: 43gpio_index: 126

+io_4iomodule_c5_index: 19gpio_index: 131

+io_4iomodule_a_index: 1gpio_index: 333

+io_4iomodule_c5_index: 59gpio_index: 134

+io_4iomodule_a_index: 2gpio_index: 329

+io_4iomodule_a_index: 9gpio_index: 325

+io_4iomodule_c5_index: 48gpio_index: 139

+io_4iomodule_a_index: 6gpio_index: 321

+io_4iomodule_a_index: 17gpio_index: 317

+io_4iomodule_c5_index: 40gpio_index: 142

+io_4iomodule_c5_index: 11gpio_index: 147

+io_4iomodule_c5_index: 58gpio_index: 150

+io_4iomodule_c5_index: 21gpio_index: 155

+io_4iomodule_c5_index: 49gpio_index: 158

+io_4iomodule_h_c5_index: 0gpio_index: 161

+io_4iomodule_h_c5_index: 6gpio_index: 165

+io_4iomodule_h_c5_index: 10gpio_index: 169

+io_4iomodule_h_c5_index: 3gpio_index: 173

+io_4iomodule_h_c5_index: 8gpio_index: 176

+io_4iomodule_h_c5_index: 11gpio_index: 180

+io_4iomodule_h_c5_index: 7gpio_index: 184

+io_4iomodule_h_c5_index: 5gpio_index: 188

+io_4iomodule_h_c5_index: 1gpio_index: 192

+io_4iomodule_h_c5_index: 2gpio_index: 196

+io_4iomodule_h_c5_index: 9gpio_index: 200

+io_4iomodule_h_c5_index: 4gpio_index: 204

+io_4iomodule_h_index: 15gpio_index: 208

+io_4iomodule_h_index: 1gpio_index: 212

+io_4iomodule_h_index: 3gpio_index: 216

+io_4iomodule_h_index: 2gpio_index: 220

+io_4iomodule_h_index: 11gpio_index: 224

+io_4iomodule_vref_h_index: 1gpio_index: 228

+io_4iomodule_h_index: 20gpio_index: 231

+io_4iomodule_h_index: 8gpio_index: 235

+io_4iomodule_h_index: 6gpio_index: 239

+io_4iomodule_h_index: 10gpio_index: 243

+io_4iomodule_h_index: 23gpio_index: 247

+io_4iomodule_h_index: 7gpio_index: 251

+io_4iomodule_h_index: 22gpio_index: 255

+io_4iomodule_h_index: 5gpio_index: 259

+io_4iomodule_h_index: 24gpio_index: 263

+io_4iomodule_h_index: 0gpio_index: 267

+io_4iomodule_h_index: 13gpio_index: 271

+io_4iomodule_h_index: 21gpio_index: 275

+io_4iomodule_h_index: 16gpio_index: 279

+io_4iomodule_vref_h_index: 0gpio_index: 283

+io_4iomodule_h_index: 12gpio_index: 286

+io_4iomodule_h_index: 4gpio_index: 290

+io_4iomodule_h_index: 19gpio_index: 294

+io_4iomodule_h_index: 18gpio_index: 298

+io_4iomodule_h_index: 17gpio_index: 302

+io_4iomodule_h_index: 25gpio_index: 306

+io_4iomodule_h_index: 14gpio_index: 310

+io_4iomodule_h_index: 9gpio_index: 314

diff --git a/part_2/ex9_partially_working/db/.cmp.kpt b/part_2/ex9_partially_working/db/.cmp.kpt
new file mode 100755
index 0000000..65813d1
--- /dev/null
+++ b/part_2/ex9_partially_working/db/.cmp.kpt
diff --git a/part_2/ex9_partially_working/db/ex9.(0).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(0).cnf.cdb
new file mode 100755
index 0000000..94e08e0
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(0).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(0).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(0).cnf.hdb
new file mode 100755
index 0000000..d744dd2
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(0).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(1).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(1).cnf.cdb
new file mode 100755
index 0000000..6fa5bfa
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(1).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(1).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(1).cnf.hdb
new file mode 100755
index 0000000..829c3df
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(1).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(2).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(2).cnf.cdb
new file mode 100755
index 0000000..43aabd2
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(2).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(2).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(2).cnf.hdb
new file mode 100755
index 0000000..a2fe649
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(2).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(3).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(3).cnf.cdb
new file mode 100755
index 0000000..47115a1
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(3).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(3).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(3).cnf.hdb
new file mode 100755
index 0000000..ef27b03
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(3).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(4).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(4).cnf.cdb
new file mode 100755
index 0000000..13f6ae2
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(4).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(4).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(4).cnf.hdb
new file mode 100755
index 0000000..b7d17a9
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(4).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(5).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(5).cnf.cdb
new file mode 100755
index 0000000..53d103c
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(5).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(5).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(5).cnf.hdb
new file mode 100755
index 0000000..01910af
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(5).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(6).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(6).cnf.cdb
new file mode 100755
index 0000000..3c6c09e
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(6).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(6).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(6).cnf.hdb
new file mode 100755
index 0000000..1c167a7
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(6).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(7).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(7).cnf.cdb
new file mode 100755
index 0000000..604867e
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(7).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(7).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(7).cnf.hdb
new file mode 100755
index 0000000..da601fb
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(7).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(8).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(8).cnf.cdb
new file mode 100755
index 0000000..97e595e
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(8).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(8).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(8).cnf.hdb
new file mode 100755
index 0000000..42ab8b5
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(8).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.(9).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(9).cnf.cdb
new file mode 100755
index 0000000..e219d8b
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(9).cnf.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.(9).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(9).cnf.hdb
new file mode 100755
index 0000000..0bbfa6a
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.(9).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.asm.qmsg b/part_2/ex9_partially_working/db/ex9.asm.qmsg
new file mode 100755
index 0000000..6d6746e
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073276145 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073276148 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:27:55 2016 " "Processing started: Fri Nov 25 11:27:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073276148 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480073276148 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480073276148 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480073276920 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480073281460 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073281795 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:28:01 2016 " "Processing ended: Fri Nov 25 11:28:01 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073281795 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073281795 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073281795 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480073281795 ""}

diff --git a/part_2/ex9_partially_working/db/ex9.asm.rdb b/part_2/ex9_partially_working/db/ex9.asm.rdb
new file mode 100755
index 0000000..fbc9bdf
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.asm.rdb
diff --git a/part_2/ex9_partially_working/db/ex9.cbx.xml b/part_2/ex9_partially_working/db/ex9.cbx.xml
new file mode 100755
index 0000000..9156ad4
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex9">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex9_partially_working/db/ex9.cmp.ammdb b/part_2/ex9_partially_working/db/ex9.cmp.ammdb
new file mode 100755
index 0000000..70f3c8b
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp.ammdb
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.bpm b/part_2/ex9_partially_working/db/ex9.cmp.bpm
new file mode 100755
index 0000000..d55aa16
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp.bpm
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.cdb b/part_2/ex9_partially_working/db/ex9.cmp.cdb
new file mode 100755
index 0000000..82368ee
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.hdb b/part_2/ex9_partially_working/db/ex9.cmp.hdb
new file mode 100755
index 0000000..2dfdacd
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.idb b/part_2/ex9_partially_working/db/ex9.cmp.idb
new file mode 100755
index 0000000..79dee8d
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp.idb
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.logdb b/part_2/ex9_partially_working/db/ex9.cmp.logdb
new file mode 100755
index 0000000..b4567d7
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp.logdb
@@ -0,0 +1,96 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex9_partially_working/db/ex9.cmp.rdb b/part_2/ex9_partially_working/db/ex9.cmp.rdb
new file mode 100755
index 0000000..44b0f39
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp.rdb
diff --git a/part_2/ex9_partially_working/db/ex9.cmp_merge.kpt b/part_2/ex9_partially_working/db/ex9.cmp_merge.kpt
new file mode 100755
index 0000000..fdd3bfe
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cmp_merge.kpt
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..5b115d6
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..dce4f6b
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.db_info b/part_2/ex9_partially_working/db/ex9.db_info
new file mode 100755
index 0000000..70adca2
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Fri Nov 25 10:28:00 2016

diff --git a/part_2/ex9_partially_working/db/ex9.fit.qmsg b/part_2/ex9_partially_working/db/ex9.fit.qmsg
new file mode 100755
index 0000000..1ec4c4f
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480073240104 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480073240104 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480073240361 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480073240426 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480073240426 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480073240809 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480073240945 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480073251057 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 28 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480073251162 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480073251162 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073251163 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480073251166 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480073251167 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480073251168 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480073251168 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480073251168 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480073251169 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480073251795 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480073251796 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480073251796 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480073251800 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480073251800 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480073251801 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480073251804 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480073251805 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480073251805 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480073251852 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073251853 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480073256842 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480073257105 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073257935 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480073258972 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480073259841 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073259841 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480073261018 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480073265606 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480073265606 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480073268941 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480073268941 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073268945 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480073270428 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480073270467 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480073270913 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480073270913 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480073271356 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073274070 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480073274322 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480073274384 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2617 " "Peak virtual memory: 2617 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073274841 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:27:54 2016 " "Processing ended: Fri Nov 25 11:27:54 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073274841 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:35 " "Elapsed time: 00:00:35" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073274841 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:03 " "Total CPU time (on all processors): 00:01:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073274841 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480073274841 ""}

diff --git a/part_2/ex9_partially_working/db/ex9.hier_info b/part_2/ex9_partially_working/db/ex9.hier_info
new file mode 100755
index 0000000..c903416
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.hier_info
@@ -0,0 +1,802 @@
+|ex9

+CLOCK_50 => CLOCK_50.IN2

+KEY[0] => _.IN1

+KEY[1] => ~NO_FANOUT~

+KEY[2] => ~NO_FANOUT~

+KEY[3] => _.IN1

+HEX0[0] <= hex_to_7seg:SEG0.port0

+HEX0[1] <= hex_to_7seg:SEG0.port0

+HEX0[2] <= hex_to_7seg:SEG0.port0

+HEX0[3] <= hex_to_7seg:SEG0.port0

+HEX0[4] <= hex_to_7seg:SEG0.port0

+HEX0[5] <= hex_to_7seg:SEG0.port0

+HEX0[6] <= hex_to_7seg:SEG0.port0

+HEX1[0] <= hex_to_7seg:SEG1.port0

+HEX1[1] <= hex_to_7seg:SEG1.port0

+HEX1[2] <= hex_to_7seg:SEG1.port0

+HEX1[3] <= hex_to_7seg:SEG1.port0

+HEX1[4] <= hex_to_7seg:SEG1.port0

+HEX1[5] <= hex_to_7seg:SEG1.port0

+HEX1[6] <= hex_to_7seg:SEG1.port0

+HEX2[0] <= hex_to_7seg:SEG2.port0

+HEX2[1] <= hex_to_7seg:SEG2.port0

+HEX2[2] <= hex_to_7seg:SEG2.port0

+HEX2[3] <= hex_to_7seg:SEG2.port0

+HEX2[4] <= hex_to_7seg:SEG2.port0

+HEX2[5] <= hex_to_7seg:SEG2.port0

+HEX2[6] <= hex_to_7seg:SEG2.port0

+HEX3[0] <= hex_to_7seg:SEG3.port0

+HEX3[1] <= hex_to_7seg:SEG3.port0

+HEX3[2] <= hex_to_7seg:SEG3.port0

+HEX3[3] <= hex_to_7seg:SEG3.port0

+HEX3[4] <= hex_to_7seg:SEG3.port0

+HEX3[5] <= hex_to_7seg:SEG3.port0

+HEX3[6] <= hex_to_7seg:SEG3.port0

+HEX4[0] <= hex_to_7seg:SEG4.port0

+HEX4[1] <= hex_to_7seg:SEG4.port0

+HEX4[2] <= hex_to_7seg:SEG4.port0

+HEX4[3] <= hex_to_7seg:SEG4.port0

+HEX4[4] <= hex_to_7seg:SEG4.port0

+HEX4[5] <= hex_to_7seg:SEG4.port0

+HEX4[6] <= hex_to_7seg:SEG4.port0

+HEX5[0] <= hex_to_7seg:SEG5.port0

+HEX5[1] <= hex_to_7seg:SEG5.port0

+HEX5[2] <= hex_to_7seg:SEG5.port0

+HEX5[3] <= hex_to_7seg:SEG5.port0

+HEX5[4] <= hex_to_7seg:SEG5.port0

+HEX5[5] <= hex_to_7seg:SEG5.port0

+HEX5[6] <= hex_to_7seg:SEG5.port0

+LEDR[0] <= formula_fsm:FSM.port6

+LEDR[1] <= formula_fsm:FSM.port6

+LEDR[2] <= formula_fsm:FSM.port6

+LEDR[3] <= formula_fsm:FSM.port6

+LEDR[4] <= formula_fsm:FSM.port6

+LEDR[5] <= formula_fsm:FSM.port6

+LEDR[6] <= formula_fsm:FSM.port6

+LEDR[7] <= formula_fsm:FSM.port6

+LEDR[8] <= formula_fsm:FSM.port6

+LEDR[9] <= formula_fsm:FSM.port6

+

+

+|ex9|tick_50000:TICK0

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => count[12].CLK

+CLOCK_IN => count[13].CLK

+CLOCK_IN => count[14].CLK

+CLOCK_IN => count[15].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|tick_2500:TICK1

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+en => CLK_OUT.OUTPUTSELECT

+en => count[0].ENA

+en => count[1].ENA

+en => count[2].ENA

+en => count[3].ENA

+en => count[4].ENA

+en => count[5].ENA

+en => count[6].ENA

+en => count[7].ENA

+en => count[8].ENA

+en => count[9].ENA

+en => count[10].ENA

+en => count[11].ENA

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|formula_fsm:FSM

+clk => state~3.DATAIN

+tick => ledr[0]~reg0.CLK

+tick => ledr[1]~reg0.CLK

+tick => ledr[2]~reg0.CLK

+tick => ledr[3]~reg0.CLK

+tick => ledr[4]~reg0.CLK

+tick => ledr[5]~reg0.CLK

+tick => ledr[6]~reg0.CLK

+tick => ledr[7]~reg0.CLK

+tick => ledr[8]~reg0.CLK

+tick => ledr[9]~reg0.CLK

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE

+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE

+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|LFSR:LFSR0

+CLK => COUNT[1]~reg0.CLK

+CLK => COUNT[2]~reg0.CLK

+CLK => COUNT[3]~reg0.CLK

+CLK => COUNT[4]~reg0.CLK

+CLK => COUNT[5]~reg0.CLK

+CLK => COUNT[6]~reg0.CLK

+CLK => COUNT[7]~reg0.CLK

+en => COUNT[1]~reg0.ENA

+en => COUNT[2]~reg0.ENA

+en => COUNT[3]~reg0.ENA

+en => COUNT[4]~reg0.ENA

+en => COUNT[5]~reg0.ENA

+en => COUNT[6]~reg0.ENA

+en => COUNT[7]~reg0.ENA

+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|delay:DEL0

+clk => count[0].CLK

+clk => count[1].CLK

+clk => count[2].CLK

+clk => count[3].CLK

+clk => count[4].CLK

+clk => count[5].CLK

+clk => count[6].CLK

+clk => count[7].CLK

+clk => count[8].CLK

+clk => count[9].CLK

+clk => count[10].CLK

+clk => count[11].CLK

+clk => count[12].CLK

+clk => count[13].CLK

+clk => state~4.DATAIN

+N[0] => count.DATAB

+N[1] => count.DATAB

+N[2] => count.DATAB

+N[3] => count.DATAB

+N[4] => count.DATAB

+N[5] => count.DATAB

+N[6] => count.DATAB

+N[7] => ~NO_FANOUT~

+N[8] => ~NO_FANOUT~

+N[9] => ~NO_FANOUT~

+N[10] => ~NO_FANOUT~

+N[11] => ~NO_FANOUT~

+N[12] => ~NO_FANOUT~

+N[13] => ~NO_FANOUT~

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector17.IN3

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector14.IN2

+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|counter_16:COUNT0

+clock => count[0]~reg0.CLK

+clock => count[1]~reg0.CLK

+clock => count[2]~reg0.CLK

+clock => count[3]~reg0.CLK

+clock => count[4]~reg0.CLK

+clock => count[5]~reg0.CLK

+clock => count[6]~reg0.CLK

+clock => count[7]~reg0.CLK

+clock => count[8]~reg0.CLK

+clock => count[9]~reg0.CLK

+clock => count[10]~reg0.CLK

+clock => count[11]~reg0.CLK

+clock => count[12]~reg0.CLK

+clock => count[13]~reg0.CLK

+clock => count[14]~reg0.CLK

+clock => count[15]~reg0.CLK

+clock => state.CLK

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => count.OUTPUTSELECT

+start => state.OUTPUTSELECT

+stop => state.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+stop => count.OUTPUTSELECT

+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD

+B[0] => BCD_0[0].DATAIN

+B[1] => w35[0].IN1

+B[2] => w30[0].IN1

+B[3] => w26[0].IN1

+B[4] => w22[0].IN1

+B[5] => w18[0].IN1

+B[6] => w15[0].IN1

+B[7] => w12[0].IN1

+B[8] => w9[0].IN1

+B[9] => w7[0].IN1

+B[10] => w5[0].IN1

+B[11] => w3[0].IN1

+B[12] => w2[0].IN1

+B[13] => w1[0].IN1

+B[14] => w1[1].IN1

+B[15] => w1[2].IN1

+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE

+BCD_0[1] <= add3_ge5:A35.port1

+BCD_0[2] <= add3_ge5:A35.port1

+BCD_0[3] <= add3_ge5:A35.port1

+BCD_1[0] <= add3_ge5:A35.port1

+BCD_1[1] <= add3_ge5:A34.port1

+BCD_1[2] <= add3_ge5:A34.port1

+BCD_1[3] <= add3_ge5:A34.port1

+BCD_2[0] <= add3_ge5:A34.port1

+BCD_2[1] <= add3_ge5:A33.port1

+BCD_2[2] <= add3_ge5:A33.port1

+BCD_2[3] <= add3_ge5:A33.port1

+BCD_3[0] <= add3_ge5:A33.port1

+BCD_3[1] <= add3_ge5:A32.port1

+BCD_3[2] <= add3_ge5:A32.port1

+BCD_3[3] <= add3_ge5:A32.port1

+BCD_4[0] <= add3_ge5:A32.port1

+BCD_4[1] <= add3_ge5:A31.port1

+BCD_4[2] <= add3_ge5:A31.port1

+BCD_4[3] <= add3_ge5:A31.port1

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A1

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A2

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A3

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A4

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A5

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A6

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A7

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A8

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A9

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A10

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A11

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A12

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A13

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A14

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A15

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A16

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A17

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A18

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A19

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A20

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A21

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A22

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A23

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A24

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A25

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A26

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A27

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A28

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A29

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A30

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A31

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A32

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A33

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A34

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|bin2bcd_16:BCD|add3_ge5:A35

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex9|hex_to_7seg:SEG0

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG1

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG2

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG3

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG4

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex9|hex_to_7seg:SEG5

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

diff --git a/part_2/ex9_partially_working/db/ex9.hif b/part_2/ex9_partially_working/db/ex9.hif
new file mode 100755
index 0000000..ae8cd2b
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.hif
diff --git a/part_2/ex9_partially_working/db/ex9.lpc.html b/part_2/ex9_partially_working/db/ex9.lpc.html
new file mode 100755
index 0000000..58bcaf3
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.lpc.html
@@ -0,0 +1,786 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+<TR >

+<TD >SEG5</TD>

+<TD >4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >7</TD>

+<TD >4</TD>

+<TD >4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG4</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG3</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG1</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A35</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A34</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A33</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A32</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A31</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A30</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A29</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A28</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A27</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A26</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A25</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A24</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A23</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A22</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A21</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A20</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A19</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A18</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A17</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A16</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A15</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A14</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A13</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A12</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A11</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A10</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A9</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A8</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A7</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A6</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A5</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A4</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A3</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD</TD>

+<TD >16</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >20</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >COUNT0</TD>

+<TD >3</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >16</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >DEL0</TD>

+<TD >16</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >1</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >LFSR0</TD>

+<TD >2</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >FSM</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >12</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >TICK1</TD>

+<TD >2</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >TICK0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+</TABLE>

diff --git a/part_2/ex9_partially_working/db/ex9.lpc.rdb b/part_2/ex9_partially_working/db/ex9.lpc.rdb
new file mode 100755
index 0000000..fb83048
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.lpc.rdb
diff --git a/part_2/ex9_partially_working/db/ex9.lpc.txt b/part_2/ex9_partially_working/db/ex9.lpc.txt
new file mode 100755
index 0000000..faa2fa4
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.lpc.txt
@@ -0,0 +1,54 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; FSM       ; 4     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; TICK1     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex9_partially_working/db/ex9.map.ammdb b/part_2/ex9_partially_working/db/ex9.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.ammdb
diff --git a/part_2/ex9_partially_working/db/ex9.map.bpm b/part_2/ex9_partially_working/db/ex9.map.bpm
new file mode 100755
index 0000000..d385b51
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.bpm
diff --git a/part_2/ex9_partially_working/db/ex9.map.cdb b/part_2/ex9_partially_working/db/ex9.map.cdb
new file mode 100755
index 0000000..5f3c85f
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.map.hdb b/part_2/ex9_partially_working/db/ex9.map.hdb
new file mode 100755
index 0000000..36281c7
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.map.kpt b/part_2/ex9_partially_working/db/ex9.map.kpt
new file mode 100755
index 0000000..c47755c
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.kpt
diff --git a/part_2/ex9_partially_working/db/ex9.map.logdb b/part_2/ex9_partially_working/db/ex9.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex9_partially_working/db/ex9.map.qmsg b/part_2/ex9_partially_working/db/ex9.map.qmsg
new file mode 100755
index 0000000..8989391
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.qmsg
@@ -0,0 +1,76 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073228337 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073228339 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:27:07 2016 " "Processing started: Fri Nov 25 11:27:07 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073228339 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073228339 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073228339 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480073228782 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480073228783 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237056 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237056 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex9/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237058 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237058 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237059 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237059 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237061 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237061 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073237062 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237062 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237062 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237064 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237064 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237064 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073237067 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237067 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237067 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237068 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237068 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237070 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237071 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237071 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237073 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237073 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480073237102 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237110 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" {  } { { "verilog_files/ex9.v" "TICK1" { Text "C:/New folder/ex9/verilog_files/ex9.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237111 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "C:/New folder/ex9/verilog_files/ex9.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237111 ""}

+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(37) " "Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 37 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480073237112 "|ex9|formula_fsm:FSM"}

+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(47) " "Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480073237112 "|ex9|formula_fsm:FSM"}

+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(47) " "Inferred latch for \"start_delay\" at formula_fsm.v(47)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237112 "|ex9|formula_fsm:FSM"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237113 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237113 ""}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480073237114 "|ex9|delay:DEL0"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 23 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237114 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "C:/New folder/ex9/verilog_files/ex9.v" 25 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237120 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237121 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237126 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480073237674 ""}

+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480073237828 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480073237906 ""}

+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480073238213 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073238238 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480073238326 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073238326 ""}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480073238368 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480073238368 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480073238368 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "353 " "Implemented 353 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480073238369 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480073238369 ""} { "Info" "ICUT_CUT_TM_LCELLS" "296 " "Implemented 296 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480073238369 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480073238369 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073238382 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:27:18 2016 " "Processing ended: Fri Nov 25 11:27:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073238382 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073238382 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073238382 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073238382 ""}

diff --git a/part_2/ex9_partially_working/db/ex9.map.rdb b/part_2/ex9_partially_working/db/ex9.map.rdb
new file mode 100755
index 0000000..1f899bf
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map.rdb
diff --git a/part_2/ex9_partially_working/db/ex9.map_bb.cdb b/part_2/ex9_partially_working/db/ex9.map_bb.cdb
new file mode 100755
index 0000000..3e660c7
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map_bb.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.map_bb.hdb b/part_2/ex9_partially_working/db/ex9.map_bb.hdb
new file mode 100755
index 0000000..cc66873
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map_bb.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.map_bb.logdb b/part_2/ex9_partially_working/db/ex9.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex9_partially_working/db/ex9.pre_map.hdb b/part_2/ex9_partially_working/db/ex9.pre_map.hdb
new file mode 100755
index 0000000..951dff6
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.pre_map.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.root_partition.map.reg_db.cdb b/part_2/ex9_partially_working/db/ex9.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..3bf7dd7
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.root_partition.map.reg_db.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.routing.rdb b/part_2/ex9_partially_working/db/ex9.routing.rdb
new file mode 100755
index 0000000..0d9ff39
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.routing.rdb
diff --git a/part_2/ex9_partially_working/db/ex9.rtlv.hdb b/part_2/ex9_partially_working/db/ex9.rtlv.hdb
new file mode 100755
index 0000000..921d905
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.rtlv.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.rtlv_sg.cdb b/part_2/ex9_partially_working/db/ex9.rtlv_sg.cdb
new file mode 100755
index 0000000..5c35259
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.rtlv_sg.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.rtlv_sg_swap.cdb b/part_2/ex9_partially_working/db/ex9.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..67d09aa
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.rtlv_sg_swap.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.sld_design_entry.sci b/part_2/ex9_partially_working/db/ex9.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.sld_design_entry.sci
diff --git a/part_2/ex9_partially_working/db/ex9.sld_design_entry_dsc.sci b/part_2/ex9_partially_working/db/ex9.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.sld_design_entry_dsc.sci
diff --git a/part_2/ex9_partially_working/db/ex9.smart_action.txt b/part_2/ex9_partially_working/db/ex9.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex9_partially_working/db/ex9.smp_dump.txt b/part_2/ex9_partially_working/db/ex9.smp_dump.txt
new file mode 100755
index 0000000..26e74f6
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.smp_dump.txt
@@ -0,0 +1,13 @@
+

+State Machine - |ex9|delay:DEL0|state

+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 

+state.IDLE 0 0 0 0 

+state.COUNTING 0 0 1 1 

+state.TIME_OUT 0 1 0 1 

+state.WAIT_LOW 1 0 0 1 

+

+State Machine - |ex9|formula_fsm:FSM|state

+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 

+state.WAIT_TRIGGER 0 0 0 

+state.LIGHT_UP_LEDS 1 0 1 

+state.WAIT_FOR_TIMEOUT 1 1 0 

diff --git a/part_2/ex9_partially_working/db/ex9.sta.qmsg b/part_2/ex9_partially_working/db/ex9.sta.qmsg
new file mode 100755
index 0000000..9b5916c
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.sta.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073283247 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073283248 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:28:02 2016 " "Processing started: Fri Nov 25 11:28:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073283248 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283248 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283248 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073283369 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283915 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283915 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283963 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283963 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284462 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284484 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284484 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT " "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284486 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284488 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284498 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073284499 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073284507 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073284527 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284527 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.063 " "Worst-case setup slack is -4.063" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.063             -92.490 CLOCK_50  " "   -4.063             -92.490 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.170            -100.678 tick_50000:TICK0\|CLK_OUT  " "   -3.170            -100.678 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.647             -14.530 tick_2500:TICK1\|CLK_OUT  " "   -1.647             -14.530 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.569              -1.569 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.569              -1.569 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284529 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -2.594 " "Worst-case hold slack is -2.594" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.594              -2.594 CLOCK_50  " "   -2.594              -2.594 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.279               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.279               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.351               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.351               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.556               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.556               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284532 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284534 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284535 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.746 " "Worst-case minimum pulse width slack is -0.746" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.746             -27.464 CLOCK_50  " "   -0.746             -27.464 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -24.429 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -24.429 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.270 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.270 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.461               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.461               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284537 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073284549 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284584 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285483 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285543 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073285550 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285550 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.620 " "Worst-case setup slack is -3.620" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.620             -88.501 CLOCK_50  " "   -3.620             -88.501 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.082             -96.216 tick_50000:TICK0\|CLK_OUT  " "   -3.082             -96.216 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.680             -14.714 tick_2500:TICK1\|CLK_OUT  " "   -1.680             -14.714 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.485              -1.485 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.485              -1.485 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285551 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -2.768 " "Worst-case hold slack is -2.768" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.768              -2.768 CLOCK_50  " "   -2.768              -2.768 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.282               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.282               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.351               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.351               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.430               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.430               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285554 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285556 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285557 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.788 " "Worst-case minimum pulse width slack is -0.788" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.788             -25.568 CLOCK_50  " "   -0.788             -25.568 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -24.417 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -24.417 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.220 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.220 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.471               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.471               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285559 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073285570 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285715 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286487 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286548 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073286550 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286550 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.305 " "Worst-case setup slack is -3.305" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.305             -54.566 CLOCK_50  " "   -3.305             -54.566 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.630             -50.049 tick_50000:TICK0\|CLK_OUT  " "   -1.630             -50.049 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.087              -9.482 tick_2500:TICK1\|CLK_OUT  " "   -1.087              -9.482 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.488              -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.488              -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286552 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.523 " "Worst-case hold slack is -1.523" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.523              -1.523 CLOCK_50  " "   -1.523              -1.523 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.071              -0.328 tick_2500:TICK1\|CLK_OUT  " "   -0.071              -0.328 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.094               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.094               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.134               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.134               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286555 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286556 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286558 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.856 " "Worst-case minimum pulse width slack is -0.856" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.856             -19.710 CLOCK_50  " "   -0.856             -19.710 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.062               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.062               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.127               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.127               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.480               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.480               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286559 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073286571 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286732 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073286734 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286734 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.694 " "Worst-case setup slack is -2.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.694             -44.892 CLOCK_50  " "   -2.694             -44.892 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.427             -42.012 tick_50000:TICK0\|CLK_OUT  " "   -1.427             -42.012 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.980              -8.435 tick_2500:TICK1\|CLK_OUT  " "   -0.980              -8.435 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.386              -0.386 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.386              -0.386 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286736 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.553 " "Worst-case hold slack is -1.553" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.553              -1.553 CLOCK_50  " "   -1.553              -1.553 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.102              -0.665 tick_2500:TICK1\|CLK_OUT  " "   -0.102              -0.665 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.064               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.064               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.081               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.081               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286740 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286741 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286743 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.880 " "Worst-case minimum pulse width slack is -0.880" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.880             -23.155 CLOCK_50  " "   -0.880             -23.155 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.079               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.079               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.135               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.483               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.483               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286744 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073288288 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073288290 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1211 " "Peak virtual memory: 1211 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073288337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:28:08 2016 " "Processing ended: Fri Nov 25 11:28:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073288337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073288337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073288337 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073288337 ""}

diff --git a/part_2/ex9_partially_working/db/ex9.sta.rdb b/part_2/ex9_partially_working/db/ex9.sta.rdb
new file mode 100755
index 0000000..ac225df
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.sta.rdb
diff --git a/part_2/ex9_partially_working/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex9_partially_working/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..0d0089d
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex9_partially_working/db/ex9.tis_db_list.ddb b/part_2/ex9_partially_working/db/ex9.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.tis_db_list.ddb
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_0c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..cdd150e
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_85c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..416a1c9
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_0c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..d97542e
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_85c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..f99fa51
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex9_partially_working/db/ex9.tmw_info b/part_2/ex9_partially_working/db/ex9.tmw_info
new file mode 100755
index 0000000..43e342c
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:01:01

+start_analysis_synthesis:s:00:00:11-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:00:37-start_full_compilation

+start_assembler:s:00:00:07-start_full_compilation

+start_timing_analyzer:s:00:00:06-start_full_compilation

diff --git a/part_2/ex9_partially_working/db/ex9.vpr.ammdb b/part_2/ex9_partially_working/db/ex9.vpr.ammdb
new file mode 100755
index 0000000..b4a4021
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9.vpr.ammdb
diff --git a/part_2/ex9_partially_working/db/ex9_partition_pins.json b/part_2/ex9_partially_working/db/ex9_partition_pins.json
new file mode 100755
index 0000000..701d3b6
--- /dev/null
+++ b/part_2/ex9_partially_working/db/ex9_partition_pins.json
@@ -0,0 +1,201 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "HEX0[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX3[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX4[6]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[0]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[1]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[2]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[3]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[4]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[5]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[6]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[7]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[8]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[9]",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[0]",

+					"strict" : false

+				},

+				{

+					"name" : "CLOCK_50",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[3]",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/db/prev_cmp_ex9.qmsg b/part_2/ex9_partially_working/db/prev_cmp_ex9.qmsg
new file mode 100755
index 0000000..b29fc79
--- /dev/null
+++ b/part_2/ex9_partially_working/db/prev_cmp_ex9.qmsg
@@ -0,0 +1,57 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073206376 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073206377 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:26:46 2016 " "Processing started: Fri Nov 25 11:26:46 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073206377 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073206377 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073206378 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480073206841 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480073206841 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215181 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215181 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex9/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215183 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215183 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215184 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215184 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215186 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215186 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073215187 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215188 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215188 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215189 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215189 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215189 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073215191 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215191 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215191 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215192 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215192 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215194 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215194 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215194 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215194 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215195 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215195 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215198 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215198 ""}

+{ "Error" "EVRFX_VERI_UNDEF_TOP_PORT" "reset counter_16.v(4) " "Verilog HDL Module Declaration error at counter_16.v(4): top module port \"reset\" is not found in the port list" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 4 0 0 } }  } 0 10206 "Verilog HDL Module Declaration error at %2!s!: top module port \"%1!s!\" is not found in the port list" 0 0 "Analysis & Synthesis" 0 -1 1480073215199 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215215 ""}

+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "836 " "Peak virtual memory: 836 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073215249 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Nov 25 11:26:55 2016 " "Processing ended: Fri Nov 25 11:26:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073215249 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073215249 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073215249 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215249 ""}

+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1  " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215850 ""}

diff --git a/part_2/ex9_partially_working/ex9.qpf b/part_2/ex9_partially_working/ex9.qpf
new file mode 100755
index 0000000..28b4ce8
--- /dev/null
+++ b/part_2/ex9_partially_working/ex9.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 10:28:00  November 25, 2016

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "16.0"

+DATE = "10:28:00  November 25, 2016"

+

+# Revisions

+

+PROJECT_REVISION = "ex9"

diff --git a/part_2/ex9_partially_working/ex9.qsf b/part_2/ex9_partially_working/ex9.qsf
new file mode 100755
index 0000000..fbba305
--- /dev/null
+++ b/part_2/ex9_partially_working/ex9.qsf
@@ -0,0 +1,275 @@
+#============================================================

+# CLOCK

+#============================================================

+set_location_assignment PIN_AF14 -to CLOCK_50

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50

+

+#============================================================

+# Add-on Card Interface Pins

+#============================================================

+set_location_assignment PIN_AJ20 -to PWM_OUT

+set_location_assignment PIN_AK21 -to DAC_LD

+set_location_assignment PIN_AD20 -to DAC_CS

+set_location_assignment PIN_AF20 -to DAC_SCK

+set_location_assignment PIN_AF21 -to ADC_SCK

+set_location_assignment PIN_AG21 -to ADC_SDI

+set_location_assignment PIN_AG20 -to ADC_CS

+set_location_assignment PIN_AG18 -to DAC_SDI

+set_location_assignment PIN_AJ21 -to ADC_SDO

+set_location_assignment PIN_Y17 -to OLED_CS

+set_location_assignment PIN_Y18 -to OLED_RST

+set_location_assignment PIN_AK18 -to OLED_DC

+set_location_assignment PIN_AJ19 -to OLED_CLK

+set_location_assignment PIN_AJ16 -to OLED_DATA

+

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO

+

+

+#============================================================

+# HEX0

+#============================================================

+set_location_assignment PIN_AE26 -to HEX0[0]

+set_location_assignment PIN_AE27 -to HEX0[1]

+set_location_assignment PIN_AE28 -to HEX0[2]

+set_location_assignment PIN_AG27 -to HEX0[3]

+set_location_assignment PIN_AF28 -to HEX0[4]

+set_location_assignment PIN_AG28 -to HEX0[5]

+set_location_assignment PIN_AH28 -to HEX0[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]

+

+#============================================================

+# HEX1

+#============================================================

+set_location_assignment PIN_AJ29 -to HEX1[0]

+set_location_assignment PIN_AH29 -to HEX1[1]

+set_location_assignment PIN_AH30 -to HEX1[2]

+set_location_assignment PIN_AG30 -to HEX1[3]

+set_location_assignment PIN_AF29 -to HEX1[4]

+set_location_assignment PIN_AF30 -to HEX1[5]

+set_location_assignment PIN_AD27 -to HEX1[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]

+

+#============================================================

+# HEX2

+#============================================================

+set_location_assignment PIN_AB23 -to HEX2[0]

+set_location_assignment PIN_AE29 -to HEX2[1]

+set_location_assignment PIN_AD29 -to HEX2[2]

+set_location_assignment PIN_AC28 -to HEX2[3]

+set_location_assignment PIN_AD30 -to HEX2[4]

+set_location_assignment PIN_AC29 -to HEX2[5]

+set_location_assignment PIN_AC30 -to HEX2[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]

+

+#============================================================

+# HEX3

+#============================================================

+set_location_assignment PIN_AD26 -to HEX3[0]

+set_location_assignment PIN_AC27 -to HEX3[1]

+set_location_assignment PIN_AD25 -to HEX3[2]

+set_location_assignment PIN_AC25 -to HEX3[3]

+set_location_assignment PIN_AB28 -to HEX3[4]

+set_location_assignment PIN_AB25 -to HEX3[5]

+set_location_assignment PIN_AB22 -to HEX3[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]

+

+#============================================================

+# HEX4

+#============================================================

+set_location_assignment PIN_AA24 -to HEX4[0]

+set_location_assignment PIN_Y23 -to HEX4[1]

+set_location_assignment PIN_Y24 -to HEX4[2]

+set_location_assignment PIN_W22 -to HEX4[3]

+set_location_assignment PIN_W24 -to HEX4[4]

+set_location_assignment PIN_V23 -to HEX4[5]

+set_location_assignment PIN_W25 -to HEX4[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]

+

+#============================================================

+# HEX5

+#============================================================

+set_location_assignment PIN_V25 -to HEX5[0]

+set_location_assignment PIN_AA28 -to HEX5[1]

+set_location_assignment PIN_Y27 -to HEX5[2]

+set_location_assignment PIN_AB27 -to HEX5[3]

+set_location_assignment PIN_AB26 -to HEX5[4]

+set_location_assignment PIN_AA26 -to HEX5[5]

+set_location_assignment PIN_AA25 -to HEX5[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]

+

+#============================================================

+# KEY

+#============================================================

+set_location_assignment PIN_AA14 -to KEY[0]

+set_location_assignment PIN_AA15 -to KEY[1]

+set_location_assignment PIN_W15 -to KEY[2]

+set_location_assignment PIN_Y16 -to KEY[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]

+

+#============================================================

+# LEDR

+#============================================================

+set_location_assignment PIN_V16 -to LEDR[0]

+set_location_assignment PIN_W16 -to LEDR[1]

+set_location_assignment PIN_V17 -to LEDR[2]

+set_location_assignment PIN_V18 -to LEDR[3]

+set_location_assignment PIN_W17 -to LEDR[4]

+set_location_assignment PIN_W19 -to LEDR[5]

+set_location_assignment PIN_Y19 -to LEDR[6]

+set_location_assignment PIN_W20 -to LEDR[7]

+set_location_assignment PIN_W21 -to LEDR[8]

+set_location_assignment PIN_Y21 -to LEDR[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]

+

+#============================================================

+# SW

+#============================================================

+set_location_assignment PIN_AB12 -to SW[0]

+set_location_assignment PIN_AC12 -to SW[1]

+set_location_assignment PIN_AF9 -to SW[2]

+set_location_assignment PIN_AF10 -to SW[3]

+set_location_assignment PIN_AD11 -to SW[4]

+set_location_assignment PIN_AD12 -to SW[5]

+set_location_assignment PIN_AE11 -to SW[6]

+set_location_assignment PIN_AC9 -to SW[7]

+set_location_assignment PIN_AD10 -to SW[8]

+set_location_assignment PIN_AE12 -to SW[9]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]

+

+#============================================================

+# End of pin and io_standard assignments

+#============================================================# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 10:28:00  November 25, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex9_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex9

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

+set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v

+set_global_assignment -name VERILOG_FILE verilog_files/delay.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name VERILOG_FILE verilog_files/ex9.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/ex9.qsf.bak b/part_2/ex9_partially_working/ex9.qsf.bak
new file mode 100755
index 0000000..d4eef07
--- /dev/null
+++ b/part_2/ex9_partially_working/ex9.qsf.bak
@@ -0,0 +1,65 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, the Altera Quartus Prime License Agreement,

+# the Altera MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Altera and sold by Altera or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+# Date created = 10:28:00  November 25, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex9_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CSEMA5F31C6

+set_global_assignment -name TOP_LEVEL_ENTITY ex9

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

+set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

+set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v

+set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

+set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v

+set_global_assignment -name VERILOG_FILE verilog_files/delay.v

+set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

+set_global_assignment -name VERILOG_FILE verilog_files/ex9.v

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/ex9.qws b/part_2/ex9_partially_working/ex9.qws
new file mode 100755
index 0000000..3d39dd3
--- /dev/null
+++ b/part_2/ex9_partially_working/ex9.qws
diff --git a/part_2/ex9_partially_working/incremental_db/README b/part_2/ex9_partially_working/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.

+

+The compiled_partitions sub-folder contains previous compilation results for each partition.

+As long as this folder is preserved, incremental compilation results from earlier compiles

+can be re-used.  To perform a clean compilation from source files for all partitions, both

+the db and incremental_db folder should be removed.

+

+The imported_partitions sub-folder contains the last imported QXP for each imported partition.

+As long as this folder is preserved, imported partitions will be automatically re-imported

+when the db or incremental_db/compiled_partitions folders are removed.

+

diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.db_info b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.db_info
new file mode 100755
index 0000000..f84b742
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Fri Nov 25 10:41:49 2016

diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
new file mode 100755
index 0000000..84e2e20
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
new file mode 100755
index 0000000..b342ddc
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..7c6e4c6
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..91157f9
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
new file mode 100755
index 0000000..c6a91c8
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..36c8945
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
new file mode 100755
index 0000000..d39bf4a
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.dpi b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
new file mode 100755
index 0000000..6e90988
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..9f6309e
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..b94502f
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
new file mode 100755
index 0000000..ef311d3
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.kpt b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
new file mode 100755
index 0000000..0ea1881
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
new file mode 100755
index 0000000..59e07ca
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
new file mode 100755
index 0000000..aec68a5
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
new file mode 100755
index 0000000..84a30b9
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.opi b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.opi
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
new file mode 100755
index 0000000..59e07ca
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
new file mode 100755
index 0000000..1490a08
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
new file mode 100755
index 0000000..3d14455
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
new file mode 100755
index 0000000..d39bf4a
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..9f6309e
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..b94502f
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
new file mode 100755
index 0000000..ef311d3
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
new file mode 100755
index 0000000..0ea1881
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrp.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrp.hdb
new file mode 100755
index 0000000..4ff0730
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrp.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrs.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrs.cdb
new file mode 100755
index 0000000..7c2db17
--- /dev/null
+++ b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrs.cdb
diff --git a/part_2/ex9_partially_working/output_files/ex9.asm.rpt b/part_2/ex9_partially_working/output_files/ex9.asm.rpt
new file mode 100755
index 0000000..30feebf
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex9

+Fri Nov 25 11:28:01 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Assembler Summary

+  3. Assembler Settings

+  4. Assembler Generated Files

+  5. Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof

+  6. Assembler Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------+

+; Assembler Summary                                             ;

++-----------------------+---------------------------------------+

+; Assembler Status      ; Successful - Fri Nov 25 11:28:01 2016 ;

+; Revision Name         ; ex9                                   ;

+; Top-level Entity Name ; ex9                                   ;

+; Family                ; Cyclone V                             ;

+; Device                ; 5CSEMA5F31C6                          ;

++-----------------------+---------------------------------------+

+

+

++----------------------------------+

+; Assembler Settings               ;

++--------+---------+---------------+

+; Option ; Setting ; Default Value ;

++--------+---------+---------------+

+

+

++----------------------------------------+

+; Assembler Generated Files              ;

++----------------------------------------+

+; File Name                              ;

++----------------------------------------+

+; C:/New folder/ex9/output_files/ex9.sof ;

++----------------------------------------+

+

+

++------------------------------------------------------------------+

+; Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof ;

++----------------+-------------------------------------------------+

+; Option         ; Setting                                         ;

++----------------+-------------------------------------------------+

+; Device         ; 5CSEMA5F31C6                                    ;

+; JTAG usercode  ; 0x00B4745D                                      ;

+; Checksum       ; 0x00B4745D                                      ;

++----------------+-------------------------------------------------+

+

+

++--------------------+

+; Assembler Messages ;

++--------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Assembler

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 11:27:55 2016

+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (115030): Assembler is generating device programming files

+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 896 megabytes

+    Info: Processing ended: Fri Nov 25 11:28:01 2016

+    Info: Elapsed time: 00:00:06

+    Info: Total CPU time (on all processors): 00:00:06

+

+

diff --git a/part_2/ex9_partially_working/output_files/ex9.done b/part_2/ex9_partially_working/output_files/ex9.done
new file mode 100755
index 0000000..893cd81
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.done
@@ -0,0 +1 @@
+Fri Nov 25 11:28:09 2016

diff --git a/part_2/ex9_partially_working/output_files/ex9.fit.rpt b/part_2/ex9_partially_working/output_files/ex9.fit.rpt
new file mode 100755
index 0000000..d5b5f11
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.fit.rpt
@@ -0,0 +1,2131 @@
+Fitter report for ex9

+Fri Nov 25 11:27:54 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Fitter Summary

+  3. Fitter Settings

+  4. Parallel Compilation

+  5. I/O Assignment Warnings

+  6. Fitter Netlist Optimizations

+  7. Ignored Assignments

+  8. Incremental Compilation Preservation Summary

+  9. Incremental Compilation Partition Settings

+ 10. Incremental Compilation Placement Preservation

+ 11. Pin-Out File

+ 12. Fitter Resource Usage Summary

+ 13. Fitter Partition Statistics

+ 14. Input Pins

+ 15. Output Pins

+ 16. I/O Bank Usage

+ 17. All Package Pins

+ 18. Fitter Resource Utilization by Entity

+ 19. Delay Chain Summary

+ 20. Pad To Core Delay Chain Fanout

+ 21. Control Signals

+ 22. Global & Other Fast Signals

+ 23. Routing Usage Summary

+ 24. I/O Rules Summary

+ 25. I/O Rules Details

+ 26. I/O Rules Matrix

+ 27. Fitter Device Options

+ 28. Operating Settings and Conditions

+ 29. Estimated Delay Added for Hold Timing Summary

+ 30. Estimated Delay Added for Hold Timing Details

+ 31. Fitter Messages

+ 32. Fitter Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Fitter Summary                                                                    ;

++---------------------------------+-------------------------------------------------+

+; Fitter Status                   ; Successful - Fri Nov 25 11:27:54 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex9                                             ;

+; Top-level Entity Name           ; ex9                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 154 / 32,070 ( < 1 % )                          ;

+; Total registers                 ; 95                                              ;

+; Total pins                      ; 57 / 457 ( 12 % )                               ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Settings                                                                                                                                            ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Option                                                                     ; Setting                               ; Default Value                         ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;

+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;

+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;

+; Use smart compilation                                                      ; Off                                   ; Off                                   ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;

+; Enable compact report table                                                ; Off                                   ; Off                                   ;

+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;

+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;

+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;

+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;

+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;

+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;

+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;

+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;

+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;

+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;

+; SSN Optimization                                                           ; Off                                   ; Off                                   ;

+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;

+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;

+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;

+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;

+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;

+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;

+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;

+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;

+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;

+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;

+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;

+; Auto Delay Chains                                                          ; On                                    ; On                                    ;

+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;

+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;

+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;

+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;

+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;

+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;

+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;

+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;

+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;

+; Auto Global Clock                                                          ; On                                    ; On                                    ;

+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;

+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;

+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;

+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;

+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;

+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;

+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;

+; Clamping Diode                                                             ; Off                                   ; Off                                   ;

+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;

+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.02        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.7%      ;

+;     Processor 3            ;   0.7%      ;

+;     Processor 4            ;   0.7%      ;

++----------------------------+-------------+

+

+

++-------------------------------------------------+

+; I/O Assignment Warnings                         ;

++----------+--------------------------------------+

+; Pin Name ; Reason                               ;

++----------+--------------------------------------+

+; HEX0[0]  ; Missing drive strength and slew rate ;

+; HEX0[1]  ; Missing drive strength and slew rate ;

+; HEX0[2]  ; Missing drive strength and slew rate ;

+; HEX0[3]  ; Missing drive strength and slew rate ;

+; HEX0[4]  ; Missing drive strength and slew rate ;

+; HEX0[5]  ; Missing drive strength and slew rate ;

+; HEX0[6]  ; Missing drive strength and slew rate ;

+; HEX1[0]  ; Missing drive strength and slew rate ;

+; HEX1[1]  ; Missing drive strength and slew rate ;

+; HEX1[2]  ; Missing drive strength and slew rate ;

+; HEX1[3]  ; Missing drive strength and slew rate ;

+; HEX1[4]  ; Missing drive strength and slew rate ;

+; HEX1[5]  ; Missing drive strength and slew rate ;

+; HEX1[6]  ; Missing drive strength and slew rate ;

+; HEX2[0]  ; Missing drive strength and slew rate ;

+; HEX2[1]  ; Missing drive strength and slew rate ;

+; HEX2[2]  ; Missing drive strength and slew rate ;

+; HEX2[3]  ; Missing drive strength and slew rate ;

+; HEX2[4]  ; Missing drive strength and slew rate ;

+; HEX2[5]  ; Missing drive strength and slew rate ;

+; HEX2[6]  ; Missing drive strength and slew rate ;

+; HEX3[0]  ; Missing drive strength and slew rate ;

+; HEX3[1]  ; Missing drive strength and slew rate ;

+; HEX3[2]  ; Missing drive strength and slew rate ;

+; HEX3[3]  ; Missing drive strength and slew rate ;

+; HEX3[4]  ; Missing drive strength and slew rate ;

+; HEX3[5]  ; Missing drive strength and slew rate ;

+; HEX3[6]  ; Missing drive strength and slew rate ;

+; HEX4[0]  ; Missing drive strength and slew rate ;

+; HEX4[1]  ; Missing drive strength and slew rate ;

+; HEX4[2]  ; Missing drive strength and slew rate ;

+; HEX4[3]  ; Missing drive strength and slew rate ;

+; HEX4[4]  ; Missing drive strength and slew rate ;

+; HEX4[5]  ; Missing drive strength and slew rate ;

+; HEX4[6]  ; Missing drive strength and slew rate ;

+; HEX5[0]  ; Missing drive strength and slew rate ;

+; HEX5[1]  ; Missing drive strength and slew rate ;

+; HEX5[2]  ; Missing drive strength and slew rate ;

+; HEX5[3]  ; Missing drive strength and slew rate ;

+; HEX5[4]  ; Missing drive strength and slew rate ;

+; HEX5[5]  ; Missing drive strength and slew rate ;

+; HEX5[6]  ; Missing drive strength and slew rate ;

+; LEDR[0]  ; Missing drive strength and slew rate ;

+; LEDR[1]  ; Missing drive strength and slew rate ;

+; LEDR[2]  ; Missing drive strength and slew rate ;

+; LEDR[3]  ; Missing drive strength and slew rate ;

+; LEDR[4]  ; Missing drive strength and slew rate ;

+; LEDR[5]  ; Missing drive strength and slew rate ;

+; LEDR[6]  ; Missing drive strength and slew rate ;

+; LEDR[7]  ; Missing drive strength and slew rate ;

+; LEDR[8]  ; Missing drive strength and slew rate ;

+; LEDR[9]  ; Missing drive strength and slew rate ;

++----------+--------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Netlist Optimizations                                                                                                                                                                                                            ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;

+; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[6]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[6]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[7]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[7]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[9]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[9]~DUPLICATE  ;                  ;                       ;

+; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;

+; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;

++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+

+

+

++--------------------------------------------------------------------------------------------+

+; Ignored Assignments                                                                        ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;

++--------------+----------------+--------------+------------+---------------+----------------+

+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;

+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;

+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;

+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;

+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;

+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;

+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;

+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;

+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;

+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;

+; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;

++--------------+----------------+--------------+------------+---------------+----------------+

+

+

++--------------------------------------------------------------------------------------------------+

+; Incremental Compilation Preservation Summary                                                     ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;

++---------------------+--------------------+----------------------------+--------------------------+

+; Placement (by node) ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 487 ) ; 0.00 % ( 0 / 487 )         ; 0.00 % ( 0 / 487 )       ;

+;     -- Achieved     ; 0.00 % ( 0 / 487 ) ; 0.00 % ( 0 / 487 )         ; 0.00 % ( 0 / 487 )       ;

+;                     ;                    ;                            ;                          ;

+; Routing (by net)    ;                    ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

++---------------------+--------------------+----------------------------+--------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Partition Settings                                                                                                                                             ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;

+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Placement Preservation                                                                                     ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Top                            ; 0.00 % ( 0 / 487 )    ; N/A                     ; Source File       ; N/A                 ;       ;

+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+

+

++--------------+

+; Pin-Out File ;

++--------------+

+The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.

+

+

++------------------------------------------------------------------------------------------+

+; Fitter Resource Usage Summary                                                            ;

++-------------------------------------------------------------+--------------------+-------+

+; Resource                                                    ; Usage              ; %     ;

++-------------------------------------------------------------+--------------------+-------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 154 / 32,070       ; < 1 % ;

+; ALMs needed [=A-B+C]                                        ; 154                ;       ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 160 / 32,070       ; < 1 % ;

+;         [a] ALMs used for LUT logic and registers           ; 37                 ;       ;

+;         [b] ALMs used for LUT logic                         ; 117                ;       ;

+;         [c] ALMs used for registers                         ; 6                  ;       ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 6 / 32,070         ; < 1 % ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;

+;         [a] Due to location constrained logic               ; 0                  ;       ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;

+;         [c] Due to LAB input limits                         ; 0                  ;       ;

+;         [d] Due to virtual I/Os                             ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Difficulty packing design                                   ; Low                ;       ;

+;                                                             ;                    ;       ;

+; Total LABs:  partially or completely used                   ; 20 / 3,207         ; < 1 % ;

+;     -- Logic LABs                                           ; 20                 ;       ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Combinational ALUT usage for logic                          ; 287                ;       ;

+;     -- 7 input functions                                    ; 0                  ;       ;

+;     -- 6 input functions                                    ; 23                 ;       ;

+;     -- 5 input functions                                    ; 14                 ;       ;

+;     -- 4 input functions                                    ; 150                ;       ;

+;     -- <=3 input functions                                  ; 100                ;       ;

+; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;

+; Dedicated logic registers                                   ; 95                 ;       ;

+;     -- By type:                                             ;                    ;       ;

+;         -- Primary logic registers                          ; 85 / 64,140        ; < 1 % ;

+;         -- Secondary logic registers                        ; 10 / 64,140        ; < 1 % ;

+;     -- By function:                                         ;                    ;       ;

+;         -- Design implementation registers                  ; 85                 ;       ;

+;         -- Routing optimization registers                   ; 10                 ;       ;

+;                                                             ;                    ;       ;

+; Virtual pins                                                ; 0                  ;       ;

+; I/O pins                                                    ; 57 / 457           ; 12 %  ;

+;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;

+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Hard processor system peripheral utilization                ;                    ;       ;

+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;

+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;

+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;

+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;

+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;

+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;

+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;

+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;

+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;

+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;

+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;

+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;

+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;

+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;

+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;

+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;

+;                                                             ;                    ;       ;

+; Global signals                                              ; 1                  ;       ;

+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;

+; Total MLAB memory bits                                      ; 0                  ;       ;

+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;

+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;

+;                                                             ;                    ;       ;

+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;

+;                                                             ;                    ;       ;

+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;

+; Global clocks                                               ; 1 / 16             ; 6 %   ;

+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;

+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;

+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;

+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;

+; JTAGs                                                       ; 0 / 1              ; 0 %   ;

+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;

+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;

+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;

+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;

+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;

+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;

+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;

+; Peak interconnect usage (total/H/V)                         ; 3.6% / 3.8% / 3.1% ;       ;

+; Maximum fan-out                                             ; 58                 ;       ;

+; Highest non-global fan-out                                  ; 58                 ;       ;

+; Total fan-out                                               ; 1391               ;       ;

+; Average fan-out                                             ; 2.79               ;       ;

++-------------------------------------------------------------+--------------------+-------+

+

+

++----------------------------------------------------------------------------------------------------------------------+

+; Fitter Partition Statistics                                                                                          ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 154 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+; ALMs needed [=A-B+C]                                        ; 154                   ; 0                              ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 160 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;

+;         [a] ALMs used for LUT logic and registers           ; 37                    ; 0                              ;

+;         [b] ALMs used for LUT logic                         ; 117                   ; 0                              ;

+;         [c] ALMs used for registers                         ; 6                     ; 0                              ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 6 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;

+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;

+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;

+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Difficulty packing design                                   ; Low                   ; Low                            ;

+;                                                             ;                       ;                                ;

+; Total LABs:  partially or completely used                   ; 20 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;

+;     -- Logic LABs                                           ; 20                    ; 0                              ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Combinational ALUT usage for logic                          ; 287                   ; 0                              ;

+;     -- 7 input functions                                    ; 0                     ; 0                              ;

+;     -- 6 input functions                                    ; 23                    ; 0                              ;

+;     -- 5 input functions                                    ; 14                    ; 0                              ;

+;     -- 4 input functions                                    ; 150                   ; 0                              ;

+;     -- <=3 input functions                                  ; 100                   ; 0                              ;

+; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;

+; Memory ALUT usage                                           ; 0                     ; 0                              ;

+;     -- 64-address deep                                      ; 0                     ; 0                              ;

+;     -- 32-address deep                                      ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Dedicated logic registers                                   ; 0                     ; 0                              ;

+;     -- By type:                                             ;                       ;                                ;

+;         -- Primary logic registers                          ; 85 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;         -- Secondary logic registers                        ; 10 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;

+;     -- By function:                                         ;                       ;                                ;

+;         -- Design implementation registers                  ; 85                    ; 0                              ;

+;         -- Routing optimization registers                   ; 10                    ; 0                              ;

+;                                                             ;                       ;                                ;

+;                                                             ;                       ;                                ;

+; Virtual pins                                                ; 0                     ; 0                              ;

+; I/O pins                                                    ; 57                    ; 0                              ;

+; I/O registers                                               ; 0                     ; 0                              ;

+; Total block memory bits                                     ; 0                     ; 0                              ;

+; Total block memory implementation bits                      ; 0                     ; 0                              ;

+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;

+;                                                             ;                       ;                                ;

+; Connections                                                 ;                       ;                                ;

+;     -- Input Connections                                    ; 0                     ; 0                              ;

+;     -- Registered Input Connections                         ; 0                     ; 0                              ;

+;     -- Output Connections                                   ; 0                     ; 0                              ;

+;     -- Registered Output Connections                        ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Internal Connections                                        ;                       ;                                ;

+;     -- Total Connections                                    ; 1391                  ; 0                              ;

+;     -- Registered Connections                               ; 407                   ; 0                              ;

+;                                                             ;                       ;                                ;

+; External Connections                                        ;                       ;                                ;

+;     -- Top                                                  ; 0                     ; 0                              ;

+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Partition Interface                                         ;                       ;                                ;

+;     -- Input Ports                                          ; 5                     ; 0                              ;

+;     -- Output Ports                                         ; 52                    ; 0                              ;

+;     -- Bidir Ports                                          ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Registered Ports                                            ;                       ;                                ;

+;     -- Registered Input Ports                               ; 0                     ; 0                              ;

+;     -- Registered Output Ports                              ; 0                     ; 0                              ;

+;                                                             ;                       ;                                ;

+; Port Connectivity                                           ;                       ;                                ;

+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;

+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;

+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;

+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;

+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;

+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;

+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;

+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;

++-------------------------------------------------------------+-----------------------+--------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Input Pins                                                                                                                                                                                                                                                                              ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 40                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

+; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;

++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

+; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;

++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+

+

++-----------------------------------------------------------------------------+

+; I/O Bank Usage                                                              ;

++----------+-------------------+---------------+--------------+---------------+

+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;

++----------+-------------------+---------------+--------------+---------------+

+; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;

+; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;

+; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;

+; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;

+; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;

+; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;

+; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

+; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;

++----------+-------------------+---------------+--------------+---------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; All Package Pins                                                                                                                                                                  ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;

+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;

+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;

+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;

+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;

+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+Note: Pin directions (input, output or bidir) are based on device operating in user mode.

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+; |ex9                       ; 154.0 (0.5)          ; 159.0 (0.5)                      ; 5.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 287 (1)             ; 95 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;

+;    |LFSR:LFSR0|            ; 2.5 (2.5)            ; 3.2 (3.2)                        ; 0.7 (0.7)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;

+;    |bin2bcd_16:BCD|        ; 67.7 (0.0)           ; 68.0 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 124 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;

+;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;

+;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;

+;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;

+;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;

+;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;

+;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;

+;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;

+;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;

+;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;

+;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;

+;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;

+;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;

+;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;

+;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;

+;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;

+;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;

+;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;

+;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;

+;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;

+;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;

+;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;

+;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;

+;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;

+;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;

+;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;

+;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;

+;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;

+;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;

+;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;

+;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;

+;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 9.0 (9.0)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;

+;    |delay:DEL0|            ; 12.2 (12.2)          ; 13.2 (13.2)                      ; 0.9 (0.9)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 22 (22)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;

+;    |formula_fsm:FSM|       ; 8.9 (8.9)            ; 10.0 (10.0)                      ; 1.1 (1.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (16)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;

+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;

+;    |tick_2500:TICK1|       ; 14.1 (14.1)          ; 14.7 (14.7)                      ; 0.6 (0.6)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 27 (27)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_2500:TICK1             ; tick_2500   ; work         ;

+;    |tick_50000:TICK0|      ; 18.1 (18.1)          ; 19.0 (19.0)                      ; 0.9 (0.9)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Delay Chain Summary                                                                                                     ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; KEY[0]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+

+

++-------------------------------------------------------------------------------+

+; Pad To Core Delay Chain Fanout                                                ;

++-------------------------------------------------+-------------------+---------+

+; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;

++-------------------------------------------------+-------------------+---------+

+; KEY[1]                                          ;                   ;         ;

+; KEY[2]                                          ;                   ;         ;

+; KEY[0]                                          ;                   ;         ;

+;      - counter_16:COUNT0|count~0                ; 0                 ; 0       ;

+; CLOCK_50                                        ;                   ;         ;

+;      - tick_50000:TICK0|CLK_OUT                 ; 0                 ; 0       ;

+;      - tick_2500:TICK1|CLK_OUT                  ; 0                 ; 0       ;

+; KEY[3]                                          ;                   ;         ;

+;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;

+;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;

+;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1                 ; 0       ;

++-------------------------------------------------+-------------------+---------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Control Signals                                                                                                                                                                 ;

++-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+; Name                                ; Location            ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+; CLOCK_50                            ; PIN_AF14            ; 3       ; Clock                      ; no     ; --                   ; --               ; --                        ;

+; CLOCK_50                            ; PIN_AF14            ; 38      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;

+; counter_16:COUNT0|count~0           ; MLABCELL_X84_Y4_N48 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;

+; counter_16:COUNT0|state             ; FF_X84_Y4_N53       ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;

+; delay:DEL0|count[1]~0               ; MLABCELL_X84_Y1_N48 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;

+; delay:DEL0|state.COUNTING           ; FF_X83_Y1_N17       ; 18      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X85_Y1_N59       ; 19      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;

+; tick_2500:TICK1|CLK_OUT             ; FF_X81_Y1_N13       ; 10      ; Clock                      ; no     ; --                   ; --               ; --                        ;

+; tick_50000:TICK0|CLK_OUT            ; FF_X83_Y2_N20       ; 58      ; Clock, Clock enable        ; no     ; --                   ; --               ; --                        ;

++-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Global & Other Fast Signals                                                                         ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+; CLOCK_50 ; PIN_AF14 ; 38      ; Global Clock         ; GCLK6            ; --                        ;

++----------+----------+---------+----------------------+------------------+---------------------------+

+

+

++-----------------------------------------------------------------------+

+; Routing Usage Summary                                                 ;

++---------------------------------------------+-------------------------+

+; Routing Resource Type                       ; Usage                   ;

++---------------------------------------------+-------------------------+

+; Block interconnects                         ; 349 / 289,320 ( < 1 % ) ;

+; C12 interconnects                           ; 7 / 13,420 ( < 1 % )    ;

+; C2 interconnects                            ; 126 / 119,108 ( < 1 % ) ;

+; C4 interconnects                            ; 95 / 56,300 ( < 1 % )   ;

+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;

+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;

+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;

+; Direct links                                ; 63 / 289,320 ( < 1 % )  ;

+; Global clocks                               ; 1 / 16 ( 6 % )          ;

+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;

+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;

+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;

+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;

+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;

+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;

+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;

+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;

+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;

+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;

+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;

+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;

+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;

+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;

+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;

+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;

+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;

+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;

+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;

+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;

+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;

+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;

+; Local interconnects                         ; 127 / 84,580 ( < 1 % )  ;

+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;

+; R14 interconnects                           ; 56 / 12,676 ( < 1 % )   ;

+; R14/C12 interconnect drivers                ; 59 / 20,720 ( < 1 % )   ;

+; R3 interconnects                            ; 175 / 130,992 ( < 1 % ) ;

+; R6 interconnects                            ; 166 / 266,960 ( < 1 % ) ;

+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;

+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;

++---------------------------------------------+-------------------------+

+

+

++------------------------------------------+

+; I/O Rules Summary                        ;

++----------------------------------+-------+

+; I/O Rules Statistic              ; Total ;

++----------------------------------+-------+

+; Total I/O Rules                  ; 28    ;

+; Number of I/O Rules Passed       ; 6     ;

+; Number of I/O Rules Failed       ; 0     ;

+; Number of I/O Rules Unchecked    ; 0     ;

+; Number of I/O Rules Inapplicable ; 22    ;

++----------------------------------+-------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Details                                                                                                                                                                                                                                                  ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;

+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;

+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;

+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;

+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;

+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;

+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;

+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;

+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;

+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;

+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;

+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;

+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Total Pass         ; 57        ; 0            ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Inapplicable ; 0         ; 57           ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ;

+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; HEX5[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+

+

++------------------------------------------------------------------------------------------------+

+; Fitter Device Options                                                                          ;

++------------------------------------------------------------------+-----------------------------+

+; Option                                                           ; Setting                     ;

++------------------------------------------------------------------+-----------------------------+

+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;

+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;

+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;

+; Enable INIT_DONE output                                          ; Off                         ;

+; Configuration scheme                                             ; Passive Serial              ;

+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;

+; Enable CvP_CONFDONE pin                                          ; Off                         ;

+; Enable open drain on CRC_ERROR pin                               ; On                          ;

+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;

+; Enable open drain on INIT_DONE pin                               ; On                          ;

+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;

+; Enable open drain on nCEO pin                                    ; On                          ;

+; Enable Partial Reconfiguration pins                              ; Off                         ;

+; Enable input tri-state on active configuration pins in user mode ; Off                         ;

+; Enable internal scrubbing                                        ; Off                         ;

+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;

+; Device initialization clock source                               ; Internal Oscillator         ;

+; Configuration via Protocol                                       ; Off                         ;

+; Configuration Voltage Level                                      ; Auto                        ;

+; Force Configuration Voltage Level                                ; Off                         ;

+; Enable nCEO output                                               ; Off                         ;

+; Data[15..8]                                                      ; Unreserved                  ;

+; Data[7..5]                                                       ; Unreserved                  ;

+; Base pin-out file on sameframe device                            ; Off                         ;

++------------------------------------------------------------------+-----------------------------+

+

+

++------------------------------------+

+; Operating Settings and Conditions  ;

++---------------------------+--------+

+; Setting                   ; Value  ;

++---------------------------+--------+

+; Nominal Core Voltage      ; 1.10 V ;

+; Low Junction Temperature  ; 0 °C   ;

+; High Junction Temperature ; 85 °C  ;

++---------------------------+--------+

+

+

++-------------------------------------------------------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Summary                                                               ;

++--------------------------------------------------------------+--------------------------+-------------------+

+; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;

++--------------------------------------------------------------+--------------------------+-------------------+

+; CLOCK_50                                                     ; CLOCK_50                 ; 48.8              ;

+; tick_50000:TICK0|CLK_OUT                                     ; tick_2500:TICK1|CLK_OUT  ; 26.5              ;

+; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 22.9              ;

+; tick_2500:TICK1|CLK_OUT                                      ; tick_2500:TICK1|CLK_OUT  ; 8.3               ;

+; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 2.7               ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 2.6               ;

++--------------------------------------------------------------+--------------------------+-------------------+

+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.

+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.

+

+

++--------------------------------------------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Details                                                    ;

++----------------------------------------+-------------------------------------+-------------------+

+; Source Register                        ; Destination Register                ; Delay Added in ns ;

++----------------------------------------+-------------------------------------+-------------------+

+; tick_50000:TICK0|CLK_OUT               ; tick_2500:TICK1|CLK_OUT             ; 5.988             ;

+; tick_2500:TICK1|count[11]              ; tick_2500:TICK1|CLK_OUT             ; 2.378             ;

+; tick_2500:TICK1|count[5]               ; tick_2500:TICK1|CLK_OUT             ; 2.208             ;

+; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT            ; 2.161             ;

+; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT            ; 2.135             ;

+; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT            ; 2.084             ;

+; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT            ; 2.083             ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[2]             ; 2.077             ;

+; tick_2500:TICK1|count[9]               ; tick_2500:TICK1|CLK_OUT             ; 2.065             ;

+; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT            ; 2.053             ;

+; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT            ; 2.050             ;

+; tick_2500:TICK1|count[10]              ; tick_2500:TICK1|CLK_OUT             ; 2.046             ;

+; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT            ; 2.043             ;

+; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT            ; 2.013             ;

+; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT            ; 2.011             ;

+; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT            ; 1.990             ;

+; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT            ; 1.975             ;

+; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT            ; 1.972             ;

+; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT            ; 1.972             ;

+; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT            ; 1.966             ;

+; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT            ; 1.950             ;

+; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT            ; 1.928             ;

+; tick_2500:TICK1|count[4]               ; tick_2500:TICK1|CLK_OUT             ; 1.919             ;

+; tick_2500:TICK1|count[2]               ; tick_2500:TICK1|CLK_OUT             ; 1.652             ;

+; tick_2500:TICK1|count[3]               ; tick_2500:TICK1|CLK_OUT             ; 1.628             ;

+; tick_2500:TICK1|count[0]               ; tick_2500:TICK1|CLK_OUT             ; 1.615             ;

+; tick_2500:TICK1|count[6]               ; tick_2500:TICK1|CLK_OUT             ; 1.606             ;

+; tick_2500:TICK1|count[7]               ; tick_2500:TICK1|CLK_OUT             ; 1.603             ;

+; tick_2500:TICK1|count[1]               ; tick_2500:TICK1|CLK_OUT             ; 1.602             ;

+; tick_2500:TICK1|count[8]               ; tick_2500:TICK1|CLK_OUT             ; 1.569             ;

+; formula_fsm:FSM|start_delay            ; delay:DEL0|count[11]                ; 1.448             ;

+; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|ledr[4]             ; 0.962             ;

+; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|ledr[9]             ; 0.956             ;

+; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|ledr[6]             ; 0.941             ;

+; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|ledr[8]             ; 0.941             ;

+; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|ledr[7]             ; 0.921             ;

+; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|ledr[2]             ; 0.916             ;

+; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|ledr[5]             ; 0.910             ;

+; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                ; 0.901             ;

+; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                ; 0.899             ;

+; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|ledr[1]             ; 0.895             ;

+; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|ledr[3]             ; 0.890             ;

+; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                ; 0.859             ;

+; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                ; 0.855             ;

+; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                ; 0.854             ;

+; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                ; 0.837             ;

+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[2]             ; 0.821             ;

+; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                ; 0.792             ;

+; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.791             ;

+; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.791             ;

+; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|state.IDLE                  ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|state.COUNTING              ; delay:DEL0|count[11]                ; 0.747             ;

+; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE               ; 0.679             ;

+; delay:DEL0|state.TIME_OUT              ; delay:DEL0|state.IDLE               ; 0.679             ;

+; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.644             ;

+; KEY[3]                                 ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.644             ;

+; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.644             ;

+; LFSR:LFSR0|COUNT[5]                    ; delay:DEL0|count[11]                ; 0.632             ;

+; LFSR:LFSR0|COUNT[4]                    ; delay:DEL0|count[10]                ; 0.628             ;

+; LFSR:LFSR0|COUNT[6]                    ; delay:DEL0|count[12]                ; 0.628             ;

+; LFSR:LFSR0|COUNT[2]                    ; delay:DEL0|count[8]                 ; 0.622             ;

+; counter_16:COUNT0|state                ; counter_16:COUNT0|count[0]          ; 0.525             ;

+; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                 ; 0.429             ;

+; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]         ; 0.267             ;

+; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]         ; 0.253             ;

+; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]         ; 0.247             ;

+; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]         ; 0.246             ;

+; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]         ; 0.246             ;

+; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]         ; 0.244             ;

+; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]         ; 0.239             ;

+; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]         ; 0.236             ;

+; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]         ; 0.234             ;

+; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]         ; 0.233             ;

+; KEY[0]                                 ; counter_16:COUNT0|count[0]          ; 0.121             ;

+; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]         ; 0.059             ;

+; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]         ; 0.054             ;

+; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]         ; 0.053             ;

+; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]         ; 0.048             ;

+; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]         ; 0.048             ;

++----------------------------------------+-------------------------------------+-------------------+

+Note: This table only shows the top 86 path(s) that have the largest delay added for hold.

+

+

++-----------------+

+; Fitter Messages ;

++-----------------+

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

+Info (184020): Starting Fitter periphery placement operations

+Info (11191): Automatically promoted 1 clock (1 global)

+    Info (11162): CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6

+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

+Info (176233): Starting register packing

+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332144): No user constrained base clocks found in the design

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.

+Info (176235): Finished register packing

+    Extra Info (176219): No registers were packed into other blocks

+Warning (15705): Ignored locations or region assignments to the following nodes

+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design

+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design

+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11

+Info (170189): Fitter placement preparation operations beginning

+Info (14951): The Fitter is using Advanced Physical Optimization.

+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01

+Info (170191): Fitter placement operations beginning

+Info (170137): Fitter placement was successful

+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02

+Info (170193): Fitter routing operations beginning

+Info (170195): Router estimated average interconnect usage is 0% of the available device resources

+    Info (170196): Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10

+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.

+    Info (170201): Optimizations that may affect the design's routability were skipped

+Info (170194): Fitter routing operations ending: elapsed time is 00:00:04

+Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04

+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

+Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg

+Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings

+    Info: Peak virtual memory: 2617 megabytes

+    Info: Processing ended: Fri Nov 25 11:27:54 2016

+    Info: Elapsed time: 00:00:35

+    Info: Total CPU time (on all processors): 00:01:03

+

+

++----------------------------+

+; Fitter Suppressed Messages ;

++----------------------------+

+The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.fit.smsg.

+

+

diff --git a/part_2/ex9_partially_working/output_files/ex9.fit.smsg b/part_2/ex9_partially_working/output_files/ex9.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing

+Extra Info (176237): Finished Fast Input/Output/OE register processing

+Extra Info (176238): Start inferring scan chains for DSP blocks

+Extra Info (176239): Inferring scan chains for DSP blocks is complete

+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density

+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

diff --git a/part_2/ex9_partially_working/output_files/ex9.fit.summary b/part_2/ex9_partially_working/output_files/ex9.fit.summary
new file mode 100755
index 0000000..976377e
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Fri Nov 25 11:27:54 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex9

+Top-level Entity Name : ex9

+Family : Cyclone V

+Device : 5CSEMA5F31C6

+Timing Models : Final

+Logic utilization (in ALMs) : 154 / 32,070 ( < 1 % )

+Total registers : 95

+Total pins : 57 / 457 ( 12 % )

+Total virtual pins : 0

+Total block memory bits : 0 / 4,065,280 ( 0 % )

+Total RAM Blocks : 0 / 397 ( 0 % )

+Total DSP Blocks : 0 / 87 ( 0 % )

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0 / 6 ( 0 % )

+Total DLLs : 0 / 4 ( 0 % )

diff --git a/part_2/ex9_partially_working/output_files/ex9.flow.rpt b/part_2/ex9_partially_working/output_files/ex9.flow.rpt
new file mode 100755
index 0000000..834877e
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.flow.rpt
@@ -0,0 +1,128 @@
+Flow report for ex9

+Fri Nov 25 11:28:08 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Flow Summary

+  3. Flow Settings

+  4. Flow Non-Default Global Settings

+  5. Flow Elapsed Time

+  6. Flow OS Summary

+  7. Flow Log

+  8. Flow Messages

+  9. Flow Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Flow Summary                                                                      ;

++---------------------------------+-------------------------------------------------+

+; Flow Status                     ; Successful - Fri Nov 25 11:28:01 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex9                                             ;

+; Top-level Entity Name           ; ex9                                             ;

+; Family                          ; Cyclone V                                       ;

+; Device                          ; 5CSEMA5F31C6                                    ;

+; Timing Models                   ; Final                                           ;

+; Logic utilization (in ALMs)     ; 154 / 32,070 ( < 1 % )                          ;

+; Total registers                 ; 95                                              ;

+; Total pins                      ; 57 / 457 ( 12 % )                               ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;

+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;

++---------------------------------+-------------------------------------------------+

+

+

++-----------------------------------------+

+; Flow Settings                           ;

++-------------------+---------------------+

+; Option            ; Setting             ;

++-------------------+---------------------+

+; Start date & time ; 11/25/2016 11:27:08 ;

+; Main task         ; Compilation         ;

+; Revision Name     ; ex9                 ;

++-------------------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------+

+; Flow Non-Default Global Settings                                                                                       ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+; COMPILER_SIGNATURE_ID               ; 260248564297095.148007322808280       ; --            ; --          ; --         ;

+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;

+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;

+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;

+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;

+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;

+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;

+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;

+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;

++-------------------------------------+---------------------------------------+---------------+-------------+------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------------+

+; Flow Elapsed Time                                                                                                             ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Analysis & Synthesis      ; 00:00:11     ; 1.0                     ; 896 MB              ; 00:00:21                           ;

+; Fitter                    ; 00:00:35     ; 1.0                     ; 2617 MB             ; 00:01:03                           ;

+; Assembler                 ; 00:00:06     ; 1.0                     ; 895 MB              ; 00:00:06                           ;

+; TimeQuest Timing Analyzer ; 00:00:06     ; 1.1                     ; 1211 MB             ; 00:00:06                           ;

+; Total                     ; 00:00:58     ; --                      ; --                  ; 00:01:36                           ;

++---------------------------+--------------+-------------------------+---------------------+------------------------------------+

+

+

++----------------------------------------------------------------------------------------+

+; Flow OS Summary                                                                        ;

++---------------------------+------------------+-----------+------------+----------------+

+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;

++---------------------------+------------------+-----------+------------+----------------+

+; Analysis & Synthesis      ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; Fitter                    ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; Assembler                 ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

+; TimeQuest Timing Analyzer ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;

++---------------------------+------------------+-----------+------------+----------------+

+

+

+------------

+; Flow Log ;

+------------

+quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9

+quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9

+quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9

+quartus_sta ex9 -c ex9

+

+

+

diff --git a/part_2/ex9_partially_working/output_files/ex9.jdi b/part_2/ex9_partially_working/output_files/ex9.jdi
new file mode 100755
index 0000000..98be503
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>

+  <project>

+    <hash md5_digest_80b="a5a1d44468e3c5ecef42"/>

+  </project>

+  <file_info>

+    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>

+  </file_info>

+</sld_project_info>

diff --git a/part_2/ex9_partially_working/output_files/ex9.map.rpt b/part_2/ex9_partially_working/output_files/ex9.map.rpt
new file mode 100755
index 0000000..ce355a7
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.map.rpt
@@ -0,0 +1,629 @@
+Analysis & Synthesis report for ex9

+Fri Nov 25 11:27:18 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Analysis & Synthesis Summary

+  3. Analysis & Synthesis Settings

+  4. Parallel Compilation

+  5. Analysis & Synthesis Source Files Read

+  6. Analysis & Synthesis Resource Usage Summary

+  7. Analysis & Synthesis Resource Utilization by Entity

+  8. State Machine - |ex9|delay:DEL0|state

+  9. State Machine - |ex9|formula_fsm:FSM|state

+ 10. User-Specified and Inferred Latches

+ 11. Registers Removed During Synthesis

+ 12. General Register Statistics

+ 13. Inverted Register Statistics

+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)

+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0

+ 16. Parameter Settings for User Entity Instance: tick_2500:TICK1

+ 17. Parameter Settings for User Entity Instance: formula_fsm:FSM

+ 18. Parameter Settings for User Entity Instance: delay:DEL0

+ 19. Parameter Settings for User Entity Instance: counter_16:COUNT0

+ 20. Port Connectivity Checks: "hex_to_7seg:SEG5"

+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"

+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"

+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"

+ 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"

+ 25. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"

+ 26. Port Connectivity Checks: "delay:DEL0"

+ 27. Post-Synthesis Netlist Statistics for Top Partition

+ 28. Elapsed Time Per Partition

+ 29. Analysis & Synthesis Messages

+ 30. Analysis & Synthesis Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-----------------------------------------------------------------------------------+

+; Analysis & Synthesis Summary                                                      ;

++---------------------------------+-------------------------------------------------+

+; Analysis & Synthesis Status     ; Successful - Fri Nov 25 11:27:18 2016           ;

+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Revision Name                   ; ex9                                             ;

+; Top-level Entity Name           ; ex9                                             ;

+; Family                          ; Cyclone V                                       ;

+; Logic utilization (in ALMs)     ; N/A                                             ;

+; Total registers                 ; 85                                              ;

+; Total pins                      ; 57                                              ;

+; Total virtual pins              ; 0                                               ;

+; Total block memory bits         ; 0                                               ;

+; Total DSP Blocks                ; 0                                               ;

+; Total HSSI RX PCSs              ; 0                                               ;

+; Total HSSI PMA RX Deserializers ; 0                                               ;

+; Total HSSI TX PCSs              ; 0                                               ;

+; Total HSSI PMA TX Serializers   ; 0                                               ;

+; Total PLLs                      ; 0                                               ;

+; Total DLLs                      ; 0                                               ;

++---------------------------------+-------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Settings                                                                                             ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Option                                                                          ; Setting            ; Default Value      ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;

+; Top-level entity name                                                           ; ex9                ; ex9                ;

+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;

+; Use smart compilation                                                           ; Off                ; Off                ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;

+; Enable compact report table                                                     ; Off                ; Off                ;

+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;

+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;

+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;

+; Preserve fewer node names                                                       ; On                 ; On                 ;

+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;

+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;

+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;

+; State Machine Processing                                                        ; Auto               ; Auto               ;

+; Safe State Machine                                                              ; Off                ; Off                ;

+; Extract Verilog State Machines                                                  ; On                 ; On                 ;

+; Extract VHDL State Machines                                                     ; On                 ; On                 ;

+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;

+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;

+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;

+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;

+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;

+; Parallel Synthesis                                                              ; On                 ; On                 ;

+; DSP Block Balancing                                                             ; Auto               ; Auto               ;

+; NOT Gate Push-Back                                                              ; On                 ; On                 ;

+; Power-Up Don't Care                                                             ; On                 ; On                 ;

+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;

+; Remove Duplicate Registers                                                      ; On                 ; On                 ;

+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;

+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;

+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;

+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;

+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;

+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;

+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;

+; Optimization Technique                                                          ; Balanced           ; Balanced           ;

+; Carry Chain Length                                                              ; 70                 ; 70                 ;

+; Auto Carry Chains                                                               ; On                 ; On                 ;

+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;

+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;

+; Auto ROM Replacement                                                            ; On                 ; On                 ;

+; Auto RAM Replacement                                                            ; On                 ; On                 ;

+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;

+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;

+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;

+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;

+; Strict RAM Replacement                                                          ; Off                ; Off                ;

+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;

+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;

+; Auto Resource Sharing                                                           ; Off                ; Off                ;

+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;

+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;

+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;

+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;

+; Report Parameter Settings                                                       ; On                 ; On                 ;

+; Report Source Assignments                                                       ; On                 ; On                 ;

+; Report Connectivity Checks                                                      ; On                 ; On                 ;

+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;

+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;

+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;

+; HDL message level                                                               ; Level2             ; Level2             ;

+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;

+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;

+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;

+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;

+; Clock MUX Protection                                                            ; On                 ; On                 ;

+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;

+; Block Design Naming                                                             ; Auto               ; Auto               ;

+; SDC constraint protection                                                       ; Off                ; Off                ;

+; Synthesis Effort                                                                ; Auto               ; Auto               ;

+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;

+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;

+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;

+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;

+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;

+; Synthesis Seed                                                                  ; 1                  ; 1                  ;

+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;

+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processors 2-4         ;   0.0%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Source Files Read                                                                                                ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ; Library ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/tick_50000.v  ;         ;

+; verilog_files/tick_2500.v        ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/tick_2500.v   ;         ;

+; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/LFSR.v        ;         ;

+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/hex_to_7seg.v ;         ;

+; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/formula_fsm.v ;         ;

+; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/delay.v       ;         ;

+; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/counter_16.v  ;         ;

+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/bin2bcd_16.v  ;         ;

+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/add3_ge5.v    ;         ;

+; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/ex9.v         ;         ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+

+

+

++------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Usage Summary                            ;

++---------------------------------------------+--------------------------+

+; Resource                                    ; Usage                    ;

++---------------------------------------------+--------------------------+

+; Estimate of Logic utilization (ALMs needed) ; 156                      ;

+;                                             ;                          ;

+; Combinational ALUT usage for logic          ; 287                      ;

+;     -- 7 input functions                    ; 0                        ;

+;     -- 6 input functions                    ; 23                       ;

+;     -- 5 input functions                    ; 14                       ;

+;     -- 4 input functions                    ; 150                      ;

+;     -- <=3 input functions                  ; 100                      ;

+;                                             ;                          ;

+; Dedicated logic registers                   ; 85                       ;

+;                                             ;                          ;

+; I/O pins                                    ; 57                       ;

+;                                             ;                          ;

+; Total DSP Blocks                            ; 0                        ;

+;                                             ;                          ;

+; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;

+; Maximum fan-out                             ; 58                       ;

+; Total fan-out                               ; 1369                     ;

+; Average fan-out                             ; 2.82                     ;

++---------------------------------------------+--------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+; |ex9                       ; 287 (1)           ; 85 (0)       ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;

+;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;

+;    |bin2bcd_16:BCD|        ; 124 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;

+;       |add3_ge5:A10|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;

+;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;

+;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;

+;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;

+;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;

+;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;

+;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;

+;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;

+;       |add3_ge5:A18|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;

+;       |add3_ge5:A19|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;

+;       |add3_ge5:A1|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;

+;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;

+;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;

+;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;

+;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;

+;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;

+;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;

+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;

+;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;

+;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;

+;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;

+;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;

+;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;

+;       |add3_ge5:A32|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;

+;       |add3_ge5:A33|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;

+;       |add3_ge5:A34|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;

+;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;

+;       |add3_ge5:A3|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;

+;       |add3_ge5:A4|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;

+;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;

+;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;

+;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;

+;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;

+;       |add3_ge5:A9|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;

+;    |counter_16:COUNT0|     ; 17 (17)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;

+;    |delay:DEL0|            ; 22 (22)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;

+;    |formula_fsm:FSM|       ; 16 (16)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;

+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;

+;    |hex_to_7seg:SEG4|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;

+;    |tick_2500:TICK1|       ; 27 (27)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_2500:TICK1             ; tick_2500   ; work         ;

+;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;

++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

+Encoding Type:  One-Hot

++--------------------------------------------------------------------------------+

+; State Machine - |ex9|delay:DEL0|state                                          ;

++----------------+----------------+----------------+----------------+------------+

+; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;

++----------------+----------------+----------------+----------------+------------+

+; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;

+; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;

+; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;

+; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;

++----------------+----------------+----------------+----------------+------------+

+

+

+Encoding Type:  One-Hot

++--------------------------------------------------------------------------------------------+

+; State Machine - |ex9|formula_fsm:FSM|state                                                 ;

++------------------------+--------------------+------------------------+---------------------+

+; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;

++------------------------+--------------------+------------------------+---------------------+

+; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;

+; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;

+; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;

++------------------------+--------------------+------------------------+---------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------+

+; User-Specified and Inferred Latches                                                                               ;

++----------------------------------------------------+-------------------------------------+------------------------+

+; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;

++----------------------------------------------------+-------------------------------------+------------------------+

+; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;

+; Number of user-specified and inferred latches = 1  ;                                     ;                        ;

++----------------------------------------------------+-------------------------------------+------------------------+

+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.

+

+

++------------------------------------------------------------+

+; Registers Removed During Synthesis                         ;

++---------------------------------------+--------------------+

+; Register name                         ; Reason for Removal ;

++---------------------------------------+--------------------+

+; delay:DEL0|state~5                    ; Lost fanout        ;

+; delay:DEL0|state~6                    ; Lost fanout        ;

+; Total Number of Removed Registers = 2 ;                    ;

++---------------------------------------+--------------------+

+

+

++------------------------------------------------------+

+; General Register Statistics                          ;

++----------------------------------------------+-------+

+; Statistic                                    ; Value ;

++----------------------------------------------+-------+

+; Total registers                              ; 85    ;

+; Number of registers using Synchronous Clear  ; 16    ;

+; Number of registers using Synchronous Load   ; 15    ;

+; Number of registers using Asynchronous Clear ; 0     ;

+; Number of registers using Asynchronous Load  ; 0     ;

+; Number of registers using Clock Enable       ; 48    ;

+; Number of registers using Preset             ; 0     ;

++----------------------------------------------+-------+

+

+

++---------------------------------------------------+

+; Inverted Register Statistics                      ;

++-----------------------------------------+---------+

+; Inverted Register                       ; Fan out ;

++-----------------------------------------+---------+

+; tick_50000:TICK0|count[14]              ; 2       ;

+; tick_50000:TICK0|count[15]              ; 2       ;

+; tick_50000:TICK0|count[0]               ; 2       ;

+; tick_50000:TICK0|count[1]               ; 2       ;

+; tick_50000:TICK0|count[2]               ; 2       ;

+; tick_50000:TICK0|count[3]               ; 2       ;

+; tick_50000:TICK0|count[6]               ; 2       ;

+; tick_50000:TICK0|count[8]               ; 2       ;

+; tick_50000:TICK0|count[9]               ; 2       ;

+; tick_2500:TICK1|count[11]               ; 8       ;

+; tick_2500:TICK1|count[0]                ; 2       ;

+; tick_2500:TICK1|count[1]                ; 2       ;

+; tick_2500:TICK1|count[6]                ; 2       ;

+; tick_2500:TICK1|count[7]                ; 2       ;

+; tick_2500:TICK1|count[8]                ; 2       ;

+; LFSR:LFSR0|COUNT[1]                     ; 3       ;

+; Total number of inverted registers = 16 ;         ;

++-----------------------------------------+---------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------+

+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+

+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+

+; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[1] ;

+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[1]        ;

+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[11]       ;

+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector4  ;

+; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;

+; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;

++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+

+

+

++---------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;

++----------------+-------+--------------------------------------+

+; Parameter Name ; Value ; Type                                 ;

++----------------+-------+--------------------------------------+

+; NBIT           ; 16    ; Signed Integer                       ;

++----------------+-------+--------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++--------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;

++----------------+-------+-------------------------------------+

+; Parameter Name ; Value ; Type                                ;

++----------------+-------+-------------------------------------+

+; NBIT           ; 12    ; Signed Integer                      ;

++----------------+-------+-------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++--------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;

++------------------+-------+-----------------------------------+

+; Parameter Name   ; Value ; Type                              ;

++------------------+-------+-----------------------------------+

+; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;

+; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;

+; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;

++------------------+-------+-----------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++---------------------------------------------------------+

+; Parameter Settings for User Entity Instance: delay:DEL0 ;

++----------------+-------+--------------------------------+

+; Parameter Name ; Value ; Type                           ;

++----------------+-------+--------------------------------+

+; BIT_SZ         ; 14    ; Signed Integer                 ;

+; IDLE           ; 00    ; Unsigned Binary                ;

+; COUNTING       ; 01    ; Unsigned Binary                ;

+; TIME_OUT       ; 10    ; Unsigned Binary                ;

+; WAIT_LOW       ; 11    ; Unsigned Binary                ;

++----------------+-------+--------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++----------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;

++----------------+-------+---------------------------------------+

+; Parameter Name ; Value ; Type                                  ;

++----------------+-------+---------------------------------------+

+; BIT_SZ         ; 16    ; Signed Integer                        ;

+; COUNTING       ; 1     ; Unsigned Binary                       ;

+; IDLE           ; 0     ; Unsigned Binary                       ;

++----------------+-------+---------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++----------------------------------------------+

+; Port Connectivity Checks: "hex_to_7seg:SEG5" ;

++------+-------+----------+--------------------+

+; Port ; Type  ; Severity ; Details            ;

++------+-------+----------+--------------------+

+; in   ; Input ; Info     ; Stuck at GND       ;

++------+-------+----------+--------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+; Port  ; Type   ; Severity ; Details                                                                             ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;

+; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;

++-------+--------+----------+-------------------------------------------------------------------------------------+

+

+

++---------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;

++-------+-------+----------+------------------------------+

+; Port  ; Type  ; Severity ; Details                      ;

++-------+-------+----------+------------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                 ;

++-------+-------+----------+------------------------------+

+

+

++---------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;

++-------+-------+----------+------------------------------+

+; Port  ; Type  ; Severity ; Details                      ;

++-------+-------+----------+------------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                 ;

++-------+-------+----------+------------------------------+

+

+

++--------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;

++-------+-------+----------+-----------------------------+

+; Port  ; Type  ; Severity ; Details                     ;

++-------+-------+----------+-----------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                ;

++-------+-------+----------+-----------------------------+

+

+

++--------------------------------------------------------+

+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;

++-------+-------+----------+-----------------------------+

+; Port  ; Type  ; Severity ; Details                     ;

++-------+-------+----------+-----------------------------+

+; iW[3] ; Input ; Info     ; Stuck at GND                ;

++-------+-------+----------+-----------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; Port ; Type  ; Severity ; Details                                                                                                                                     ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;

++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------+

+; Post-Synthesis Netlist Statistics for Top Partition ;

++-----------------------+-----------------------------+

+; Type                  ; Count                       ;

++-----------------------+-----------------------------+

+; arriav_ff             ; 85                          ;

+;     ENA               ; 18                          ;

+;     ENA SCLR          ; 16                          ;

+;     ENA SLD           ; 14                          ;

+;     SLD               ; 1                           ;

+;     plain             ; 36                          ;

+; arriav_lcell_comb     ; 305                         ;

+;     arith             ; 58                          ;

+;         1 data inputs ; 58                          ;

+;     normal            ; 247                         ;

+;         0 data inputs ; 2                           ;

+;         1 data inputs ; 34                          ;

+;         2 data inputs ; 6                           ;

+;         3 data inputs ; 18                          ;

+;         4 data inputs ; 150                         ;

+;         5 data inputs ; 14                          ;

+;         6 data inputs ; 23                          ;

+; boundary_port         ; 57                          ;

+;                       ;                             ;

+; Max LUT depth         ; 15.00                       ;

+; Average LUT depth     ; 7.36                        ;

++-----------------------+-----------------------------+

+

+

++-------------------------------+

+; Elapsed Time Per Partition    ;

++----------------+--------------+

+; Partition Name ; Elapsed Time ;

++----------------+--------------+

+; Top            ; 00:00:00     ;

++----------------+--------------+

+

+

++-------------------------------+

+; Analysis & Synthesis Messages ;

++-------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Analysis & Synthesis

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 11:27:07 2016

+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v

+    Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex9/verilog_files/tick_50000.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v

+    Info (12023): Found entity 1: tick_2500 File: C:/New folder/ex9/verilog_files/tick_2500.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v

+    Info (12023): Found entity 1: LFSR File: C:/New folder/ex9/verilog_files/LFSR.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v

+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex9/verilog_files/hex_to_7seg.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v

+    Info (12023): Found entity 1: formula_fsm File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v

+    Info (12023): Found entity 1: delay File: C:/New folder/ex9/verilog_files/delay.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v

+    Info (12023): Found entity 1: counter_16 File: C:/New folder/ex9/verilog_files/counter_16.v Line: 1

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v

+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 12

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v

+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex9/verilog_files/add3_ge5.v Line: 9

+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v

+    Info (12023): Found entity 1: ex9 File: C:/New folder/ex9/verilog_files/ex9.v Line: 1

+Info (12127): Elaborating entity "ex9" for the top level hierarchy

+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 14

+Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: C:/New folder/ex9/verilog_files/ex9.v Line: 15

+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: C:/New folder/ex9/verilog_files/ex9.v Line: 17

+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 37

+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 47

+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(47) File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 47

+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 19

+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 21

+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: C:/New folder/ex9/verilog_files/delay.v Line: 24

+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 23

+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: C:/New folder/ex9/verilog_files/ex9.v Line: 25

+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 26

+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 27

+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder

+Warning (13024): Output pins are stuck at VCC or GND

+    Warning (13410): Pin "HEX5[0]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[1]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[2]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[3]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[4]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[5]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: C:/New folder/ex9/verilog_files/ex9.v Line: 6

+Info (286030): Timing-Driven Synthesis is running

+Info (17049): 2 registers lost all their fanouts during netlist optimizations.

+Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg

+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

+Warning (21074): Design contains 2 input pin(s) that do not drive logic

+    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4

+    Warning (15610): No output dependent on input pin "KEY[2]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4

+Info (21057): Implemented 353 device resources after synthesis - the final resource count might be different

+    Info (21058): Implemented 5 input pins

+    Info (21059): Implemented 52 output pins

+    Info (21061): Implemented 296 logic cells

+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings

+    Info: Peak virtual memory: 896 megabytes

+    Info: Processing ended: Fri Nov 25 11:27:18 2016

+    Info: Elapsed time: 00:00:11

+    Info: Total CPU time (on all processors): 00:00:21

+

+

++------------------------------------------+

+; Analysis & Synthesis Suppressed Messages ;

++------------------------------------------+

+The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.map.smsg.

+

+

diff --git a/part_2/ex9_partially_working/output_files/ex9.map.smsg b/part_2/ex9_partially_working/output_files/ex9.map.smsg
new file mode 100755
index 0000000..4b23fa8
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.map.smsg
@@ -0,0 +1,38 @@
+Warning (10268): Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 36

+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: C:/New folder/ex9/verilog_files/delay.v Line: 7

+Warning (10268): Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/counter_16.v Line: 16

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22

diff --git a/part_2/ex9_partially_working/output_files/ex9.map.summary b/part_2/ex9_partially_working/output_files/ex9.map.summary
new file mode 100755
index 0000000..b9abbcf
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Fri Nov 25 11:27:18 2016

+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Revision Name : ex9

+Top-level Entity Name : ex9

+Family : Cyclone V

+Logic utilization (in ALMs) : N/A

+Total registers : 85

+Total pins : 57

+Total virtual pins : 0

+Total block memory bits : 0

+Total DSP Blocks : 0

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0

+Total DLLs : 0

diff --git a/part_2/ex9_partially_working/output_files/ex9.pin b/part_2/ex9_partially_working/output_files/ex9.pin
new file mode 100755
index 0000000..6b2c6db
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+ -- Your use of Altera Corporation's design tools, logic functions 

+ -- and other software and tools, and its AMPP partner logic 

+ -- functions, and any output files from any of the foregoing 

+ -- (including device programming or simulation files), and any 

+ -- associated documentation or information are expressly subject 

+ -- to the terms and conditions of the Altera Program License 

+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,

+ -- the Altera MegaCore Function License Agreement, or other 

+ -- applicable license agreement, including, without limitation, 

+ -- that your use is for the sole purpose of programming logic 

+ -- devices manufactured by Altera and sold by Altera or its 

+ -- authorized distributors.  Please refer to the applicable 

+ -- agreement for further details.

+ -- 

+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is

+ -- not intended for use as a Quartus Prime input file. This file cannot be used

+ -- to make Quartus Prime pin assignments - for instructions on how to make pin

+ -- assignments, please see Quartus Prime help.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- NC            : No Connect. This pin has no internal connection to the device.

+ -- DNU           : Do Not Use. This pin MUST NOT be connected.

+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.

+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).

+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC

+ --                 of its bank.

+ --                  Bank 3A:       2.5V

+ --                  Bank 3B:       3.3V

+ --                  Bank 4A:       3.3V

+ --                  Bank 5A:       3.3V

+ --                  Bank 5B:       3.3V

+ --                  Bank 6B:       2.5V

+ --                  Bank 6A:  2.5V

+ --                  Bank 7A:  2.5V

+ --                  Bank 7B:  2.5V

+ --                  Bank 7C:  2.5V

+ --                  Bank 7D:  2.5V

+ --                  Bank 8A:  2.5V

+ -- RREF          : External reference resistor for the quad, MUST be connected to

+ --                 GND via a 2k Ohm resistor.

+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.

+ --                  It can also be used to report unused dedicated pins. The connection

+ --                  on the board for unused dedicated pins depends on whether this will

+ --                  be used in a future design. One example is device migration. When

+ --                  using device migration, refer to the device pin-tables. If it is a

+ --                  GND pin in the pin table or if it will not be used in a future design

+ --                  for another purpose the it MUST be connected to GND. If it is an unused

+ --                  dedicated pin, then it can be connected to a valid signal on the board

+ --                  (low, high, or toggling) if that signal is required for a different

+ --                  revision of the design.

+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.

+ --                  This pin should be connected to GND. It may also be connected  to a

+ --                  valid signal  on the board  (low, high, or toggling)  if that signal

+ --                  is required for a different revision of the design.

+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND

+ --                  or leave it unconnected.

+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.

+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.

+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.

+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.

+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.

+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin

+ --                 must not be connected.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- Pin directions (input, output or bidir) are based on device operating in user mode.

+ ---------------------------------------------------------------------------------

+

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6

+

+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

+-------------------------------------------------------------------------------------------------------------

+GND                          : A2        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                

+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                

+GND                          : A12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                

+GND                          : A17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                

+GND                          : A22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                

+GND                          : A26       :        :                   :         : 7A        :                

+GND                          : A27       : gnd    :                   :         :           :                

+HPS_TRST                     : A28       :        :                   :         : 7A        :                

+HPS_TMS                      : A29       :        :                   :         : 7A        :                

+GND                          : AA1       : gnd    :                   :         :           :                

+GND                          : AA2       : gnd    :                   :         :           :                

+GND                          : AA3       : gnd    :                   :         :           :                

+GND                          : AA4       : gnd    :                   :         :           :                

+VCC                          : AA5       : power  :                   : 1.1V    :           :                

+GND                          : AA6       : gnd    :                   :         :           :                

+DNU                          : AA7       :        :                   :         :           :                

+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                

+GND                          : AA9       : gnd    :                   :         :           :                

+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                

+GND                          : AA11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                

+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                

+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                

+GND                          : AA22      : gnd    :                   :         :           :                

+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                

+HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                

+GND                          : AB1       : gnd    :                   :         :           :                

+GND                          : AB2       : gnd    :                   :         :           :                

+DNU                          : AB3       :        :                   :         :           :                

+DNU                          : AB4       :        :                   :         :           :                

+GND                          : AB5       : gnd    :                   :         :           :                

+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                

+GND                          : AB7       : gnd    :                   :         :           :                

+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                

+TDO                          : AB9       : output :                   :         : 3A        :                

+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                

+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                

+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AB19      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                

+HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                

+HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AB29      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                

+GND                          : AC1       : gnd    :                   :         :           :                

+GND                          : AC2       : gnd    :                   :         :           :                

+GND                          : AC3       : gnd    :                   :         :           :                

+GND                          : AC4       : gnd    :                   :         :           :                

+TCK                          : AC5       : input  :                   :         : 3A        :                

+GND                          : AC6       : gnd    :                   :         :           :                

+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                

+GND                          : AC8       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                

+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                

+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                

+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                

+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                

+GND                          : AC16      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                

+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                

+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                

+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                

+HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AC26      : gnd    :                   :         :           :                

+HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AD1       : gnd    :                   :         :           :                

+GND                          : AD2       : gnd    :                   :         :           :                

+DNU                          : AD3       :        :                   :         :           :                

+DNU                          : AD4       :        :                   :         :           :                

+GND                          : AD5       : gnd    :                   :         :           :                

+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                

+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                

+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                

+DNU                          : AD15      :        :                   :         :           :                

+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                

+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                

+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                

+GND                          : AD23      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                

+HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                

+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              

+GND                          : AE1       : gnd    :                   :         :           :                

+GND                          : AE2       : gnd    :                   :         :           :                

+GND                          : AE3       : gnd    :                   :         :           :                

+GND                          : AE4       : gnd    :                   :         :           :                

+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                

+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                

+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                

+GND                          : AE10      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                

+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                

+GND                          : AE20      : gnd    :                   :         :           :                

+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                

+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                

+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                

+GND                          : AF1       : gnd    :                   :         :           :                

+GND                          : AF2       : gnd    :                   :         :           :                

+GND                          : AF3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                

+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                

+GND                          : AF12      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                

+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                

+GND                          : AF17      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                

+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                

+GND                          : AF27      : gnd    :                   :         :           :                

+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                

+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                

+GND                          : AG9       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                

+GND                          : AG14      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                

+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                

+GND                          : AG24      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                

+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                

+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AH1       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                

+GND                          : AH6       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                

+GND                          : AH11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                

+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                

+GND                          : AH21      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                

+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                

+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                

+GND                          : AJ3       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                

+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                

+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                

+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                

+GND                          : AJ18      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                

+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                

+GND                          : AJ28      : gnd    :                   :         :           :                

+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : AJ30      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                

+GND                          : AK5       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                

+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                

+GND                          : AK15      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                

+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                

+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                

+GND                          : AK25      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                

+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                

+GND                          : B9        : gnd    :                   :         :           :                

+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                

+GND                          : B14       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                

+GND                          : B19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                

+GND                          : B24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                

+HPS_TDI                      : B27       :        :                   :         : 7A        :                

+HPS_TDO                      : B28       :        :                   :         : 7A        :                

+GND                          : B29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                

+GND                          : C1        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                

+GND                          : C6        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                

+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                

+GND                          : C16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                

+GND                          : C21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                

+GND                          : C26       : gnd    :                   :         :           :                

+HPS_nRST                     : C27       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                

+GND                          : D3        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                

+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                

+GND                          : D13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                

+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                

+GND                          : D23       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                

+HPS_CLK1                     : D25       :        :                   :         : 7A        :                

+GND                          : D26       :        :                   :         : 7A        :                

+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                

+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                

+GND                          : E10       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                

+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                

+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                

+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                

+GND                          : E25       : gnd    :                   :         :           :                

+DNU                          : E26       :        :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                

+GND                          : E30       : gnd    :                   :         :           :                

+DNU                          : F1        :        :                   :         :           :                

+GND                          : F2        : gnd    :                   :         :           :                

+CONF_DONE                    : F3        :        :                   :         : 9A        :                

+nSTATUS                      : F4        :        :                   :         : 9A        :                

+GND                          : F5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                

+GND                          : F7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                

+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                

+GND                          : F17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                

+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                

+HPS_nPOR                     : F23       :        :                   :         : 7A        :                

+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                

+HPS_CLK2                     : F25       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                

+GND                          : F27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                

+GND                          : G1        :        :                   :         :           :                

+DNU                          : G2        :        :                   :         :           :                

+GND                          : G3        : gnd    :                   :         :           :                

+GND                          : G4        : gnd    :                   :         :           :                

+nCE                          : G5        :        :                   :         : 9A        :                

+MSEL2                        : G6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                

+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                

+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                

+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                

+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                

+GND                          : G24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                

+GND                          : H1        : gnd    :                   :         :           :                

+GND                          : H2        : gnd    :                   :         :           :                

+DNU                          : H3        :        :                   :         :           :                

+DNU                          : H4        :        :                   :         :           :                

+GND                          : H5        : gnd    :                   :         :           :                

+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                

+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                

+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                

+GND                          : H11       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                

+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                

+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                

+HPS_TCK                      : H22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                

+GND                          : J1        : gnd    :                   :         :           :                

+GND                          : J2        : gnd    :                   :         :           :                

+GND                          : J3        : gnd    :                   :         :           :                

+GND                          : J4        : gnd    :                   :         :           :                

+nCONFIG                      : J5        :        :                   :         : 9A        :                

+GND                          : J6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                

+GND                          : J8        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                

+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                

+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                

+DNU                          : J15       :        :                   :         :           :                

+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                

+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                

+GND                          : J18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                

+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                

+GND                          : J22       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                

+GND                          : J28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                

+GND                          : K1        : gnd    :                   :         :           :                

+GND                          : K2        : gnd    :                   :         :           :                

+DNU                          : K3        :        :                   :         :           :                

+DNU                          : K4        :        :                   :         :           :                

+GND                          : K5        : gnd    :                   :         :           :                

+MSEL1                        : K6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                

+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                

+GND                          : K10       : gnd    :                   :         :           :                

+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                

+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                

+GND                          : K15       : gnd    :                   :         :           :                

+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                

+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                

+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                

+GND                          : K20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                

+GND                          : K25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                

+GND                          : L1        : gnd    :                   :         :           :                

+GND                          : L2        : gnd    :                   :         :           :                

+GND                          : L3        : gnd    :                   :         :           :                

+GND                          : L4        : gnd    :                   :         :           :                

+VCC                          : L5        : power  :                   : 1.1V    :           :                

+GND                          : L6        : gnd    :                   :         :           :                

+MSEL3                        : L7        :        :                   :         : 9A        :                

+MSEL0                        : L8        :        :                   :         : 9A        :                

+MSEL4                        : L9        :        :                   :         : 9A        :                

+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                

+GND                          : L11       : gnd    :                   :         :           :                

+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                

+GND                          : L13       : gnd    :                   :         :           :                

+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                

+GND                          : L15       : gnd    :                   :         :           :                

+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                

+GND                          : L17       : gnd    :                   :         :           :                

+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                

+GND                          : L19       : gnd    :                   :         :           :                

+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                

+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                

+GND                          : L22       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                

+GND                          : M1        : gnd    :                   :         :           :                

+GND                          : M2        : gnd    :                   :         :           :                

+DNU                          : M3        :        :                   :         :           :                

+DNU                          : M4        :        :                   :         :           :                

+GND                          : M5        : gnd    :                   :         :           :                

+VCC                          : M6        : power  :                   : 1.1V    :           :                

+GND                          : M7        : gnd    :                   :         :           :                

+GND                          : M8        : gnd    :                   :         :           :                

+VCC                          : M9        : power  :                   : 1.1V    :           :                

+GND                          : M10       : gnd    :                   :         :           :                

+VCC                          : M11       : power  :                   : 1.1V    :           :                

+GND                          : M12       : gnd    :                   :         :           :                

+VCC                          : M13       : power  :                   : 1.1V    :           :                

+GND                          : M14       : gnd    :                   :         :           :                

+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                

+GND                          : M16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                

+GND                          : M18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                

+GND                          : M20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                

+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                

+GND                          : M29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                

+GND                          : N1        : gnd    :                   :         :           :                

+GND                          : N2        : gnd    :                   :         :           :                

+GND                          : N3        : gnd    :                   :         :           :                

+GND                          : N4        : gnd    :                   :         :           :                

+VCC                          : N5        : power  :                   : 1.1V    :           :                

+GND                          : N6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                

+GND                          : N8        : gnd    :                   :         :           :                

+GND                          : N9        : gnd    :                   :         :           :                

+VCC                          : N10       : power  :                   : 1.1V    :           :                

+GND                          : N11       : gnd    :                   :         :           :                

+VCC                          : N12       : power  :                   : 1.1V    :           :                

+GND                          : N13       : gnd    :                   :         :           :                

+VCC                          : N14       : power  :                   : 1.1V    :           :                

+GND                          : N15       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                

+GND                          : N17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                

+GND                          : N19       : gnd    :                   :         :           :                

+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                

+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                

+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                

+GND                          : N26       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                

+GND                          : P1        : gnd    :                   :         :           :                

+GND                          : P2        : gnd    :                   :         :           :                

+DNU                          : P3        :        :                   :         :           :                

+DNU                          : P4        :        :                   :         :           :                

+GND                          : P5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                

+GND                          : P7        : gnd    :                   :         :           :                

+GND                          : P8        : gnd    :                   :         :           :                

+GND                          : P9        : gnd    :                   :         :           :                

+GND                          : P10       : gnd    :                   :         :           :                

+VCC                          : P11       : power  :                   : 1.1V    :           :                

+GND                          : P12       : gnd    :                   :         :           :                

+VCC                          : P13       : power  :                   : 1.1V    :           :                

+GND                          : P14       : gnd    :                   :         :           :                

+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                

+GND                          : P16       : gnd    :                   :         :           :                

+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                

+GND                          : P18       : gnd    :                   :         :           :                

+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                

+GND                          : P20       : gnd    :                   :         :           :                

+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                

+GND                          : R1        : gnd    :                   :         :           :                

+GND                          : R2        : gnd    :                   :         :           :                

+GND                          : R3        : gnd    :                   :         :           :                

+GND                          : R4        : gnd    :                   :         :           :                

+VCC                          : R5        : power  :                   : 1.1V    :           :                

+GND                          : R6        : gnd    :                   :         :           :                

+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                

+GND                          : R8        : gnd    :                   :         :           :                

+GND                          : R9        : gnd    :                   :         :           :                

+VCC                          : R10       : power  :                   : 1.1V    :           :                

+GND                          : R11       : gnd    :                   :         :           :                

+VCC                          : R12       : power  :                   : 1.1V    :           :                

+GND                          : R13       : gnd    :                   :         :           :                

+VCC                          : R14       : power  :                   : 1.1V    :           :                

+GND                          : R15       : gnd    :                   :         :           :                

+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                

+GND                          : R17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                

+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                

+GND                          : R30       : gnd    :                   :         :           :                

+GND                          : T1        : gnd    :                   :         :           :                

+GND                          : T2        : gnd    :                   :         :           :                

+DNU                          : T3        :        :                   :         :           :                

+DNU                          : T4        :        :                   :         :           :                

+GND                          : T5        : gnd    :                   :         :           :                

+VCC                          : T6        : power  :                   : 1.1V    :           :                

+GND                          : T7        : gnd    :                   :         :           :                

+GND                          : T8        : gnd    :                   :         :           :                

+GND                          : T9        : gnd    :                   :         :           :                

+GND                          : T10       : gnd    :                   :         :           :                

+VCC                          : T11       : power  :                   : 1.1V    :           :                

+GND                          : T12       : gnd    :                   :         :           :                

+VCC                          : T13       : power  :                   : 1.1V    :           :                

+GND                          : T14       : gnd    :                   :         :           :                

+GND                          : T15       : gnd    :                   :         :           :                

+GND                          : T16       : gnd    :                   :         :           :                

+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                

+GND                          : T18       : gnd    :                   :         :           :                

+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                

+GND                          : T20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                

+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                

+GND                          : T27       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                

+GND                          : U1        : gnd    :                   :         :           :                

+GND                          : U2        : gnd    :                   :         :           :                

+GND                          : U3        : gnd    :                   :         :           :                

+GND                          : U4        : gnd    :                   :         :           :                

+VCC                          : U5        : power  :                   : 1.1V    :           :                

+GND                          : U6        : gnd    :                   :         :           :                

+DCLK                         : U7        :        :                   :         : 3A        :                

+TDI                          : U8        : input  :                   :         : 3A        :                

+GND                          : U9        : gnd    :                   :         :           :                

+VCC                          : U10       : power  :                   : 1.1V    :           :                

+GND                          : U11       : gnd    :                   :         :           :                

+VCC                          : U12       : power  :                   : 1.1V    :           :                

+GND                          : U13       : gnd    :                   :         :           :                

+VCC                          : U14       : power  :                   : 1.1V    :           :                

+GND                          : U15       : gnd    :                   :         :           :                

+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                

+GND                          : U17       : gnd    :                   :         :           :                

+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                

+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                

+VCC                          : U21       : power  :                   : 1.1V    :           :                

+GND                          : U22       : gnd    :                   :         :           :                

+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                

+GND                          : U24       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                

+GND                          : U29       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                

+GND                          : V1        : gnd    :                   :         :           :                

+GND                          : V2        : gnd    :                   :         :           :                

+DNU                          : V3        :        :                   :         :           :                

+DNU                          : V4        :        :                   :         :           :                

+GND                          : V5        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                

+GND                          : V7        : gnd    :                   :         :           :                

+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                

+TMS                          : V9        : input  :                   :         : 3A        :                

+GND                          : V10       : gnd    :                   :         :           :                

+VCC                          : V11       : power  :                   : 1.1V    :           :                

+GND                          : V12       : gnd    :                   :         :           :                

+VCC                          : V13       : power  :                   : 1.1V    :           :                

+GND                          : V14       : gnd    :                   :         :           :                

+VCC                          : V15       : power  :                   : 1.1V    :           :                

+LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : V19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                

+GND                          : V21       : gnd    :                   :         :           :                

+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                

+HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                

+HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              

+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                

+GND                          : W1        : gnd    :                   :         :           :                

+GND                          : W2        : gnd    :                   :         :           :                

+GND                          : W3        : gnd    :                   :         :           :                

+GND                          : W4        : gnd    :                   :         :           :                

+VCC                          : W5        : power  :                   : 1.1V    :           :                

+GND                          : W6        : gnd    :                   :         :           :                

+GND                          : W7        : gnd    :                   :         :           :                

+GND                          : W8        : gnd    :                   :         :           :                

+GND                          : W9        : gnd    :                   :         :           :                

+VCC                          : W10       : power  :                   : 1.1V    :           :                

+GND                          : W11       : gnd    :                   :         :           :                

+VCC                          : W12       : power  :                   : 1.1V    :           :                

+GND                          : W13       : gnd    :                   :         :           :                

+VCC                          : W14       : power  :                   : 1.1V    :           :                

+KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              

+LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : W18       : gnd    :                   :         :           :                

+LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              

+LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              

+LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                

+HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                

+GND                          : W28       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                

+GND                          : Y1        : gnd    :                   :         :           :                

+GND                          : Y2        : gnd    :                   :         :           :                

+DNU                          : Y3        :        :                   :         :           :                

+DNU                          : Y4        :        :                   :         :           :                

+GND                          : Y5        : gnd    :                   :         :           :                

+VCC                          : Y6        : power  :                   : 1.1V    :           :                

+GND                          : Y7        : gnd    :                   :         :           :                

+GND                          : Y8        : gnd    :                   :         :           :                

+VCC                          : Y9        : power  :                   : 1.1V    :           :                

+GND                          : Y10       : gnd    :                   :         :           :                

+VCC                          : Y11       : power  :                   : 1.1V    :           :                

+GND                          : Y12       : gnd    :                   :         :           :                

+VCC                          : Y13       : power  :                   : 1.1V    :           :                

+GND                          : Y14       : gnd    :                   :         :           :                

+GND                          : Y15       : gnd    :                   :         :           :                

+KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                

+LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              

+GND                          : Y20       : gnd    :                   :         :           :                

+LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              

+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                

+HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              

+HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              

+GND                          : Y25       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                

+HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                

+GND                          : Y30       : gnd    :                   :         :           :                

diff --git a/part_2/ex9_partially_working/output_files/ex9.sld b/part_2/ex9_partially_working/output_files/ex9.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.sld
@@ -0,0 +1 @@
+<sld_project_info/>

diff --git a/part_2/ex9_partially_working/output_files/ex9.sof b/part_2/ex9_partially_working/output_files/ex9.sof
new file mode 100755
index 0000000..7a37fc1
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.sof
diff --git a/part_2/ex9_partially_working/output_files/ex9.sta.rpt b/part_2/ex9_partially_working/output_files/ex9.sta.rpt
new file mode 100755
index 0000000..b7af62e
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.sta.rpt
@@ -0,0 +1,1046 @@
+TimeQuest Timing Analyzer report for ex9

+Fri Nov 25 11:28:08 2016

+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. TimeQuest Timing Analyzer Summary

+  3. Parallel Compilation

+  4. Clocks

+  5. Slow 1100mV 85C Model Fmax Summary

+  6. Timing Closure Recommendations

+  7. Slow 1100mV 85C Model Setup Summary

+  8. Slow 1100mV 85C Model Hold Summary

+  9. Slow 1100mV 85C Model Recovery Summary

+ 10. Slow 1100mV 85C Model Removal Summary

+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary

+ 12. Slow 1100mV 85C Model Metastability Summary

+ 13. Slow 1100mV 0C Model Fmax Summary

+ 14. Slow 1100mV 0C Model Setup Summary

+ 15. Slow 1100mV 0C Model Hold Summary

+ 16. Slow 1100mV 0C Model Recovery Summary

+ 17. Slow 1100mV 0C Model Removal Summary

+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary

+ 19. Slow 1100mV 0C Model Metastability Summary

+ 20. Fast 1100mV 85C Model Setup Summary

+ 21. Fast 1100mV 85C Model Hold Summary

+ 22. Fast 1100mV 85C Model Recovery Summary

+ 23. Fast 1100mV 85C Model Removal Summary

+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary

+ 25. Fast 1100mV 85C Model Metastability Summary

+ 26. Fast 1100mV 0C Model Setup Summary

+ 27. Fast 1100mV 0C Model Hold Summary

+ 28. Fast 1100mV 0C Model Recovery Summary

+ 29. Fast 1100mV 0C Model Removal Summary

+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary

+ 31. Fast 1100mV 0C Model Metastability Summary

+ 32. Multicorner Timing Analysis Summary

+ 33. Board Trace Model Assignments

+ 34. Input Transition Times

+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)

+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)

+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)

+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)

+ 39. Setup Transfers

+ 40. Hold Transfers

+ 41. Report TCCS

+ 42. Report RSKM

+ 43. Unconstrained Paths Summary

+ 44. Clock Status Summary

+ 45. Unconstrained Input Ports

+ 46. Unconstrained Output Ports

+ 47. Unconstrained Input Ports

+ 48. Unconstrained Output Ports

+ 49. TimeQuest Timing Analyzer Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, the Altera Quartus Prime License Agreement,

+the Altera MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Altera and sold by Altera or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------------------------+

+; TimeQuest Timing Analyzer Summary                                               ;

++-----------------------+---------------------------------------------------------+

+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;

+; Timing Analyzer       ; TimeQuest                                               ;

+; Revision Name         ; ex9                                                     ;

+; Device Family         ; Cyclone V                                               ;

+; Device Name           ; 5CSEMA5F31C6                                            ;

+; Timing Models         ; Final                                                   ;

+; Delay Model           ; Combined                                                ;

+; Rise/Fall Delays      ; Enabled                                                 ;

++-----------------------+---------------------------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 8           ;

+; Maximum allowed            ; 4           ;

+;                            ;             ;

+; Average used               ; 1.13        ;

+; Maximum used               ; 4           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   4.6%      ;

+;     Processor 3            ;   4.5%      ;

+;     Processor 4            ;   4.4%      ;

++----------------------------+-------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Clocks                                                                                                                                                                                                                                   ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;

+; tick_2500:TICK1|CLK_OUT             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_2500:TICK1|CLK_OUT }             ;

+; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;

++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+

+

+

++----------------------------------------------------------------+

+; Slow 1100mV 85C Model Fmax Summary                             ;

++------------+-----------------+--------------------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;

++------------+-----------------+--------------------------+------+

+; 239.81 MHz ; 239.81 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;

+; 295.86 MHz ; 295.86 MHz      ; CLOCK_50                 ;      ;

+; 446.83 MHz ; 446.83 MHz      ; tick_2500:TICK1|CLK_OUT  ;      ;

++------------+-----------------+--------------------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

+----------------------------------

+; Timing Closure Recommendations ;

+----------------------------------

+HTML report is unavailable in plain text report export.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 85C Model Setup Summary                          ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -4.063 ; -92.490       ;

+; tick_50000:TICK0|CLK_OUT            ; -3.170 ; -100.678      ;

+; tick_2500:TICK1|CLK_OUT             ; -1.647 ; -14.530       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.569 ; -1.569        ;

++-------------------------------------+--------+---------------+

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 85C Model Hold Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -2.594 ; -2.594        ;

+; tick_50000:TICK0|CLK_OUT            ; 0.279  ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.351  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.556  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+------------------------------------------

+; Slow 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Slow 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.746 ; -27.464       ;

+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -24.429       ;

+; tick_2500:TICK1|CLK_OUT             ; -0.394 ; -5.270        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.461  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------------

+; Slow 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++----------------------------------------------------------------+

+; Slow 1100mV 0C Model Fmax Summary                              ;

++------------+-----------------+--------------------------+------+

+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;

++------------+-----------------+--------------------------+------+

+; 244.98 MHz ; 244.98 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;

+; 276.93 MHz ; 276.93 MHz      ; CLOCK_50                 ;      ;

+; 451.06 MHz ; 451.06 MHz      ; tick_2500:TICK1|CLK_OUT  ;      ;

++------------+-----------------+--------------------------+------+

+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 0C Model Setup Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -3.620 ; -88.501       ;

+; tick_50000:TICK0|CLK_OUT            ; -3.082 ; -96.216       ;

+; tick_2500:TICK1|CLK_OUT             ; -1.680 ; -14.714       ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.485 ; -1.485        ;

++-------------------------------------+--------+---------------+

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 0C Model Hold Summary                            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -2.768 ; -2.768        ;

+; tick_50000:TICK0|CLK_OUT            ; 0.282  ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.351  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.430  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------

+; Slow 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Slow 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.788 ; -25.568       ;

+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -24.417       ;

+; tick_2500:TICK1|CLK_OUT             ; -0.394 ; -5.220        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.471  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+----------------------------------------------

+; Slow 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Setup Summary                          ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -3.305 ; -54.566       ;

+; tick_50000:TICK0|CLK_OUT            ; -1.630 ; -50.049       ;

+; tick_2500:TICK1|CLK_OUT             ; -1.087 ; -9.482        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.488 ; -0.488        ;

++-------------------------------------+--------+---------------+

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Hold Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -1.523 ; -1.523        ;

+; tick_2500:TICK1|CLK_OUT             ; -0.071 ; -0.328        ;

+; tick_50000:TICK0|CLK_OUT            ; 0.094  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.134  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+------------------------------------------

+; Fast 1100mV 85C Model Recovery Summary ;

+------------------------------------------

+No paths to report.

+

+

+-----------------------------------------

+; Fast 1100mV 85C Model Removal Summary ;

+-----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.856 ; -19.710       ;

+; tick_50000:TICK0|CLK_OUT            ; 0.062  ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.127  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.480  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------------

+; Fast 1100mV 85C Model Metastability Summary ;

+-----------------------------------------------

+No synchronizer chains to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Setup Summary                           ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -2.694 ; -44.892       ;

+; tick_50000:TICK0|CLK_OUT            ; -1.427 ; -42.012       ;

+; tick_2500:TICK1|CLK_OUT             ; -0.980 ; -8.435        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.386 ; -0.386        ;

++-------------------------------------+--------+---------------+

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Hold Summary                            ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -1.553 ; -1.553        ;

+; tick_2500:TICK1|CLK_OUT             ; -0.102 ; -0.665        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.064  ; 0.000         ;

+; tick_50000:TICK0|CLK_OUT            ; 0.081  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+-----------------------------------------

+; Fast 1100mV 0C Model Recovery Summary ;

+-----------------------------------------

+No paths to report.

+

+

+----------------------------------------

+; Fast 1100mV 0C Model Removal Summary ;

+----------------------------------------

+No paths to report.

+

+

++--------------------------------------------------------------+

+; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;

++-------------------------------------+--------+---------------+

+; Clock                               ; Slack  ; End Point TNS ;

++-------------------------------------+--------+---------------+

+; CLOCK_50                            ; -0.880 ; -23.155       ;

+; tick_50000:TICK0|CLK_OUT            ; 0.079  ; 0.000         ;

+; tick_2500:TICK1|CLK_OUT             ; 0.135  ; 0.000         ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.483  ; 0.000         ;

++-------------------------------------+--------+---------------+

+

+

+----------------------------------------------

+; Fast 1100mV 0C Model Metastability Summary ;

+----------------------------------------------

+No synchronizer chains to report.

+

+

++-----------------------------------------------------------------------------------------------------+

+; Multicorner Timing Analysis Summary                                                                 ;

++--------------------------------------+----------+--------+----------+---------+---------------------+

+; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;

++--------------------------------------+----------+--------+----------+---------+---------------------+

+; Worst-case Slack                     ; -4.063   ; -2.768 ; N/A      ; N/A     ; -0.880              ;

+;  CLOCK_50                            ; -4.063   ; -2.768 ; N/A      ; N/A     ; -0.880              ;

+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.569   ; 0.064  ; N/A      ; N/A     ; 0.461               ;

+;  tick_2500:TICK1|CLK_OUT             ; -1.680   ; -0.102 ; N/A      ; N/A     ; -0.394              ;

+;  tick_50000:TICK0|CLK_OUT            ; -3.170   ; 0.081  ; N/A      ; N/A     ; -0.394              ;

+; Design-wide TNS                      ; -209.267 ; -2.768 ; 0.0      ; 0.0     ; -57.163             ;

+;  CLOCK_50                            ; -92.490  ; -2.768 ; N/A      ; N/A     ; -27.464             ;

+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.569   ; 0.000  ; N/A      ; N/A     ; 0.000               ;

+;  tick_2500:TICK1|CLK_OUT             ; -14.714  ; -0.665 ; N/A      ; N/A     ; -5.270              ;

+;  tick_50000:TICK0|CLK_OUT            ; -100.678 ; 0.000  ; N/A      ; N/A     ; -24.429             ;

++--------------------------------------+----------+--------+----------+---------+---------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;

++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+

+

+

++-------------------------------------------------------------+

+; Input Transition Times                                      ;

++----------+--------------+-----------------+-----------------+

+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;

++----------+--------------+-----------------+-----------------+

+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

+; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;

++----------+--------------+-----------------+-----------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;

+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;

+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;

++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------+

+; Setup Transfers                                                                                                       ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; CLOCK_50                            ; CLOCK_50                            ; 574      ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; CLOCK_50                            ; 13       ; 13       ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_2500:TICK1|CLK_OUT             ; 9        ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; 9        ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_2500:TICK1|CLK_OUT             ; 10       ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 26       ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_50000:TICK0|CLK_OUT            ; 20       ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 605      ; 0        ; 0        ; 0        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

++-----------------------------------------------------------------------------------------------------------------------+

+; Hold Transfers                                                                                                        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+; CLOCK_50                            ; CLOCK_50                            ; 574      ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; CLOCK_50                            ; 13       ; 13       ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_2500:TICK1|CLK_OUT             ; 9        ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; 9        ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_2500:TICK1|CLK_OUT             ; 10       ; 0        ; 0        ; 0        ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 26       ; 9        ; 0        ; 0        ;

+; tick_2500:TICK1|CLK_OUT             ; tick_50000:TICK0|CLK_OUT            ; 20       ; 0        ; 0        ; 0        ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 605      ; 0        ; 0        ; 0        ;

++-------------------------------------+-------------------------------------+----------+----------+----------+----------+

+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.

+

+

+---------------

+; Report TCCS ;

+---------------

+No dedicated SERDES Transmitter circuitry present in device or used in design

+

+

+---------------

+; Report RSKM ;

+---------------

+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design

+

+

++------------------------------------------------+

+; Unconstrained Paths Summary                    ;

++---------------------------------+-------+------+

+; Property                        ; Setup ; Hold ;

++---------------------------------+-------+------+

+; Illegal Clocks                  ; 0     ; 0    ;

+; Unconstrained Clocks            ; 0     ; 0    ;

+; Unconstrained Input Ports       ; 2     ; 2    ;

+; Unconstrained Input Port Paths  ; 20    ; 20   ;

+; Unconstrained Output Ports      ; 45    ; 45   ;

+; Unconstrained Output Port Paths ; 500   ; 500  ;

++---------------------------------+-------+------+

+

+

++------------------------------------------------------------------------------------------------+

+; Clock Status Summary                                                                           ;

++-------------------------------------+-------------------------------------+------+-------------+

+; Target                              ; Clock                               ; Type ; Status      ;

++-------------------------------------+-------------------------------------+------+-------------+

+; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;

+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;

+; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; Base ; Constrained ;

+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;

++-------------------------------------+-------------------------------------+------+-------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------+

+; Unconstrained Input Ports                                                                         ;

++------------+--------------------------------------------------------------------------------------+

+; Input Port ; Comment                                                                              ;

++------------+--------------------------------------------------------------------------------------+

+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;

++------------+--------------------------------------------------------------------------------------+

+

+

++-----------------------------------------------------------------------------------------------------+

+; Unconstrained Output Ports                                                                          ;

++-------------+---------------------------------------------------------------------------------------+

+; Output Port ; Comment                                                                               ;

++-------------+---------------------------------------------------------------------------------------+

+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;

++-------------+---------------------------------------------------------------------------------------+

+

+

++------------------------------------+

+; TimeQuest Timing Analyzer Messages ;

++------------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime TimeQuest Timing Analyzer

+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+    Info: Processing started: Fri Nov 25 11:28:02 2016

+Info: Command: quartus_sta ex9 -c ex9

+Info: qsta_default_script.tcl version: #1

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

+Info (21077): Low junction temperature is 0 degrees C

+Info (21077): High junction temperature is 85 degrees C

+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"

+Info (332105): Deriving Clocks

+    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT

+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50

+    Info (332105): create_clock -period 1.000 -name tick_2500:TICK1|CLK_OUT tick_2500:TICK1|CLK_OUT

+    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON

+Info: Analyzing Slow 1100mV 85C Model

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -4.063

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -4.063             -92.490 CLOCK_50 

+    Info (332119):    -3.170            -100.678 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -1.647             -14.530 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -1.569              -1.569 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is -2.594

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -2.594              -2.594 CLOCK_50 

+    Info (332119):     0.279               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.351               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.556               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.746

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.746             -27.464 CLOCK_50 

+    Info (332119):    -0.394             -24.429 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.394              -5.270 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.461               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Slow 1100mV 0C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -3.620

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -3.620             -88.501 CLOCK_50 

+    Info (332119):    -3.082             -96.216 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -1.680             -14.714 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -1.485              -1.485 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is -2.768

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -2.768              -2.768 CLOCK_50 

+    Info (332119):     0.282               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.351               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.430               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.788

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.788             -25.568 CLOCK_50 

+    Info (332119):    -0.394             -24.417 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.394              -5.220 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.471               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Fast 1100mV 85C Model

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -3.305

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -3.305             -54.566 CLOCK_50 

+    Info (332119):    -1.630             -50.049 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -1.087              -9.482 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -0.488              -0.488 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is -1.523

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -1.523              -1.523 CLOCK_50 

+    Info (332119):    -0.071              -0.328 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.094               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.134               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.856

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.856             -19.710 CLOCK_50 

+    Info (332119):     0.062               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.127               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.480               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info: Analyzing Fast 1100mV 0C Model

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Critical Warning (332148): Timing requirements not met

+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

+Info (332146): Worst-case setup slack is -2.694

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -2.694             -44.892 CLOCK_50 

+    Info (332119):    -1.427             -42.012 tick_50000:TICK0|CLK_OUT 

+    Info (332119):    -0.980              -8.435 tick_2500:TICK1|CLK_OUT 

+    Info (332119):    -0.386              -0.386 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332146): Worst-case hold slack is -1.553

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -1.553              -1.553 CLOCK_50 

+    Info (332119):    -0.102              -0.665 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.064               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+    Info (332119):     0.081               0.000 tick_50000:TICK0|CLK_OUT 

+Info (332140): No Recovery paths to report

+Info (332140): No Removal paths to report

+Info (332146): Worst-case minimum pulse width slack is -0.880

+    Info (332119):     Slack       End Point TNS Clock 

+    Info (332119): ========= =================== =====================

+    Info (332119):    -0.880             -23.155 CLOCK_50 

+    Info (332119):     0.079               0.000 tick_50000:TICK0|CLK_OUT 

+    Info (332119):     0.135               0.000 tick_2500:TICK1|CLK_OUT 

+    Info (332119):     0.483               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 

+Info (332102): Design is not fully constrained for setup requirements

+Info (332102): Design is not fully constrained for hold requirements

+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings

+    Info: Peak virtual memory: 1211 megabytes

+    Info: Processing ended: Fri Nov 25 11:28:08 2016

+    Info: Elapsed time: 00:00:06

+    Info: Total CPU time (on all processors): 00:00:06

+

+

diff --git a/part_2/ex9_partially_working/output_files/ex9.sta.summary b/part_2/ex9_partially_working/output_files/ex9.sta.summary
new file mode 100755
index 0000000..18cd1d8
--- /dev/null
+++ b/part_2/ex9_partially_working/output_files/ex9.sta.summary
@@ -0,0 +1,197 @@
+------------------------------------------------------------

+TimeQuest Timing Analyzer Summary

+------------------------------------------------------------

+

+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'

+Slack : -4.063

+TNS   : -92.490

+

+Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -3.170

+TNS   : -100.678

+

+Type  : Slow 1100mV 85C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -1.647

+TNS   : -14.530

+

+Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -1.569

+TNS   : -1.569

+

+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'

+Slack : -2.594

+TNS   : -2.594

+

+Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.279

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.351

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.556

+TNS   : 0.000

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.746

+TNS   : -27.464

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.394

+TNS   : -24.429

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : -0.394

+TNS   : -5.270

+

+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.461

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'

+Slack : -3.620

+TNS   : -88.501

+

+Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -3.082

+TNS   : -96.216

+

+Type  : Slow 1100mV 0C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -1.680

+TNS   : -14.714

+

+Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -1.485

+TNS   : -1.485

+

+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'

+Slack : -2.768

+TNS   : -2.768

+

+Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.282

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.351

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.430

+TNS   : 0.000

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.788

+TNS   : -25.568

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : -0.394

+TNS   : -24.417

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : -0.394

+TNS   : -5.220

+

+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.471

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'

+Slack : -3.305

+TNS   : -54.566

+

+Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -1.630

+TNS   : -50.049

+

+Type  : Fast 1100mV 85C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -1.087

+TNS   : -9.482

+

+Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -0.488

+TNS   : -0.488

+

+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'

+Slack : -1.523

+TNS   : -1.523

+

+Type  : Fast 1100mV 85C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : -0.071

+TNS   : -0.328

+

+Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.094

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.134

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.856

+TNS   : -19.710

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.062

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.127

+TNS   : 0.000

+

+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.480

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'

+Slack : -2.694

+TNS   : -44.892

+

+Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'

+Slack : -1.427

+TNS   : -42.012

+

+Type  : Fast 1100mV 0C Model Setup 'tick_2500:TICK1|CLK_OUT'

+Slack : -0.980

+TNS   : -8.435

+

+Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : -0.386

+TNS   : -0.386

+

+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'

+Slack : -1.553

+TNS   : -1.553

+

+Type  : Fast 1100mV 0C Model Hold 'tick_2500:TICK1|CLK_OUT'

+Slack : -0.102

+TNS   : -0.665

+

+Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.064

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.081

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

+Slack : -0.880

+TNS   : -23.155

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'

+Slack : 0.079

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'

+Slack : 0.135

+TNS   : 0.000

+

+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'

+Slack : 0.483

+TNS   : 0.000

+

+------------------------------------------------------------

diff --git a/part_2/ex9_partially_working/verilog_files/LFSR.v b/part_2/ex9_partially_working/verilog_files/LFSR.v
new file mode 100755
index 0000000..46140b2
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/LFSR.v
@@ -0,0 +1,18 @@
+module LFSR(CLK, en, COUNT);

+

+	input CLK;

+	input en;

+	

+	output [7:1] COUNT;

+	

+	reg [7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		if(en == 1'b1)

+			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		else

+			COUNT <= COUNT;

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/LFSR.v.bak b/part_2/ex9_partially_working/verilog_files/LFSR.v.bak
new file mode 100755
index 0000000..89ec82a
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/LFSR.v.bak
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);

+	input CLK;

+	output[7:1] COUNT;

+	reg[7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/add3_ge5.v b/part_2/ex9_partially_working/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..a3cd6a9
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/add3_ge5.v
@@ -0,0 +1,34 @@
+//------------------------------

+// Module name: add3_ge5

+// Function: Add 3 to input if it is 5 or above

+// Creator:  Peter Cheung

+// Version:  1.0

+// Date:     21 Jan 2014

+//------------------------------

+

+module add3_ge5(iW,oA);

+

+ input [3:0] iW; 

+ output reg [3:0] oA;  

+ 

+	always @ (iW)

+		case (iW) 

+		//****** input <5, pass to output unchanged ******

+			4'b0000: oA <= 4'b0000; 

+			4'b0001: oA <= 4'b0001; 

+			4'b0010: oA <= 4'b0010; 

+			4'b0011: oA <= 4'b0011; 

+			4'b0100: oA <= 4'b0100;

+			

+		//****** input >=5, output = input + 3	******	

+			4'b0101: oA <= 4'b1000; 

+			4'b0110: oA <= 4'b1001; 

+			4'b0111: oA <= 4'b1010; 

+			4'b1000: oA <= 4'b1011; 

+			4'b1001: oA <= 4'b1100;

+			4'b1010: oA <= 4'b1101;	

+			4'b1011: oA <= 4'b1110;	

+			4'b1100: oA <= 4'b1111;	

+			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow

+		endcase 

+endmodule

diff --git a/part_2/ex9_partially_working/verilog_files/bin2bcd_16.v b/part_2/ex9_partially_working/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..b25d0bd
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/bin2bcd_16.v
@@ -0,0 +1,109 @@
+//------------------------------

+// Module name: bin2bcd_16

+// Function: Converts a 16-bit binary number to 5 digits BCD

+//            .... it uses a shift-and-add3 algorithm

+// Creator:  Peter Cheung

+// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)

+// Date:     24 Nov 2016

+//------------------------------

+//   For more explanation of how this work, see 

+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment

+

+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+

+	input [15:0]	B;		// binary input number

+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD

+	

+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;

+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;

+	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;

+	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;

+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;

+	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;

+

+	// Instantiate a tree of add3-if-greater than or equal to 5 cells

+	//  ... input is w_n, and output is a_n

+	add3_ge5 A1 (w1,a1);

+	add3_ge5 A2 (w2,a2);

+	add3_ge5 A3 (w3,a3);

+	add3_ge5 A4 (w4,a4);

+	add3_ge5 A5 (w5,a5);

+	add3_ge5 A6 (w6,a6);

+	add3_ge5 A7 (w7,a7);

+	add3_ge5 A8 (w8,a8);

+	add3_ge5 A9 (w9,a9);

+	add3_ge5 A10 (w10,a10);

+	add3_ge5 A11 (w11,a11);

+	add3_ge5 A12 (w12,a12);

+	add3_ge5 A13 (w13,a13);

+	add3_ge5 A14 (w14,a14);

+	add3_ge5 A15 (w15,a15);

+	add3_ge5 A16 (w16,a16);

+	add3_ge5 A17 (w17,a17);

+	add3_ge5 A18 (w18,a18);

+	add3_ge5 A19 (w19,a19);

+	add3_ge5 A20 (w20,a20);

+	add3_ge5 A21 (w21,a21);

+	add3_ge5 A22 (w22,a22);

+	add3_ge5 A23 (w23,a23);

+	add3_ge5 A24 (w24,a24);

+	add3_ge5 A25 (w25,a25);

+	add3_ge5 A26 (w26,a26);

+	add3_ge5 A27 (w27,a27);

+	add3_ge5 A28 (w28,a28);

+	add3_ge5 A29 (w29,a29);

+	add3_ge5 A30 (w30,a30);

+	add3_ge5 A31 (w31,a31);

+	add3_ge5 A32 (w32,a32);

+	add3_ge5 A33 (w33,a33);

+	add3_ge5 A34 (w34,a34);

+	add3_ge5 A35 (w35,a35);

+		

+	// wire the tree of add3 modules together

+	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n

+	assign  w2 = {a1[2:0], B[12]};		

+	assign  w3 = {a2[2:0], B[11]};		

+	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};

+	assign  w5 = {a3[2:0], B[10]};

+	assign  w6 = {a4[2:0], a5[3]};

+	assign  w7 = {a5[2:0], B[9]};

+	assign  w8 = {a6[2:0], a7[3]};

+	assign  w9 = {a7[2:0], B[8]};

+	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};

+	assign  w11 = {a8[2:0], a9[3]};

+	assign  w12 = {a9[2:0], B[7]};

+	assign  w13 = {a10[2:0], a11[3]};

+	assign  w14 = {a11[2:0], a12[3]};

+	assign  w15 = {a12[2:0], B[6]};

+	assign  w16 = {a13[2:0], a14[3]};

+	assign  w17 = {a14[2:0], a15[3]};

+	assign  w18 = {a15[2:0], B[5]};

+	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};

+	assign  w20 = {a16[2:0], a17[3]};

+	assign  w21 = {a17[2:0], a18[3]};

+	assign  w22 = {a18[2:0], B[4]};

+	assign  w23 = {a19[2:0], a20[3]};

+	assign  w24 = {a20[2:0], a21[3]};

+	assign  w25 = {a21[2:0], a22[3]};

+	assign  w26 = {a22[2:0], B[3]};

+	assign  w27 = {a23[2:0], a24[3]};

+	assign  w28 = {a24[2:0], a25[3]};

+	assign  w29 = {a25[2:0], a26[3]};

+	assign  w30 = {a26[2:0], B[2]};

+	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};

+	assign  w32 = {a27[2:0], a28[3]};

+	assign  w33 = {a28[2:0], a29[3]};

+	assign  w34 = {a29[2:0], a30[3]};

+	assign  w35 = {a30[2:0], B[1]};

+	

+	// connect up to four BCD digit outputs	

+	assign BCD_0 = {a35[2:0],B[0]};

+	assign BCD_1 = {a34[2:0],a35[3]};

+	assign BCD_2 = {a33[2:0],a34[3]};

+	assign BCD_3 = {a32[2:0],a33[3]};

+	assign BCD_4 = {a31[2:0],a32[3]};	

+endmodule

+

+	

+	

+

diff --git a/part_2/ex9_partially_working/verilog_files/counter_16.v b/part_2/ex9_partially_working/verilog_files/counter_16.v
new file mode 100755
index 0000000..79c144c
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/counter_16.v
@@ -0,0 +1,31 @@
+module counter_16(clock, start, stop, count);

+

+	parameter BIT_SZ = 16;

+	input clock, start, stop;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	reg state;

+	

+	parameter COUNTING = 1'b1, IDLE = 1'b0;

+	

+	initial count = 0;

+	initial state = IDLE;

+	

+	always @ (posedge clock)

+		case(state)

+			IDLE:

+				if(start == 1'b1)

+					begin

+						count = 0;

+						state = COUNTING;

+					end

+			COUNTING:

+				if(stop == 1'b1)

+					state <= IDLE;

+				else

+					count <= count + 1'b1;

+		endcase

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/counter_16.v.bak b/part_2/ex9_partially_working/verilog_files/counter_16.v.bak
new file mode 100755
index 0000000..c0ec549
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/counter_16.v.bak
@@ -0,0 +1,21 @@
+`timescale 1ns / 100ps

+

+module counter_16(clock,enable,reset,count);

+

+	parameter BIT_SZ = 16;

+	input clock, enable, reset;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		begin

+			if(enable == 1'b1)

+				count <= count + 1'b1;

+			if(reset == 1'b1)

+				count <= 16'b0;

+		end

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/delay.v b/part_2/ex9_partially_working/verilog_files/delay.v
new file mode 100755
index 0000000..a983085
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/delay.v
@@ -0,0 +1,60 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 14;

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+				begin

+					count <= N*128;

+					state <= COUNTING;

+				end

+			COUNTING: 

+				begin

+					if(count == 1'b0)

+						begin

+							state <= TIME_OUT;

+						end

+					else 

+						count <= count - 1'b1;

+				end

+			TIME_OUT: 

+				begin

+					if(trigger == 1'b0)

+						state <= IDLE;

+					else

+						state <= WAIT_LOW;

+				end

+			WAIT_LOW: 

+				if(trigger == 1'b0)

+					state <= IDLE;

+			default: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE:

+					time_out = 1'b0;

+			COUNTING: 

+					time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/delay.v.bak b/part_2/ex9_partially_working/verilog_files/delay.v.bak
new file mode 100755
index 0000000..7b79342
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/delay.v.bak
@@ -0,0 +1,47 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 7

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+		count = N-1'b1;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+					state <= COUNTING;

+			COUNTING: if(count == 1'b0) begin

+					count <= n - 1'b1;

+					state <= TIME_OUT;

+				end

+			TIME_OUT: if(trigger == 1'b0)

+					state <= IDLE;

+				else

+					state <= WAIT_LOW;

+			WAIT_LOW: if(trigger == 1'b0)

+					state <= IDLE;

+			defualt: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE: time_out = 1'b0;

+			COUNTING: time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex8.v b/part_2/ex9_partially_working/verilog_files/ex8.v
new file mode 100755
index 0000000..6ca51d6
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/ex8.v
@@ -0,0 +1,23 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex8.v.bak b/part_2/ex9_partially_working/verilog_files/ex8.v.bak
new file mode 100755
index 0000000..ac293e7
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/ex8.v.bak
@@ -0,0 +1 @@
+module ex8(
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex9.v b/part_2/ex9_partially_working/verilog_files/ex9.v
new file mode 100755
index 0000000..81aa0f9
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/ex9.v
@@ -0,0 +1,34 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	wire [15:0] count_out;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	

+	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);

+	

+	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	hex_to_7seg SEG3(HEX3, BCD_3);

+	hex_to_7seg SEG4(HEX4, BCD_4);

+	hex_to_7seg SEG5(HEX5, 4'b0);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex9.v.bak b/part_2/ex9_partially_working/verilog_files/ex9.v.bak
new file mode 100755
index 0000000..6ca51d6
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/ex9.v.bak
@@ -0,0 +1,23 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/formula_fsm.v b/part_2/ex9_partially_working/verilog_files/formula_fsm.v
new file mode 100755
index 0000000..90daa0c
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/formula_fsm.v
@@ -0,0 +1,66 @@
+module formula_fsm(clk, tick, trigger, time_out, en_lfsr, start_delay, ledr);

+

+input clk, tick, trigger, time_out;

+output en_lfsr, start_delay;

+output [9:0] ledr;

+

+reg [1:0] state;

+reg led_on, en_lfsr, start_delay;

+reg [9:0] ledr;

+

+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;

+

+initial 

+	begin

+		state = WAIT_TRIGGER;

+		en_lfsr = 1'b0;

+		start_delay = 1'b0;

+	end

+

+always @ (posedge clk)

+	case(state)

+		WAIT_TRIGGER: 

+			begin

+				if(trigger == 1'b1)

+					state <= LIGHT_UP_LEDS;

+			end

+		LIGHT_UP_LEDS:

+				if(ledr == 10'h3ff)

+					state <= WAIT_FOR_TIMEOUT;

+		WAIT_FOR_TIMEOUT:

+				if(time_out == 1'b1)

+					 state <= WAIT_TRIGGER;

+		default: ;

+	endcase

+

+always @ (posedge tick)

+	case(state)

+		WAIT_TRIGGER:

+			ledr = 10'b0;

+		LIGHT_UP_LEDS:

+			ledr <= {ledr[8:0], 1'b1};

+		default:

+			ledr <= 10'h3ff;

+	endcase

+	

+always @ (*)

+	case(state)

+		WAIT_TRIGGER:

+			begin

+

+				en_lfsr = 1'b0;

+				start_delay = 1'b0;

+			end

+		LIGHT_UP_LEDS:

+			begin

+				en_lfsr = 1'b1;

+			end

+		WAIT_FOR_TIMEOUT:

+			begin

+				start_delay = 1'b1;

+				en_lfsr = 1'b0;

+			end

+		default: ;

+	endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/formula_fsm.v.bak b/part_2/ex9_partially_working/verilog_files/formula_fsm.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/formula_fsm.v.bak
diff --git a/part_2/ex9_partially_working/verilog_files/hex_to_7seg.v b/part_2/ex9_partially_working/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/ex9_partially_working/verilog_files/tick_2500.v b/part_2/ex9_partially_working/verilog_files/tick_2500.v
new file mode 100755
index 0000000..e75a131
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/tick_2500.v
@@ -0,0 +1,35 @@
+module tick_2500(CLOCK_IN, en, CLK_OUT);

+

+	parameter NBIT = 12;

+	

+	input CLOCK_IN, en;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 12'd2499;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		if(en == 1'b1)

+			begin

+				if(count == 1'b0)

+					begin

+						CLK_OUT <= 1'b1;

+						count <= 12'd2499;

+					end

+				else

+					begin

+						count <= count - 1'b1;

+						CLK_OUT <= 1'b0;

+					end

+			end

+		else 

+			CLK_OUT <= 1'b0;

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/tick_2500.v.bak b/part_2/ex9_partially_working/verilog_files/tick_2500.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/tick_2500.v.bak
diff --git a/part_2/ex9_partially_working/verilog_files/tick_50000.v b/part_2/ex9_partially_working/verilog_files/tick_50000.v
new file mode 100755
index 0000000..7ccc81b
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/tick_50000.v
@@ -0,0 +1,32 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd49999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= 1'b1;

+					count <= 16'd49999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+					CLK_OUT <= 1'b0;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/tick_50000.v.bak b/part_2/ex9_partially_working/verilog_files/tick_50000.v.bak
new file mode 100755
index 0000000..45c4166
--- /dev/null
+++ b/part_2/ex9_partially_working/verilog_files/tick_50000.v.bak
@@ -0,0 +1,31 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd24999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= ~CLK_OUT;

+					count <= 16'd24999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/mylib/LFSR.v b/part_2/mylib/LFSR.v
new file mode 100755
index 0000000..89ec82a
--- /dev/null
+++ b/part_2/mylib/LFSR.v
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);

+	input CLK;

+	output[7:1] COUNT;

+	reg[7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/mylib/add3_ge5.v b/part_2/mylib/add3_ge5.v
new file mode 100755
index 0000000..65a561d
--- /dev/null
+++ b/part_2/mylib/add3_ge5.v
@@ -0,0 +1,25 @@
+module add3_ge5(w,a);

+	output [3:0] a;

+	input [3:0] w;

+	

+	reg [3:0] a;

+	

+	always @ (w)

+		case(w)

+			4'b0000: a <= 4'b0000;

+			4'b0001: a <= 4'b0001;

+			4'b0010: a <= 4'b0010;

+			4'b0011: a <= 4'b0011;

+			4'b0100: a <= 4'b0100;

+			4'b0101: a <= 4'b1000;

+			4'b0110: a <= 4'b1001;

+			4'b0111: a <= 4'b1010;

+			4'b1000: a <= 4'b1011;

+			4'b1001: a <= 4'b1100;

+			4'b1010: a <= 4'b1101;

+			4'b1011: a <= 4'b1110;

+			4'b1100: a <= 4'b1111;

+			

+			default: a <= 4'b0000;

+		endcase

+endmodule

diff --git a/part_2/mylib/bin2bcd_16.v b/part_2/mylib/bin2bcd_16.v
new file mode 100755
index 0000000..fdfb655
--- /dev/null
+++ b/part_2/mylib/bin2bcd_16.v
@@ -0,0 +1,97 @@
+//------------------------------

+// Module name: bin2bcd_16

+// Function: Converts a 16-bit binary number to 5 digits BCD

+//            .... it uses a shift-and-add3 algorithm

+// Creator:  Peter Cheung

+// Version:  1.0

+// Date:     18 Sept 2016

+//------------------------------

+//   For more explanation of how this work, see 

+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment

+

+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+

+	input [15:0]	B;		// binary input number

+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD

+	

+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;

+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;

+	wire [3:0]	w26,w27,w28,w29;

+	wire [3:0]	a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;

+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;

+	wire [3:0]	a26,a27,a28,a29;

+

+	// Instantiate a tree of add3-if-greater than or equal to 5 cells

+	//  ... input is w_n, and output is a_n

+	add3_ge5 A1 (w1,a1);

+	add3_ge5 A2 (w2,a2);

+	add3_ge5 A3 (w3,a3);

+	add3_ge5 A4 (w4,a4);

+	add3_ge5 A5 (w5,a5);

+	add3_ge5 A6 (w6,a6);

+	add3_ge5 A7 (w7,a7);

+	add3_ge5 A8 (w8,a8);

+	add3_ge5 A9 (w9,a9);

+	add3_ge5 A10 (w10,a10);

+	add3_ge5 A11 (w11,a11);

+	add3_ge5 A12 (w12,a12);

+	add3_ge5 A13 (w13,a13);

+	add3_ge5 A14 (w14,a14);

+	add3_ge5 A15 (w15,a15);

+	add3_ge5 A16 (w16,a16);

+	add3_ge5 A17 (w17,a17);

+	add3_ge5 A18 (w18,a18);

+	add3_ge5 A19 (w19,a19);

+	add3_ge5 A20 (w20,a20);

+	add3_ge5 A21 (w21,a21);

+	add3_ge5 A22 (w22,a22);

+	add3_ge5 A23 (w23,a23);

+	add3_ge5 A24 (w24,a24);

+	add3_ge5 A25 (w25,a25);

+	add3_ge5 A26 (w26,a26);

+	add3_ge5 A27 (w27,a27);

+	add3_ge5 A28 (w28,a28);

+	add3_ge5 A29 (w29,a29);

+		

+	// wire the tree of add3 modules together

+	assign  w1 = {B[14:11]};		// wn is the input port to module An

+	assign  w2 = {a1[2:0], B[10]};

+	assign  w3 = {1'b0, B[15], a1[3], a2[3]};

+	assign  w4 = {a2[2:0], B[9]};

+	assign  w5 = {a3[2:0], a4[3]};

+	assign  w6 = {a4[2:0], B[8]};

+	assign  w7 = {a5[2:0], a6[3]};

+	assign  w8 = {a6[2:0], B[7]};

+	assign  w9 = {1'b0, a3[3], a5[3], a7[3]};

+	assign  w10 = {a7[2:0], a8[3]};

+	assign  w11 = {a8[2:0], B[6]};

+	assign  w12 = {a9[2:0], a10[3]};

+	assign  w13 = {a10[2:0], a11[3]};

+	assign  w14 = {a11[2:0], B[5]};

+	assign  w15 = {a12[2:0], a13[3]};

+	assign  w16 = {a13[2:0], a14[3]};

+	assign  w17 = {a14[2:0], B[4]};

+	assign  w18 = {1'b0, a9[3], a12[3], a15[3]};

+	assign  w19 = {a15[2:0], a16[3]};

+	assign  w20 = {a16[2:0], a17[3]};

+	assign  w21 = {a17[2:0], B[3]};

+	assign  w22 = {a18[2:0], a19[3]};

+	assign  w23 = {a19[2:0], a20[3]};

+	assign  w24 = {a20[2:0], a21[3]};

+	assign  w25 = {a21[2:0], B[2]};

+	assign  w26 = {a22[2:0], a23[3]};

+	assign  w27 = {a23[2:0], a24[3]};

+	assign  w28 = {a24[2:0], a25[3]};

+	assign  w29 = {a25[2:0], B[1]};

+	

+	// connect up to four BCD digit outputs	

+	assign BCD_0 = {a29[2:0],B[0]};

+	assign BCD_1 = {a28[2:0],a29[3]};

+	assign BCD_2 = {a27[2:0],a28[3]};

+	assign BCD_3 = {a26[2:0],a27[3]};

+	assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};	

+endmodule

+

+	

+	

+

diff --git a/part_2/mylib/counter_16.v b/part_2/mylib/counter_16.v
new file mode 100755
index 0000000..c0ec549
--- /dev/null
+++ b/part_2/mylib/counter_16.v
@@ -0,0 +1,21 @@
+`timescale 1ns / 100ps

+

+module counter_16(clock,enable,reset,count);

+

+	parameter BIT_SZ = 16;

+	input clock, enable, reset;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		begin

+			if(enable == 1'b1)

+				count <= count + 1'b1;

+			if(reset == 1'b1)

+				count <= 16'b0;

+		end

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/mylib/counter_8.v b/part_2/mylib/counter_8.v
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/mylib/counter_8.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/mylib/delay.v b/part_2/mylib/delay.v
new file mode 100755
index 0000000..a983085
--- /dev/null
+++ b/part_2/mylib/delay.v
@@ -0,0 +1,60 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 14;

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+				begin

+					count <= N*128;

+					state <= COUNTING;

+				end

+			COUNTING: 

+				begin

+					if(count == 1'b0)

+						begin

+							state <= TIME_OUT;

+						end

+					else 

+						count <= count - 1'b1;

+				end

+			TIME_OUT: 

+				begin

+					if(trigger == 1'b0)

+						state <= IDLE;

+					else

+						state <= WAIT_LOW;

+				end

+			WAIT_LOW: 

+				if(trigger == 1'b0)

+					state <= IDLE;

+			default: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE:

+					time_out = 1'b0;

+			COUNTING: 

+					time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/mylib/ex8.v b/part_2/mylib/ex8.v
new file mode 100755
index 0000000..aaa8488
--- /dev/null
+++ b/part_2/mylib/ex8.v
@@ -0,0 +1,23 @@
+module ex8(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/mylib/formula_fsm.v b/part_2/mylib/formula_fsm.v
new file mode 100755
index 0000000..90daa0c
--- /dev/null
+++ b/part_2/mylib/formula_fsm.v
@@ -0,0 +1,66 @@
+module formula_fsm(clk, tick, trigger, time_out, en_lfsr, start_delay, ledr);

+

+input clk, tick, trigger, time_out;

+output en_lfsr, start_delay;

+output [9:0] ledr;

+

+reg [1:0] state;

+reg led_on, en_lfsr, start_delay;

+reg [9:0] ledr;

+

+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;

+

+initial 

+	begin

+		state = WAIT_TRIGGER;

+		en_lfsr = 1'b0;

+		start_delay = 1'b0;

+	end

+

+always @ (posedge clk)

+	case(state)

+		WAIT_TRIGGER: 

+			begin

+				if(trigger == 1'b1)

+					state <= LIGHT_UP_LEDS;

+			end

+		LIGHT_UP_LEDS:

+				if(ledr == 10'h3ff)

+					state <= WAIT_FOR_TIMEOUT;

+		WAIT_FOR_TIMEOUT:

+				if(time_out == 1'b1)

+					 state <= WAIT_TRIGGER;

+		default: ;

+	endcase

+

+always @ (posedge tick)

+	case(state)

+		WAIT_TRIGGER:

+			ledr = 10'b0;

+		LIGHT_UP_LEDS:

+			ledr <= {ledr[8:0], 1'b1};

+		default:

+			ledr <= 10'h3ff;

+	endcase

+	

+always @ (*)

+	case(state)

+		WAIT_TRIGGER:

+			begin

+

+				en_lfsr = 1'b0;

+				start_delay = 1'b0;

+			end

+		LIGHT_UP_LEDS:

+			begin

+				en_lfsr = 1'b1;

+			end

+		WAIT_FOR_TIMEOUT:

+			begin

+				start_delay = 1'b1;

+				en_lfsr = 1'b0;

+			end

+		default: ;

+	endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/mylib/hex_to_7seg.v b/part_2/mylib/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/mylib/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/mylib/tick_2500.v b/part_2/mylib/tick_2500.v
new file mode 100755
index 0000000..e75a131
--- /dev/null
+++ b/part_2/mylib/tick_2500.v
@@ -0,0 +1,35 @@
+module tick_2500(CLOCK_IN, en, CLK_OUT);

+

+	parameter NBIT = 12;

+	

+	input CLOCK_IN, en;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 12'd2499;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		if(en == 1'b1)

+			begin

+				if(count == 1'b0)

+					begin

+						CLK_OUT <= 1'b1;

+						count <= 12'd2499;

+					end

+				else

+					begin

+						count <= count - 1'b1;

+						CLK_OUT <= 1'b0;

+					end

+			end

+		else 

+			CLK_OUT <= 1'b0;

+

+endmodule
\ No newline at end of file
diff --git a/part_2/mylib/tick_50000.v b/part_2/mylib/tick_50000.v
new file mode 100755
index 0000000..45c4166
--- /dev/null
+++ b/part_2/mylib/tick_50000.v
@@ -0,0 +1,31 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd24999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= ~CLK_OUT;

+					count <= 16'd24999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+				end

+		end

+

+endmodule
\ No newline at end of file