adding part 2 and 3

77 files changed, 2054 insertions, 0 deletions

diff --git a/part_2/ex8/db/.cmp.kpt b/part_2/ex8/db/.cmp.kpt
new file mode 100755
index 0000000..113b18d
--- /dev/null
+++ b/part_2/ex8/db/.cmp.kpt
diff --git a/part_2/ex8/db/ex8.(0).cnf.cdb b/part_2/ex8/db/ex8.(0).cnf.cdb
new file mode 100755
index 0000000..5cdd1d4
--- /dev/null
+++ b/part_2/ex8/db/ex8.(0).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(0).cnf.hdb b/part_2/ex8/db/ex8.(0).cnf.hdb
new file mode 100755
index 0000000..4517872
--- /dev/null
+++ b/part_2/ex8/db/ex8.(0).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(1).cnf.cdb b/part_2/ex8/db/ex8.(1).cnf.cdb
new file mode 100755
index 0000000..4aa533b
--- /dev/null
+++ b/part_2/ex8/db/ex8.(1).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(1).cnf.hdb b/part_2/ex8/db/ex8.(1).cnf.hdb
new file mode 100755
index 0000000..592417b
--- /dev/null
+++ b/part_2/ex8/db/ex8.(1).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(2).cnf.cdb b/part_2/ex8/db/ex8.(2).cnf.cdb
new file mode 100755
index 0000000..fa21ea0
--- /dev/null
+++ b/part_2/ex8/db/ex8.(2).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(2).cnf.hdb b/part_2/ex8/db/ex8.(2).cnf.hdb
new file mode 100755
index 0000000..9b7ef11
--- /dev/null
+++ b/part_2/ex8/db/ex8.(2).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(3).cnf.cdb b/part_2/ex8/db/ex8.(3).cnf.cdb
new file mode 100755
index 0000000..4ac3994
--- /dev/null
+++ b/part_2/ex8/db/ex8.(3).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(3).cnf.hdb b/part_2/ex8/db/ex8.(3).cnf.hdb
new file mode 100755
index 0000000..b5a6f32
--- /dev/null
+++ b/part_2/ex8/db/ex8.(3).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(4).cnf.cdb b/part_2/ex8/db/ex8.(4).cnf.cdb
new file mode 100755
index 0000000..e6a0005
--- /dev/null
+++ b/part_2/ex8/db/ex8.(4).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(4).cnf.hdb b/part_2/ex8/db/ex8.(4).cnf.hdb
new file mode 100755
index 0000000..1aa2860
--- /dev/null
+++ b/part_2/ex8/db/ex8.(4).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(5).cnf.cdb b/part_2/ex8/db/ex8.(5).cnf.cdb
new file mode 100755
index 0000000..e02c97b
--- /dev/null
+++ b/part_2/ex8/db/ex8.(5).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(5).cnf.hdb b/part_2/ex8/db/ex8.(5).cnf.hdb
new file mode 100755
index 0000000..92790f4
--- /dev/null
+++ b/part_2/ex8/db/ex8.(5).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(6).cnf.cdb b/part_2/ex8/db/ex8.(6).cnf.cdb
new file mode 100755
index 0000000..2ef9091
--- /dev/null
+++ b/part_2/ex8/db/ex8.(6).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(6).cnf.hdb b/part_2/ex8/db/ex8.(6).cnf.hdb
new file mode 100755
index 0000000..af5dcd5
--- /dev/null
+++ b/part_2/ex8/db/ex8.(6).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(7).cnf.cdb b/part_2/ex8/db/ex8.(7).cnf.cdb
new file mode 100755
index 0000000..280aa80
--- /dev/null
+++ b/part_2/ex8/db/ex8.(7).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(7).cnf.hdb b/part_2/ex8/db/ex8.(7).cnf.hdb
new file mode 100755
index 0000000..42ab8b5
--- /dev/null
+++ b/part_2/ex8/db/ex8.(7).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(8).cnf.cdb b/part_2/ex8/db/ex8.(8).cnf.cdb
new file mode 100755
index 0000000..75ea495
--- /dev/null
+++ b/part_2/ex8/db/ex8.(8).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(8).cnf.hdb b/part_2/ex8/db/ex8.(8).cnf.hdb
new file mode 100755
index 0000000..1df751e
--- /dev/null
+++ b/part_2/ex8/db/ex8.(8).cnf.hdb
diff --git a/part_2/ex8/db/ex8.ae.hdb b/part_2/ex8/db/ex8.ae.hdb
new file mode 100755
index 0000000..58cff3f
--- /dev/null
+++ b/part_2/ex8/db/ex8.ae.hdb
diff --git a/part_2/ex8/db/ex8.analyze_file.qmsg b/part_2/ex8/db/ex8.analyze_file.qmsg
new file mode 100755
index 0000000..34ad0f8
--- /dev/null
+++ b/part_2/ex8/db/ex8.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479898397112 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 23 10:53:16 2016 " "Processing started: Wed Nov 23 10:53:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479898397114 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479898397537 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479898397537 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "827 " "Peak virtual memory: 827 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 10:53:26 2016 " "Processing ended: Wed Nov 23 10:53:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479898406239 ""}

diff --git a/part_2/ex8/db/ex8.asm.qmsg b/part_2/ex8/db/ex8.asm.qmsg
new file mode 100755
index 0000000..ef22aca
--- /dev/null
+++ b/part_2/ex8/db/ex8.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069275578 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069275579 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:21:15 2016 " "Processing started: Fri Nov 25 10:21:15 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069275579 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480069275579 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480069275579 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480069276308 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480069280806 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "891 " "Peak virtual memory: 891 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069281145 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:21:21 2016 " "Processing ended: Fri Nov 25 10:21:21 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069281145 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069281145 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069281145 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480069281145 ""}

diff --git a/part_2/ex8/db/ex8.asm.rdb b/part_2/ex8/db/ex8.asm.rdb
new file mode 100755
index 0000000..dfb3a37
--- /dev/null
+++ b/part_2/ex8/db/ex8.asm.rdb
diff --git a/part_2/ex8/db/ex8.cbx.xml b/part_2/ex8/db/ex8.cbx.xml
new file mode 100755
index 0000000..721f2cf
--- /dev/null
+++ b/part_2/ex8/db/ex8.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex8">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex8/db/ex8.cmp.ammdb b/part_2/ex8/db/ex8.cmp.ammdb
new file mode 100755
index 0000000..69804ca
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.ammdb
diff --git a/part_2/ex8/db/ex8.cmp.bpm b/part_2/ex8/db/ex8.cmp.bpm
new file mode 100755
index 0000000..c507a35
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.bpm
diff --git a/part_2/ex8/db/ex8.cmp.cdb b/part_2/ex8/db/ex8.cmp.cdb
new file mode 100755
index 0000000..02cc71a
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.cdb
diff --git a/part_2/ex8/db/ex8.cmp.hdb b/part_2/ex8/db/ex8.cmp.hdb
new file mode 100755
index 0000000..668f70d
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.hdb
diff --git a/part_2/ex8/db/ex8.cmp.idb b/part_2/ex8/db/ex8.cmp.idb
new file mode 100755
index 0000000..197cc17
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.idb
diff --git a/part_2/ex8/db/ex8.cmp.logdb b/part_2/ex8/db/ex8.cmp.logdb
new file mode 100755
index 0000000..b69cd55
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.logdb
@@ -0,0 +1,75 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,36;0;36;0;0;36;36;0;36;36;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,0;36;0;36;36;0;0;36;0;0;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex8/db/ex8.cmp.rdb b/part_2/ex8/db/ex8.cmp.rdb
new file mode 100755
index 0000000..e73dbf7
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.rdb
diff --git a/part_2/ex8/db/ex8.cmp_merge.kpt b/part_2/ex8/db/ex8.cmp_merge.kpt
new file mode 100755
index 0000000..214a1dd
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp_merge.kpt
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..da61997
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..acc52a8
--- /dev/null
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex8/db/ex8.db_info b/part_2/ex8/db/ex8.db_info
new file mode 100755
index 0000000..1c55704
--- /dev/null
+++ b/part_2/ex8/db/ex8.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

+Version_Index = 402707200

+Creation_Time = Fri Nov 25 09:03:31 2016

diff --git a/part_2/ex8/db/ex8.fit.qmsg b/part_2/ex8/db/ex8.fit.qmsg
new file mode 100755
index 0000000..5eedf90
--- /dev/null
+++ b/part_2/ex8/db/ex8.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480069241195 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480069241195 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480069241428 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069241476 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069241476 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480069241861 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480069241993 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480069252081 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 28 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480069252159 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480069252159 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069252160 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480069252162 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069252163 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069252164 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480069252164 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480069252164 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480069252165 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480069252738 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480069252739 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480069252739 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480069252742 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480069252742 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480069252743 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480069252745 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480069252746 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480069252746 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069252779 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480069252779 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069252781 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480069257842 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480069258034 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069258608 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480069259183 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480069260053 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069260053 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480069261137 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X67_Y0 X77_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10"} { { 12 { 0 ""} 67 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480069265623 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480069265623 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480069269026 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480069269026 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069269030 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.42 " "Total time spent on timing analysis during the Fitter is 0.42 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480069270334 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069270372 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069270735 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069270736 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069271090 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069273487 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480069273723 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480069273779 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 51 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 51 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2595 " "Peak virtual memory: 2595 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069274198 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:21:14 2016 " "Processing ended: Fri Nov 25 10:21:14 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069274198 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069274198 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:58 " "Total CPU time (on all processors): 00:00:58" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069274198 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480069274198 ""}

diff --git a/part_2/ex8/db/ex8.hier_info b/part_2/ex8/db/ex8.hier_info
new file mode 100755
index 0000000..70306ab
--- /dev/null
+++ b/part_2/ex8/db/ex8.hier_info
@@ -0,0 +1,669 @@
+|ex8

+CLOCK_50 => CLOCK_50.IN2

+KEY[0] => ~NO_FANOUT~

+KEY[1] => ~NO_FANOUT~

+KEY[2] => ~NO_FANOUT~

+KEY[3] => _.IN1

+HEX0[0] <= hex_to_7seg:SEG0.port0

+HEX0[1] <= hex_to_7seg:SEG0.port0

+HEX0[2] <= hex_to_7seg:SEG0.port0

+HEX0[3] <= hex_to_7seg:SEG0.port0

+HEX0[4] <= hex_to_7seg:SEG0.port0

+HEX0[5] <= hex_to_7seg:SEG0.port0

+HEX0[6] <= hex_to_7seg:SEG0.port0

+HEX1[0] <= hex_to_7seg:SEG1.port0

+HEX1[1] <= hex_to_7seg:SEG1.port0

+HEX1[2] <= hex_to_7seg:SEG1.port0

+HEX1[3] <= hex_to_7seg:SEG1.port0

+HEX1[4] <= hex_to_7seg:SEG1.port0

+HEX1[5] <= hex_to_7seg:SEG1.port0

+HEX1[6] <= hex_to_7seg:SEG1.port0

+HEX2[0] <= hex_to_7seg:SEG2.port0

+HEX2[1] <= hex_to_7seg:SEG2.port0

+HEX2[2] <= hex_to_7seg:SEG2.port0

+HEX2[3] <= hex_to_7seg:SEG2.port0

+HEX2[4] <= hex_to_7seg:SEG2.port0

+HEX2[5] <= hex_to_7seg:SEG2.port0

+HEX2[6] <= hex_to_7seg:SEG2.port0

+LEDR[0] <= formula_fsm:FSM.port6

+LEDR[1] <= formula_fsm:FSM.port6

+LEDR[2] <= formula_fsm:FSM.port6

+LEDR[3] <= formula_fsm:FSM.port6

+LEDR[4] <= formula_fsm:FSM.port6

+LEDR[5] <= formula_fsm:FSM.port6

+LEDR[6] <= formula_fsm:FSM.port6

+LEDR[7] <= formula_fsm:FSM.port6

+LEDR[8] <= formula_fsm:FSM.port6

+LEDR[9] <= formula_fsm:FSM.port6

+

+

+|ex8|tick_50000:TICK0

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => count[12].CLK

+CLOCK_IN => count[13].CLK

+CLOCK_IN => count[14].CLK

+CLOCK_IN => count[15].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|tick_2500:TICK1

+CLOCK_IN => count[0].CLK

+CLOCK_IN => count[1].CLK

+CLOCK_IN => count[2].CLK

+CLOCK_IN => count[3].CLK

+CLOCK_IN => count[4].CLK

+CLOCK_IN => count[5].CLK

+CLOCK_IN => count[6].CLK

+CLOCK_IN => count[7].CLK

+CLOCK_IN => count[8].CLK

+CLOCK_IN => count[9].CLK

+CLOCK_IN => count[10].CLK

+CLOCK_IN => count[11].CLK

+CLOCK_IN => CLK_OUT~reg0.CLK

+en => CLK_OUT.OUTPUTSELECT

+en => count[0].ENA

+en => count[1].ENA

+en => count[2].ENA

+en => count[3].ENA

+en => count[4].ENA

+en => count[5].ENA

+en => count[6].ENA

+en => count[7].ENA

+en => count[8].ENA

+en => count[9].ENA

+en => count[10].ENA

+en => count[11].ENA

+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|formula_fsm:FSM

+clk => state~3.DATAIN

+tick => ledr[0]~reg0.CLK

+tick => ledr[1]~reg0.CLK

+tick => ledr[2]~reg0.CLK

+tick => ledr[3]~reg0.CLK

+tick => ledr[4]~reg0.CLK

+tick => ledr[5]~reg0.CLK

+tick => ledr[6]~reg0.CLK

+tick => ledr[7]~reg0.CLK

+tick => ledr[8]~reg0.CLK

+tick => ledr[9]~reg0.CLK

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+time_out => state.OUTPUTSELECT

+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE

+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE

+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|LFSR:LFSR0

+CLK => COUNT[1]~reg0.CLK

+CLK => COUNT[2]~reg0.CLK

+CLK => COUNT[3]~reg0.CLK

+CLK => COUNT[4]~reg0.CLK

+CLK => COUNT[5]~reg0.CLK

+CLK => COUNT[6]~reg0.CLK

+CLK => COUNT[7]~reg0.CLK

+en => COUNT[1]~reg0.ENA

+en => COUNT[2]~reg0.ENA

+en => COUNT[3]~reg0.ENA

+en => COUNT[4]~reg0.ENA

+en => COUNT[5]~reg0.ENA

+en => COUNT[6]~reg0.ENA

+en => COUNT[7]~reg0.ENA

+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|delay:DEL0

+clk => count[0].CLK

+clk => count[1].CLK

+clk => count[2].CLK

+clk => count[3].CLK

+clk => count[4].CLK

+clk => count[5].CLK

+clk => count[6].CLK

+clk => count[7].CLK

+clk => count[8].CLK

+clk => count[9].CLK

+clk => count[10].CLK

+clk => count[11].CLK

+clk => count[12].CLK

+clk => count[13].CLK

+clk => state~4.DATAIN

+N[0] => count.DATAB

+N[1] => count.DATAB

+N[2] => count.DATAB

+N[3] => count.DATAB

+N[4] => count.DATAB

+N[5] => count.DATAB

+N[6] => count.DATAB

+N[7] => ~NO_FANOUT~

+N[8] => ~NO_FANOUT~

+N[9] => ~NO_FANOUT~

+N[10] => ~NO_FANOUT~

+N[11] => ~NO_FANOUT~

+N[12] => ~NO_FANOUT~

+N[13] => ~NO_FANOUT~

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => count.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector17.IN3

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => state.OUTPUTSELECT

+trigger => Selector14.IN2

+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD

+B[0] => BCD_0[0].DATAIN

+B[1] => w35[0].IN1

+B[2] => w30[0].IN1

+B[3] => w26[0].IN1

+B[4] => w22[0].IN1

+B[5] => w18[0].IN1

+B[6] => w15[0].IN1

+B[7] => w12[0].IN1

+B[8] => w9[0].IN1

+B[9] => w7[0].IN1

+B[10] => w5[0].IN1

+B[11] => w3[0].IN1

+B[12] => w2[0].IN1

+B[13] => w1[0].IN1

+B[14] => w1[1].IN1

+B[15] => w1[2].IN1

+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE

+BCD_0[1] <= add3_ge5:A35.port1

+BCD_0[2] <= add3_ge5:A35.port1

+BCD_0[3] <= add3_ge5:A35.port1

+BCD_1[0] <= add3_ge5:A35.port1

+BCD_1[1] <= add3_ge5:A34.port1

+BCD_1[2] <= add3_ge5:A34.port1

+BCD_1[3] <= add3_ge5:A34.port1

+BCD_2[0] <= add3_ge5:A34.port1

+BCD_2[1] <= add3_ge5:A33.port1

+BCD_2[2] <= add3_ge5:A33.port1

+BCD_2[3] <= add3_ge5:A33.port1

+BCD_3[0] <= add3_ge5:A33.port1

+BCD_3[1] <= add3_ge5:A32.port1

+BCD_3[2] <= add3_ge5:A32.port1

+BCD_3[3] <= add3_ge5:A32.port1

+BCD_4[0] <= add3_ge5:A32.port1

+BCD_4[1] <= add3_ge5:A31.port1

+BCD_4[2] <= add3_ge5:A31.port1

+BCD_4[3] <= add3_ge5:A31.port1

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A1

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A2

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A3

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A4

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A5

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A6

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A7

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A8

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A9

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A10

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A11

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A12

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A13

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A14

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A15

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A16

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A17

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A18

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A19

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A20

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A21

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A22

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A23

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A24

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A25

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A26

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A27

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A28

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A29

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A30

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A31

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A32

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A33

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A34

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|bin2bcd_16:BCD|add3_ge5:A35

+iW[0] => Decoder0.IN3

+iW[1] => Decoder0.IN2

+iW[2] => Decoder0.IN1

+iW[3] => Decoder0.IN0

+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+

+

+|ex8|hex_to_7seg:SEG0

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex8|hex_to_7seg:SEG1

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

+|ex8|hex_to_7seg:SEG2

+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE

+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE

+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE

+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE

+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE

+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE

+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE

+in[0] => Decoder0.IN3

+in[1] => Decoder0.IN2

+in[2] => Decoder0.IN1

+in[3] => Decoder0.IN0

+

+

diff --git a/part_2/ex8/db/ex8.hif b/part_2/ex8/db/ex8.hif
new file mode 100755
index 0000000..81f8f61
--- /dev/null
+++ b/part_2/ex8/db/ex8.hif
diff --git a/part_2/ex8/db/ex8.lpc.html b/part_2/ex8/db/ex8.lpc.html
new file mode 100755
index 0000000..b0b17d7
--- /dev/null
+++ b/part_2/ex8/db/ex8.lpc.html
@@ -0,0 +1,722 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+<TR >

+<TD >SEG2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG1</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >SEG0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A35</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A34</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A33</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A32</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A31</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A30</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A29</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A28</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A27</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A26</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A25</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A24</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A23</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A22</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A21</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A20</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A19</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A18</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A17</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A16</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A15</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A14</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A13</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A12</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A11</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A10</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A9</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A8</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A7</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A6</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A5</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A4</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A3</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A2</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD|A1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >4</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >BCD</TD>

+<TD >16</TD>

+<TD >9</TD>

+<TD >0</TD>

+<TD >9</TD>

+<TD >20</TD>

+<TD >9</TD>

+<TD >9</TD>

+<TD >9</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >DEL0</TD>

+<TD >16</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >1</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >LFSR0</TD>

+<TD >2</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >7</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >FSM</TD>

+<TD >4</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >12</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >TICK1</TD>

+<TD >2</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+<TR >

+<TD >TICK0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >1</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+<TD >0</TD>

+</TR>

+</TABLE>

diff --git a/part_2/ex8/db/ex8.lpc.rdb b/part_2/ex8/db/ex8.lpc.rdb
new file mode 100755
index 0000000..f107311
--- /dev/null
+++ b/part_2/ex8/db/ex8.lpc.rdb
diff --git a/part_2/ex8/db/ex8.lpc.txt b/part_2/ex8/db/ex8.lpc.txt
new file mode 100755
index 0000000..5e9734c
--- /dev/null
+++ b/part_2/ex8/db/ex8.lpc.txt
@@ -0,0 +1,50 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; BCD       ; 16    ; 9              ; 0            ; 9              ; 20     ; 9               ; 9             ; 9               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; FSM       ; 4     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; TICK1     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

+; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex8/db/ex8.map.ammdb b/part_2/ex8/db/ex8.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.ammdb
diff --git a/part_2/ex8/db/ex8.map.bpm b/part_2/ex8/db/ex8.map.bpm
new file mode 100755
index 0000000..e407061
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.bpm
diff --git a/part_2/ex8/db/ex8.map.cdb b/part_2/ex8/db/ex8.map.cdb
new file mode 100755
index 0000000..e054ff8
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.cdb
diff --git a/part_2/ex8/db/ex8.map.hdb b/part_2/ex8/db/ex8.map.hdb
new file mode 100755
index 0000000..4070275
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.hdb
diff --git a/part_2/ex8/db/ex8.map.kpt b/part_2/ex8/db/ex8.map.kpt
new file mode 100755
index 0000000..97786a3
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.kpt
diff --git a/part_2/ex8/db/ex8.map.logdb b/part_2/ex8/db/ex8.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex8/db/ex8.map.qmsg b/part_2/ex8/db/ex8.map.qmsg
new file mode 100755
index 0000000..c26ecb2
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.qmsg
@@ -0,0 +1,74 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069229728 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069229730 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:20:29 2016 " "Processing started: Fri Nov 25 10:20:29 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069229730 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069229730 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069229730 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480069230202 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480069230202 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238583 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238583 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238585 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238585 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238586 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238586 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238588 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238588 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238589 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238590 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238591 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238591 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238592 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238592 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480069238594 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238594 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238594 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069238595 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238595 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238595 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238597 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238597 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069238600 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238600 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480069238629 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex8.v" "TICK0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238635 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" {  } { { "verilog_files/ex8.v" "TICK1" { Text "C:/New folder/ex8/verilog_files/ex8.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238636 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex8.v" "FSM" { Text "C:/New folder/ex8/verilog_files/ex8.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238637 ""}

+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(37) " "Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 37 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 "|ex8|formula_fsm:comb_5"}

+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(47) " "Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 "|ex8|formula_fsm:comb_5"}

+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(47) " "Inferred latch for \"start_delay\" at formula_fsm.v(47)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 "|ex8|formula_fsm:comb_5"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex8.v" "LFSR0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238638 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex8.v" "DEL0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238639 ""}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480069238639 "|ex8|delay:comb_8"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex8.v" "BCD" { Text "C:/New folder/ex8/verilog_files/ex8.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238640 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238641 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex8.v" "SEG0" { Text "C:/New folder/ex8/verilog_files/ex8.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069238646 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480069239089 ""}

+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069239127 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069239127 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069239127 "|ex8|HEX2[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480069239127 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480069239203 ""}

+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480069239399 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069239421 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480069239504 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069239504 ""}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069239539 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069239539 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069239539 "|ex8|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480069239539 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "183 " "Implemented 183 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480069239540 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480069239540 ""} { "Info" "ICUT_CUT_TM_LCELLS" "147 " "Implemented 147 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480069239540 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480069239540 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "916 " "Peak virtual memory: 916 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069239553 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:20:39 2016 " "Processing ended: Fri Nov 25 10:20:39 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069239553 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069239553 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069239553 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069239553 ""}

diff --git a/part_2/ex8/db/ex8.map.rdb b/part_2/ex8/db/ex8.map.rdb
new file mode 100755
index 0000000..44ea2dd
--- /dev/null
+++ b/part_2/ex8/db/ex8.map.rdb
diff --git a/part_2/ex8/db/ex8.map_bb.cdb b/part_2/ex8/db/ex8.map_bb.cdb
new file mode 100755
index 0000000..652b850
--- /dev/null
+++ b/part_2/ex8/db/ex8.map_bb.cdb
diff --git a/part_2/ex8/db/ex8.map_bb.hdb b/part_2/ex8/db/ex8.map_bb.hdb
new file mode 100755
index 0000000..d485d10
--- /dev/null
+++ b/part_2/ex8/db/ex8.map_bb.hdb
diff --git a/part_2/ex8/db/ex8.map_bb.logdb b/part_2/ex8/db/ex8.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex8/db/ex8.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex8/db/ex8.pre_map.cdb b/part_2/ex8/db/ex8.pre_map.cdb
new file mode 100755
index 0000000..7e3e287
--- /dev/null
+++ b/part_2/ex8/db/ex8.pre_map.cdb
diff --git a/part_2/ex8/db/ex8.pre_map.hdb b/part_2/ex8/db/ex8.pre_map.hdb
new file mode 100755
index 0000000..b23e67a
--- /dev/null
+++ b/part_2/ex8/db/ex8.pre_map.hdb
diff --git a/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..f01a94f
--- /dev/null
+++ b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
diff --git a/part_2/ex8/db/ex8.routing.rdb b/part_2/ex8/db/ex8.routing.rdb
new file mode 100755
index 0000000..99de65e
--- /dev/null
+++ b/part_2/ex8/db/ex8.routing.rdb
diff --git a/part_2/ex8/db/ex8.rtlv.hdb b/part_2/ex8/db/ex8.rtlv.hdb
new file mode 100755
index 0000000..a81a06a
--- /dev/null
+++ b/part_2/ex8/db/ex8.rtlv.hdb
diff --git a/part_2/ex8/db/ex8.rtlv_sg.cdb b/part_2/ex8/db/ex8.rtlv_sg.cdb
new file mode 100755
index 0000000..74a197d
--- /dev/null
+++ b/part_2/ex8/db/ex8.rtlv_sg.cdb
diff --git a/part_2/ex8/db/ex8.rtlv_sg_swap.cdb b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..54c6f7c
--- /dev/null
+++ b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
diff --git a/part_2/ex8/db/ex8.sld_design_entry.sci b/part_2/ex8/db/ex8.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex8/db/ex8.sld_design_entry.sci
diff --git a/part_2/ex8/db/ex8.sld_design_entry_dsc.sci b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
diff --git a/part_2/ex8/db/ex8.smart_action.txt b/part_2/ex8/db/ex8.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex8/db/ex8.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex8/db/ex8.smp_dump.txt b/part_2/ex8/db/ex8.smp_dump.txt
new file mode 100755
index 0000000..04f2111
--- /dev/null
+++ b/part_2/ex8/db/ex8.smp_dump.txt
@@ -0,0 +1,13 @@
+

+State Machine - |ex8|delay:DEL0|state

+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 

+state.IDLE 0 0 0 0 

+state.COUNTING 0 0 1 1 

+state.TIME_OUT 0 1 0 1 

+state.WAIT_LOW 1 0 0 1 

+

+State Machine - |ex8|formula_fsm:FSM|state

+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 

+state.WAIT_TRIGGER 0 0 0 

+state.LIGHT_UP_LEDS 1 0 1 

+state.WAIT_FOR_TIMEOUT 1 1 0 

diff --git a/part_2/ex8/db/ex8.sta.qmsg b/part_2/ex8/db/ex8.sta.qmsg
new file mode 100755
index 0000000..69fb7fe
--- /dev/null
+++ b/part_2/ex8/db/ex8.sta.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069282649 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069282650 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:21:22 2016 " "Processing started: Fri Nov 25 10:21:22 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069282650 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069282650 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069282650 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069282780 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283327 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283327 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283377 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283377 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283871 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283890 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283890 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT " "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069283891 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283891 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283893 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283898 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069283899 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069283906 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069283924 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283924 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.828 " "Worst-case setup slack is -4.828" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.828             -90.826 CLOCK_50  " "   -4.828             -90.826 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.650             -63.464 tick_50000:TICK0\|CLK_OUT  " "   -2.650             -63.464 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.004             -18.612 tick_2500:TICK1\|CLK_OUT  " "   -2.004             -18.612 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.489              -1.489 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.489              -1.489 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283926 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283926 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.283 " "Worst-case hold slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.283               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.283               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.376               0.000 CLOCK_50  " "    0.376               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.424               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.424               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.523               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.523               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283929 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283929 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283931 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283933 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.636 " "Worst-case minimum pulse width slack is -0.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.636             -25.765 CLOCK_50  " "   -0.636             -25.765 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -14.976 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -14.976 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.130 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.130 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.404               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.404               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069283934 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283934 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069283945 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069283979 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284794 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284844 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069284850 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284850 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.731 " "Worst-case setup slack is -4.731" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.731             -86.467 CLOCK_50  " "   -4.731             -86.467 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.603             -61.065 tick_50000:TICK0\|CLK_OUT  " "   -2.603             -61.065 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.916             -17.960 tick_2500:TICK1\|CLK_OUT  " "   -1.916             -17.960 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.373              -1.373 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.373              -1.373 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284851 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284851 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.283 " "Worst-case hold slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.283               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.283               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.287               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.287               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.389               0.000 CLOCK_50  " "    0.389               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.530               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.530               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284854 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284854 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284856 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284857 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.690 " "Worst-case minimum pulse width slack is -0.690" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.690             -23.719 CLOCK_50  " "   -0.690             -23.719 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -14.868 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -14.868 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.140 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.140 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.384               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.384               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069284859 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069284859 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069284870 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285012 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285704 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285750 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069285752 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285752 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.046 " "Worst-case setup slack is -4.046" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.046             -58.106 CLOCK_50  " "   -4.046             -58.106 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.373             -12.517 tick_2500:TICK1\|CLK_OUT  " "   -1.373             -12.517 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.359             -32.665 tick_50000:TICK0\|CLK_OUT  " "   -1.359             -32.665 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.480              -0.480 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.480              -0.480 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285754 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285754 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.023 " "Worst-case hold slack is 0.023" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.023               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.023               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.061               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.061               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.092               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.092               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.182               0.000 CLOCK_50  " "    0.182               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285757 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285757 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285759 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285761 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.760 " "Worst-case minimum pulse width slack is -0.760" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.760             -18.549 CLOCK_50  " "   -0.760             -18.549 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.049               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.049               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.131               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.131               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.469               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.469               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285762 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285762 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069285773 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285920 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069285922 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285922 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.445 " "Worst-case setup slack is -3.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.445             -47.547 CLOCK_50  " "   -3.445             -47.547 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.171             -10.740 tick_2500:TICK1\|CLK_OUT  " "   -1.171             -10.740 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.164             -27.696 tick_50000:TICK0\|CLK_OUT  " "   -1.164             -27.696 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.362              -0.362 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.362              -0.362 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285924 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285924 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.013 " "Worst-case hold slack is 0.013" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.013               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.013               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.014               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.014               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.024               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172               0.000 CLOCK_50  " "    0.172               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285927 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285927 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285929 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285930 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.812 " "Worst-case minimum pulse width slack is -0.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.812             -22.016 CLOCK_50  " "   -0.812             -22.016 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.076               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.076               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.135               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.465               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.465               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069285932 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069285932 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069287278 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069287278 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1209 " "Peak virtual memory: 1209 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069287320 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:21:27 2016 " "Processing ended: Fri Nov 25 10:21:27 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069287320 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069287320 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069287320 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069287320 ""}

diff --git a/part_2/ex8/db/ex8.sta.rdb b/part_2/ex8/db/ex8.sta.rdb
new file mode 100755
index 0000000..18c12e2
--- /dev/null
+++ b/part_2/ex8/db/ex8.sta.rdb
diff --git a/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..cc7aaf1
--- /dev/null
+++ b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex8/db/ex8.tis_db_list.ddb b/part_2/ex8/db/ex8.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_2/ex8/db/ex8.tis_db_list.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..058f4f0
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..57389e8
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..cc60683
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..c35046f
--- /dev/null
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex8/db/ex8.tmw_info b/part_2/ex8/db/ex8.tmw_info
new file mode 100755
index 0000000..97862be
--- /dev/null
+++ b/part_2/ex8/db/ex8.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:01:00

+start_analysis_synthesis:s:00:00:12-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:00:34-start_full_compilation

+start_assembler:s:00:00:07-start_full_compilation

+start_timing_analyzer:s:00:00:07-start_full_compilation

diff --git a/part_2/ex8/db/ex8.vpr.ammdb b/part_2/ex8/db/ex8.vpr.ammdb
new file mode 100755
index 0000000..0f304da
--- /dev/null
+++ b/part_2/ex8/db/ex8.vpr.ammdb
diff --git a/part_2/ex8/db/ex8_partition_pins.json b/part_2/ex8/db/ex8_partition_pins.json
new file mode 100755
index 0000000..ad28bfb
--- /dev/null
+++ b/part_2/ex8/db/ex8_partition_pins.json
@@ -0,0 +1,129 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "HEX0[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX0[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[1]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[2]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[5]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX1[6]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[0]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[3]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[4]",

+					"strict" : false

+				},

+				{

+					"name" : "HEX2[5]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[0]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[1]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[2]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[3]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[4]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[5]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[6]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[7]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[8]",

+					"strict" : false

+				},

+				{

+					"name" : "LEDR[9]",

+					"strict" : false

+				},

+				{

+					"name" : "KEY[3]",

+					"strict" : false

+				},

+				{

+					"name" : "CLOCK_50",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex8/db/prev_cmp_ex8.qmsg b/part_2/ex8/db/prev_cmp_ex8.qmsg
new file mode 100755
index 0000000..ddafb7b
--- /dev/null
+++ b/part_2/ex8/db/prev_cmp_ex8.qmsg
@@ -0,0 +1,195 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480069024021 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069024023 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:03 2016 " "Processing started: Fri Nov 25 10:17:03 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069024023 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069024023 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069024023 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480069024479 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480069024480 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032679 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032679 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032681 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032681 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032682 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032682 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032684 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032684 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032686 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032687 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032687 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032688 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032688 ""}

+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480069032691 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032692 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032692 ""}

+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480069032693 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032693 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032693 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032695 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032695 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480069032696 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032696 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(13) " "Verilog HDL Instantiation warning at ex8.v(13): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 13 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032697 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(14) " "Verilog HDL Instantiation warning at ex8.v(14): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 14 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(15) " "Verilog HDL Instantiation warning at ex8.v(15): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 15 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(16) " "Verilog HDL Instantiation warning at ex8.v(16): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 16 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(17) " "Verilog HDL Instantiation warning at ex8.v(17): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 17 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(18) " "Verilog HDL Instantiation warning at ex8.v(18): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 18 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(19) " "Verilog HDL Instantiation warning at ex8.v(19): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 19 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "ex8.v(20) " "Verilog HDL Instantiation warning at ex8.v(20): instance has no name" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 20 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480069032698 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480069032724 ""}

+{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX2 ex8.v(6) " "Output port \"HEX2\" at ex8.v(6) has no driver" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1480069032725 "|ex8"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:comb_3 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:comb_3\"" {  } { { "verilog_files/ex8.v" "comb_3" { Text "C:/New folder/ex8/verilog_files/ex8.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032725 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:comb_4 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:comb_4\"" {  } { { "verilog_files/ex8.v" "comb_4" { Text "C:/New folder/ex8/verilog_files/ex8.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032726 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:comb_5 " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:comb_5\"" {  } { { "verilog_files/ex8.v" "comb_5" { Text "C:/New folder/ex8/verilog_files/ex8.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032727 ""}

+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(37) " "Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 37 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480069032728 "|ex8|formula_fsm:comb_5"}

+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(47) " "Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480069032728 "|ex8|formula_fsm:comb_5"}

+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(47) " "Inferred latch for \"start_delay\" at formula_fsm.v(47)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069032728 "|ex8|formula_fsm:comb_5"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:comb_7 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:comb_7\"" {  } { { "verilog_files/ex8.v" "comb_7" { Text "C:/New folder/ex8/verilog_files/ex8.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032734 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:comb_8 " "Elaborating entity \"delay\" for hierarchy \"delay:comb_8\"" {  } { { "verilog_files/ex8.v" "comb_8" { Text "C:/New folder/ex8/verilog_files/ex8.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032735 ""}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex8/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480069032736 "|ex8|delay:comb_8"}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:comb_9 " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:comb_9\"" {  } { { "verilog_files/ex8.v" "comb_9" { Text "C:/New folder/ex8/verilog_files/ex8.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032737 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:comb_9\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:comb_9\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032738 ""}

+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:comb_10 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:comb_10\"" {  } { { "verilog_files/ex8.v" "comb_10" { Text "C:/New folder/ex8/verilog_files/ex8.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069032743 ""}

+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480069033183 ""}

+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[0\] GND " "Pin \"HEX2\[0\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[3\] GND " "Pin \"HEX2\[3\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[4\] GND " "Pin \"HEX2\[4\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[5\] GND " "Pin \"HEX2\[5\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] GND " "Pin \"HEX2\[6\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480069033220 "|ex8|HEX2[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480069033220 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480069033295 ""}

+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480069033491 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069033516 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480069033599 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480069033599 ""}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069033635 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069033635 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex8.v" "" { Text "C:/New folder/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480069033635 "|ex8|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480069033635 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "182 " "Implemented 182 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480069033636 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480069033636 ""} { "Info" "ICUT_CUT_TM_LCELLS" "146 " "Implemented 146 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480069033636 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480069033636 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "914 " "Peak virtual memory: 914 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069033648 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:17:13 2016 " "Processing ended: Fri Nov 25 10:17:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069033648 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069033648 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069033648 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480069033648 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1480069035073 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069035074 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:14 2016 " "Processing started: Fri Nov 25 10:17:14 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069035074 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480069035074 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480069035074 ""}

+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480069035195 ""}

+{ "Info" "0" "" "Project  = ex8" {  } {  } 0 0 "Project  = ex8" 0 0 "Fitter" 0 0 1480069035195 ""}

+{ "Info" "0" "" "Revision = ex8" {  } {  } 0 0 "Revision = ex8" 0 0 "Fitter" 0 0 1480069035195 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480069035310 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480069035311 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480069035571 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069035633 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480069035633 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480069036022 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480069036154 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480069046211 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 28 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480069046288 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480069046288 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069046288 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480069046291 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069046291 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480069046292 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480069046292 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480069046293 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480069046293 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480069046865 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480069046866 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480069046866 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480069046869 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480069046869 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480069046870 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480069046872 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480069046873 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480069046873 ""}

+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480069046907 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480069046907 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069046909 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480069051902 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480069052104 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069052666 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480069053236 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480069054137 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069054138 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480069055233 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480069059723 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480069059723 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480069063963 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480069063963 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069063968 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.43 " "Total time spent on timing analysis during the Fitter is 0.43 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480069065291 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069065331 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069065698 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480069065698 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480069066056 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480069068455 ""}

+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480069068691 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file C:/New folder/ex8/output_files/ex8.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480069068745 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 51 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 51 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2630 " "Peak virtual memory: 2630 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069069180 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:17:49 2016 " "Processing ended: Fri Nov 25 10:17:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069069180 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:35 " "Elapsed time: 00:00:35" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069069180 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:58 " "Total CPU time (on all processors): 00:00:58" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069069180 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480069069180 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480069070489 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069070491 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:50 2016 " "Processing started: Fri Nov 25 10:17:50 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069070491 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480069070491 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480069070492 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480069071266 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480069075853 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "889 " "Peak virtual memory: 889 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069076193 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:17:56 2016 " "Processing ended: Fri Nov 25 10:17:56 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069076193 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069076193 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069076193 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480069076193 ""}

+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480069076843 ""}

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480069077652 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480069077653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 10:17:57 2016 " "Processing started: Fri Nov 25 10:17:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480069077653 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069077653 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069077653 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069077776 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078333 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078333 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078381 ""}

+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078381 ""}

+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078878 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078898 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078898 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:comb_3\|CLK_OUT tick_50000:comb_3\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:comb_3\|CLK_OUT tick_50000:comb_3\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_2500:comb_4\|CLK_OUT tick_2500:comb_4\|CLK_OUT " "create_clock -period 1.000 -name tick_2500:comb_4\|CLK_OUT tick_2500:comb_4\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:comb_5\|state.LIGHT_UP_LEDS formula_fsm:comb_5\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:comb_5\|state.LIGHT_UP_LEDS formula_fsm:comb_5\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480069078899 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078899 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078900 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078906 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069078906 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069078913 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069078929 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078929 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.713 " "Worst-case setup slack is -3.713" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.713             -89.478 CLOCK_50  " "   -3.713             -89.478 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.069             -68.001 tick_50000:comb_3\|CLK_OUT  " "   -3.069             -68.001 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.865             -17.220 tick_2500:comb_4\|CLK_OUT  " "   -1.865             -17.220 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.559              -1.559 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -1.559              -1.559 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078931 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078931 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.282 " "Worst-case hold slack is 0.282" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.282               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.282               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.376               0.000 CLOCK_50  " "    0.376               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.380               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.380               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.425               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.425               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078934 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078934 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078935 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078937 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.679 " "Worst-case minimum pulse width slack is -0.679" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.679             -25.746 CLOCK_50  " "   -0.679             -25.746 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -15.156 tick_50000:comb_3\|CLK_OUT  " "   -0.394             -15.156 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.330 tick_2500:comb_4\|CLK_OUT  " "   -0.394              -5.330 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.461               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.461               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069078939 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078939 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069078950 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069078985 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079799 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079849 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069079855 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079855 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.511 " "Worst-case setup slack is -3.511" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.511             -84.954 CLOCK_50  " "   -3.511             -84.954 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.976             -66.210 tick_50000:comb_3\|CLK_OUT  " "   -2.976             -66.210 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.912             -17.517 tick_2500:comb_4\|CLK_OUT  " "   -1.912             -17.517 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.528              -1.528 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -1.528              -1.528 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079857 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079857 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.265 " "Worst-case hold slack is 0.265" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.265               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.265               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.285               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.285               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.374               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.374               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.392               0.000 CLOCK_50  " "    0.392               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079859 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079859 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079861 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079862 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.722 " "Worst-case minimum pulse width slack is -0.722" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.722             -23.943 CLOCK_50  " "   -0.722             -23.943 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -14.998 tick_50000:comb_3\|CLK_OUT  " "   -0.394             -14.998 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.250 tick_2500:comb_4\|CLK_OUT  " "   -0.394              -5.250 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.444               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.444               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069079864 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069079864 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069079874 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080017 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080708 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080756 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069080758 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080758 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.058 " "Worst-case setup slack is -3.058" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.058             -53.489 CLOCK_50  " "   -3.058             -53.489 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.522             -33.572 tick_50000:comb_3\|CLK_OUT  " "   -1.522             -33.572 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.243             -11.298 tick_2500:comb_4\|CLK_OUT  " "   -1.243             -11.298 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.459              -0.459 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -0.459              -0.459 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080760 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080760 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.004 " "Worst-case hold slack is 0.004" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.004               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.004               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.023               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.023               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.095               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.095               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.182               0.000 CLOCK_50  " "    0.182               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080763 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080763 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080764 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080766 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.801 " "Worst-case minimum pulse width slack is -0.801" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.801             -18.381 CLOCK_50  " "   -0.801             -18.381 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.108               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.108               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.120               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.120               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.491               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.491               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080767 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080767 ""}

+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480069080778 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080927 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480069080929 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080929 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.570 " "Worst-case setup slack is -2.570" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.570             -43.622 CLOCK_50  " "   -2.570             -43.622 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.344             -29.187 tick_50000:comb_3\|CLK_OUT  " "   -1.344             -29.187 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.091              -9.985 tick_2500:comb_4\|CLK_OUT  " "   -1.091              -9.985 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.376              -0.376 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -0.376              -0.376 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080931 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080931 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.039 " "Worst-case hold slack is -0.039" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.039              -0.039 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "   -0.039              -0.039 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.035              -0.155 tick_2500:comb_4\|CLK_OUT  " "   -0.035              -0.155 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.076               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.076               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.174               0.000 CLOCK_50  " "    0.174               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080934 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080934 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080936 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080938 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.840 " "Worst-case minimum pulse width slack is -0.840" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.840             -21.816 CLOCK_50  " "   -0.840             -21.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.123               0.000 tick_50000:comb_3\|CLK_OUT  " "    0.123               0.000 tick_50000:comb_3\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 tick_2500:comb_4\|CLK_OUT  " "    0.135               0.000 tick_2500:comb_4\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.485               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS  " "    0.485               0.000 formula_fsm:comb_5\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480069080939 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069080939 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069082294 ""}

+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069082295 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1210 " "Peak virtual memory: 1210 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480069082337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 10:18:02 2016 " "Processing ended: Fri Nov 25 10:18:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480069082337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480069082337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480069082337 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069082337 ""}

+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 84 s " "Quartus Prime Full Compilation was successful. 0 errors, 84 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480069083091 ""}