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author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
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committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_2/ex9_final/verilog_files/ex9.v.bak | |
parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip |
adding full files to github, with all updates
Diffstat (limited to 'part_2/ex9_final/verilog_files/ex9.v.bak')
-rwxr-xr-x | part_2/ex9_final/verilog_files/ex9.v.bak | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/part_2/ex9_final/verilog_files/ex9.v.bak b/part_2/ex9_final/verilog_files/ex9.v.bak deleted file mode 100755 index 6ca51d6..0000000 --- a/part_2/ex9_final/verilog_files/ex9.v.bak +++ /dev/null @@ -1,23 +0,0 @@ -module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-
- input CLOCK_50;
- input [3:0] KEY;
- output [9:0] LEDR;
- output [6:0] HEX0, HEX1, HEX2;
-
- wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
- wire [6:0] N;
- wire [6:0] bcd_to_hex;
- wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-
- tick_50000 TICK0(CLOCK_50, tick_ms);
- tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
- formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
- LFSR LFSR0(tick_ms, en_lfsr, N);
- delay DEL0(tick_ms, N, start_delay, time_out);
- bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
- hex_to_7seg SEG0(HEX0, BCD_0);
- hex_to_7seg SEG1(HEX1, BCD_1);
- hex_to_7seg SEG2(HEX2, BCD_2);
-
-endmodule
\ No newline at end of file |