adding full files to github, with all updates

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-# -------------------------------------------------------------------------- #

-#

-# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.

-# Your use of Altera Corporation's design tools, logic functions 

-# and other software and tools, and its AMPP partner logic 

-# functions, and any output files from any of the foregoing 

-# (including device programming or simulation files), and any 

-# associated documentation or information are expressly subject 

-# to the terms and conditions of the Altera Program License 

-# Subscription Agreement, the Altera Quartus Prime License Agreement,

-# the Altera MegaCore Function License Agreement, or other 

-# applicable license agreement, including, without limitation, 

-# that your use is for the sole purpose of programming logic 

-# devices manufactured by Altera and sold by Altera or its 

-# authorized distributors.  Please refer to the applicable 

-# agreement for further details.

-#

-# -------------------------------------------------------------------------- #

-#

-# Quartus Prime

-# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition

-# Date created = 10:28:00  November 25, 2016

-#

-# -------------------------------------------------------------------------- #

-#

-# Notes:

-#

-# 1) The default values for assignments are stored in the file:

-#		ex9_assignment_defaults.qdf

-#    If this file doesn't exist, see file:

-#		assignment_defaults.qdf

-#

-# 2) Altera recommends that you do not modify this file. This

-#    file is updated automatically by the Quartus Prime software

-#    and any changes you make may be lost or overwritten.

-#

-# -------------------------------------------------------------------------- #

-

-

-set_global_assignment -name FAMILY "Cyclone V"

-set_global_assignment -name DEVICE 5CSEMA5F31C6

-set_global_assignment -name TOP_LEVEL_ENTITY ex9

-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0

-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"

-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0

-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

-set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v

-set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v

-set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v

-set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v

-set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v

-set_global_assignment -name VERILOG_FILE verilog_files/delay.v

-set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v

-set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v

-set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v

-set_global_assignment -name VERILOG_FILE verilog_files/ex9.v

-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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