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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex11/ex11.v.bak | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex11/ex11.v.bak')
| -rwxr-xr-x | part_3/ex11/ex11.v.bak | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/part_3/ex11/ex11.v.bak b/part_3/ex11/ex11.v.bak new file mode 100755 index 0000000..62a30d0 --- /dev/null +++ b/part_3/ex11/ex11.v.bak @@ -0,0 +1,13 @@ +module ex11(CLOCK_50, SW, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK);
+
+ input CLOCK_50;
+ input [9:0] SW;
+ output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK;
+
+ wire load;
+
+ tick_5000 t(CLOCK_50, load);
+ spi2dac s(CLOCK_50, SW, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
+ pwm p(CLOCK_50, SW, load, PWM_OUT);
+
+endmodule
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