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| author | ymherklotz <ymherklotz@gmail.com> | 2016-12-11 16:37:13 +0000 |
|---|---|---|
| committer | ymherklotz <ymherklotz@gmail.com> | 2016-12-11 16:37:13 +0000 |
| commit | 47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731 (patch) | |
| tree | 3b6ca2e93e2ad9fd56d4286af311c3c880c09068 /part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do | |
| parent | 137e647c057d471bd0a26fa037b1ef575a2568e7 (diff) | |
| download | VerilogCoursework-47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731.tar.gz VerilogCoursework-47665d0ff2ee13848f4b5b2e3a36d7f4e8b08731.zip | |
updated part 2
Diffstat (limited to 'part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do')
| -rwxr-xr-x | part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do index b12a7d7..52dd5a2 100755 --- a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do +++ b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do @@ -1,17 +1,17 @@ -add wave -position end sysclk -add wave -position end -hexadecimal data_in -add wave -position end load -add wave -position end dac_sdi -add wave -position end dac_cs -add wave -position end dac_sck -add wave -position end dac_ld -force sysclk 1 0, 0 10ns -r 20ns -force data_in 10'h23b -force load 0 -run 200ns -force load 1 -run 400ns -force load 0 -run 20us - - +add wave -position end sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end dac_sdi
+add wave -position end dac_cs
+add wave -position end dac_sck
+add wave -position end dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
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