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| author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
| commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
| tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do | |
| parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
| download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip | |
adding full files to github, with all updates
Diffstat (limited to 'part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do')
| -rwxr-xr-x | part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do index 52dd5a2..b12a7d7 100755 --- a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do +++ b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do @@ -1,17 +1,17 @@ -add wave -position end sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end dac_sdi
-add wave -position end dac_cs
-add wave -position end dac_sck
-add wave -position end dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end sysclk +add wave -position end -hexadecimal data_in +add wave -position end load +add wave -position end dac_sdi +add wave -position end dac_cs +add wave -position end dac_sck +add wave -position end dac_ld +force sysclk 1 0, 0 10ns -r 20ns +force data_in 10'h23b +force load 0 +run 200ns +force load 1 +run 400ns +force load 0 +run 20us + + |