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| author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
| commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
| tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex11/simulation/modelsim/rtl_work/_vmake | |
| parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
| download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip | |
adding full files to github, with all updates
Diffstat (limited to 'part_3/ex11/simulation/modelsim/rtl_work/_vmake')
| -rwxr-xr-x | part_3/ex11/simulation/modelsim/rtl_work/_vmake | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_vmake b/part_3/ex11/simulation/modelsim/rtl_work/_vmake index b51b305..2f7e729 100755 --- a/part_3/ex11/simulation/modelsim/rtl_work/_vmake +++ b/part_3/ex11/simulation/modelsim/rtl_work/_vmake @@ -1,3 +1,3 @@ -m255
-K3
-cModel Technology
+m255 +K3 +cModel Technology |