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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex11/verilog_files/tick_5000.v | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex11/verilog_files/tick_5000.v')
| -rwxr-xr-x | part_3/ex11/verilog_files/tick_5000.v | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/part_3/ex11/verilog_files/tick_5000.v b/part_3/ex11/verilog_files/tick_5000.v new file mode 100755 index 0000000..a048386 --- /dev/null +++ b/part_3/ex11/verilog_files/tick_5000.v @@ -0,0 +1,32 @@ +module tick_5000(CLOCK_IN, CLK_OUT);
+
+ parameter NBIT = 16;
+
+ input CLOCK_IN;
+ output CLK_OUT;
+
+ reg [NBIT-1:0] count;
+
+ reg CLK_OUT;
+
+ initial
+ begin
+ count = 16'd4999;
+ CLK_OUT = 1'b0;
+ end
+
+ always @ (posedge CLOCK_IN)
+ begin
+ if(count == 16'b0)
+ begin
+ CLK_OUT <= 1'b1;
+ count <= 16'd4999;
+ end
+ else
+ begin
+ count <= count - 1'b1;
+ CLK_OUT <= 1'b0;
+ end
+ end
+
+endmodule
\ No newline at end of file |