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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex12/output_files/ex12.jdi | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex12/output_files/ex12.jdi')
| -rwxr-xr-x | part_3/ex12/output_files/ex12.jdi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/part_3/ex12/output_files/ex12.jdi b/part_3/ex12/output_files/ex12.jdi new file mode 100755 index 0000000..19da7dc --- /dev/null +++ b/part_3/ex12/output_files/ex12.jdi @@ -0,0 +1,8 @@ +<sld_project_info>
+ <project>
+ <hash md5_digest_80b="7eece59e299d53d4f2fa"/>
+ </project>
+ <file_info>
+ <file device="5CSEMA5F31C6" path="ex12.sof" usercode="0xFFFFFFFF"/>
+ </file_info>
+</sld_project_info>
|