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author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
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committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd | |
parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip |
adding full files to github, with all updates
Diffstat (limited to 'part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd')
-rwxr-xr-x | part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd index 2a503c0..e874ed3 100755 --- a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd +++ b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd @@ -1,30 +1,30 @@ -library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
- generic(
- BUF : vl_logic := Hi1;
- GA_N : vl_logic := Hi1;
- SHDN_N : vl_logic := Hi1;
- TC : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
- IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0);
- WAIT_CSB_FALL : vl_logic_vector(0 to 1) := (Hi0, Hi1);
- WAIT_CSB_HIGH : vl_logic_vector(0 to 1) := (Hi1, Hi0)
- );
- port(
- sysclk : in vl_logic;
- data_in : in vl_logic_vector(9 downto 0);
- load : in vl_logic;
- dac_sdi : out vl_logic;
- dac_cs : out vl_logic;
- dac_sck : out vl_logic;
- dac_ld : out vl_logic
- );
- attribute mti_svvh_generic_type : integer;
- attribute mti_svvh_generic_type of BUF : constant is 1;
- attribute mti_svvh_generic_type of GA_N : constant is 1;
- attribute mti_svvh_generic_type of SHDN_N : constant is 1;
- attribute mti_svvh_generic_type of TC : constant is 1;
- attribute mti_svvh_generic_type of IDLE : constant is 1;
- attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
- attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog; +use verilog.vl_types.all; +entity spi2dac is + generic( + BUF : vl_logic := Hi1; + GA_N : vl_logic := Hi1; + SHDN_N : vl_logic := Hi1; + TC : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0); + IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0); + WAIT_CSB_FALL : vl_logic_vector(0 to 1) := (Hi0, Hi1); + WAIT_CSB_HIGH : vl_logic_vector(0 to 1) := (Hi1, Hi0) + ); + port( + sysclk : in vl_logic; + data_in : in vl_logic_vector(9 downto 0); + load : in vl_logic; + dac_sdi : out vl_logic; + dac_cs : out vl_logic; + dac_sck : out vl_logic; + dac_ld : out vl_logic + ); + attribute mti_svvh_generic_type : integer; + attribute mti_svvh_generic_type of BUF : constant is 1; + attribute mti_svvh_generic_type of GA_N : constant is 1; + attribute mti_svvh_generic_type of SHDN_N : constant is 1; + attribute mti_svvh_generic_type of TC : constant is 1; + attribute mti_svvh_generic_type of IDLE : constant is 1; + attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1; + attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1; +end spi2dac; |