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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex13/verilog_files/counter_10.v | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex13/verilog_files/counter_10.v')
| -rwxr-xr-x | part_3/ex13/verilog_files/counter_10.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/part_3/ex13/verilog_files/counter_10.v b/part_3/ex13/verilog_files/counter_10.v new file mode 100755 index 0000000..72c96fa --- /dev/null +++ b/part_3/ex13/verilog_files/counter_10.v @@ -0,0 +1,18 @@ +`timescale 1ns / 100ps
+
+module counter_10(clock,enable,count);
+
+ parameter BIT_SZ = 10;
+ input clock;
+ input enable;
+ output [BIT_SZ-1:0] count;
+
+ reg [BIT_SZ-1:0] count;
+
+ initial count = 0;
+
+ always @ (posedge clock)
+ if(enable == 1'b1)
+ count <= count + 1'b1;
+
+endmodule
\ No newline at end of file |