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| author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
| commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
| tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex14/.qsys_edit/preferences.xml | |
| parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
| download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip | |
adding full files to github, with all updates
Diffstat (limited to 'part_3/ex14/.qsys_edit/preferences.xml')
| -rwxr-xr-x | part_3/ex14/.qsys_edit/preferences.xml | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/part_3/ex14/.qsys_edit/preferences.xml b/part_3/ex14/.qsys_edit/preferences.xml new file mode 100755 index 0000000..c5b7680 --- /dev/null +++ b/part_3/ex14/.qsys_edit/preferences.xml @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8"?> +<preferences> + <debug showDebugMenu="0" /> + <systemtable filter="All Interfaces"> + <columns> + <connections preferredWidth="47" /> + <irq preferredWidth="34" /> + </columns> + </systemtable> + <library expandedCategories="Project,Library" /> + <window width="1100" height="800" x="0" y="0" /> +</preferences> |