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| author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
| commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
| tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex14/add_offset.v | |
| parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
| download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip | |
adding full files to github, with all updates
Diffstat (limited to 'part_3/ex14/add_offset.v')
| -rwxr-xr-x | part_3/ex14/add_offset.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/part_3/ex14/add_offset.v b/part_3/ex14/add_offset.v new file mode 100755 index 0000000..02882fb --- /dev/null +++ b/part_3/ex14/add_offset.v @@ -0,0 +1,14 @@ +module add_offset(keys, tick, address);
+
+ input [9:0] keys;
+ input tick;
+ output [9:0] address;
+
+ reg [9:0] address;
+
+ initial address = 10'b0;
+
+ always @ (posedge tick)
+ address = keys + address;
+
+endmodule
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