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authorzedarider <ymherklotz@gmail.com>2016-12-12 13:19:22 +0000
committerzedarider <ymherklotz@gmail.com>2016-12-12 13:19:22 +0000
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tree9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex14/ex10.qpf
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downloadVerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz
VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip
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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 09:17:00 November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "09:17:00 November 29, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex10"