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| author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
| commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
| tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex14/verilog_files/tick_5000.v.bak | |
| parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
| download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip | |
adding full files to github, with all updates
Diffstat (limited to 'part_3/ex14/verilog_files/tick_5000.v.bak')
| -rwxr-xr-x | part_3/ex14/verilog_files/tick_5000.v.bak | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/part_3/ex14/verilog_files/tick_5000.v.bak b/part_3/ex14/verilog_files/tick_5000.v.bak new file mode 100755 index 0000000..97fcf8b --- /dev/null +++ b/part_3/ex14/verilog_files/tick_5000.v.bak @@ -0,0 +1,32 @@ +module tick_50000(CLOCK_IN, CLK_OUT);
+
+ parameter NBIT = 16;
+
+ input CLOCK_IN;
+ output CLK_OUT;
+
+ reg [NBIT-1:0] count;
+
+ reg CLK_OUT;
+
+ initial
+ begin
+ count = 16'd4999;
+ CLK_OUT = 1'b0;
+ end
+
+ always @ (posedge CLOCK_IN)
+ begin
+ if(count == 16'b0)
+ begin
+ CLK_OUT <= 1'b1;
+ count <= 16'd49999;
+ end
+ else
+ begin
+ count <= count - 1'b1;
+ CLK_OUT <= 1'b0;
+ end
+ end
+
+endmodule
\ No newline at end of file |