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author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
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committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/ex15/output_files/ex10.map.summary | |
parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip |
adding full files to github, with all updates
Diffstat (limited to 'part_3/ex15/output_files/ex10.map.summary')
-rwxr-xr-x | part_3/ex15/output_files/ex10.map.summary | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/part_3/ex15/output_files/ex10.map.summary b/part_3/ex15/output_files/ex10.map.summary new file mode 100755 index 0000000..e8914b6 --- /dev/null +++ b/part_3/ex15/output_files/ex10.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Fri Dec 02 18:31:20 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex10
+Top-level Entity Name : ex15
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 110
+Total pins : 45
+Total virtual pins : 0
+Total block memory bits : 10,240
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
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