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| author | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-12 13:19:22 +0000 |
| commit | aee06a47eca6d7f5532a10e59e394fd33904670a (patch) | |
| tree | 9abf1adeec021a72863f1bfc8e1270513b26f1cb /part_3/mylib/add3_ge5.v | |
| parent | c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff) | |
| download | VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip | |
adding full files to github, with all updates
Diffstat (limited to 'part_3/mylib/add3_ge5.v')
| -rwxr-xr-x | part_3/mylib/add3_ge5.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/part_3/mylib/add3_ge5.v b/part_3/mylib/add3_ge5.v new file mode 100755 index 0000000..65a561d --- /dev/null +++ b/part_3/mylib/add3_ge5.v @@ -0,0 +1,25 @@ +module add3_ge5(w,a);
+ output [3:0] a;
+ input [3:0] w;
+
+ reg [3:0] a;
+
+ always @ (w)
+ case(w)
+ 4'b0000: a <= 4'b0000;
+ 4'b0001: a <= 4'b0001;
+ 4'b0010: a <= 4'b0010;
+ 4'b0011: a <= 4'b0011;
+ 4'b0100: a <= 4'b0100;
+ 4'b0101: a <= 4'b1000;
+ 4'b0110: a <= 4'b1001;
+ 4'b0111: a <= 4'b1010;
+ 4'b1000: a <= 4'b1011;
+ 4'b1001: a <= 4'b1100;
+ 4'b1010: a <= 4'b1101;
+ 4'b1011: a <= 4'b1110;
+ 4'b1100: a <= 4'b1111;
+
+ default: a <= 4'b0000;
+ endcase
+endmodule
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