1 files changed, 0 insertions, 31 deletions
diff --git a/part_2/ex9_final/verilog_files/counter_16.v b/part_2/ex9_final/verilog_files/counter_16.v
deleted file mode 100755
index 79c144c..0000000
--- a/part_2/ex9_final/verilog_files/counter_16.v
+++ /dev/null
@@ -1,31 +0,0 @@
-module counter_16(clock, start, stop, count);
-
-	parameter BIT_SZ = 16;
-	input clock, start, stop;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	reg state;
-	
-	parameter COUNTING = 1'b1, IDLE = 1'b0;
-	
-	initial count = 0;
-	initial state = IDLE;
-	
-	always @ (posedge clock)
-		case(state)
-			IDLE:
-				if(start == 1'b1)
-					begin
-						count = 0;
-						state = COUNTING;
-					end
-			COUNTING:
-				if(stop == 1'b1)
-					state <= IDLE;
-				else
-					count <= count + 1'b1;
-		endcase
-			
-endmodule
-\ No newline at end of file