diff options
Diffstat (limited to 'part_3/ex11/simulation')
16 files changed, 4489 insertions, 0 deletions
diff --git a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do new file mode 100755 index 0000000..b12a7d7 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do @@ -0,0 +1,17 @@ +add wave -position end sysclk +add wave -position end -hexadecimal data_in +add wave -position end load +add wave -position end dac_sdi +add wave -position end dac_cs +add wave -position end dac_sck +add wave -position end dac_ld +force sysclk 1 0, 0 10ns -r 20ns +force data_in 10'h23b +force load 0 +run 200ns +force load 1 +run 400ns +force load 0 +run 20us + + diff --git a/part_3/ex11/simulation/modelsim/ex10.sft b/part_3/ex11/simulation/modelsim/ex10.sft new file mode 100755 index 0000000..f324fea --- /dev/null +++ b/part_3/ex11/simulation/modelsim/ex10.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)"
diff --git a/part_3/ex11/simulation/modelsim/ex10.vo b/part_3/ex11/simulation/modelsim/ex10.vo new file mode 100755 index 0000000..1c3e82f --- /dev/null +++ b/part_3/ex11/simulation/modelsim/ex10.vo @@ -0,0 +1,3869 @@ +// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, the Altera Quartus Prime License Agreement,
+// the Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of programming logic
+// devices manufactured by Altera and sold by Altera or its
+// authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition"
+
+// DATE "11/29/2016 11:05:49"
+
+//
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+//
+
+//
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+//
+
+`timescale 1 ps/ 1 ps
+
+module ex11 (
+ CLOCK_50,
+ SW,
+ DAC_CS,
+ DAC_SDI,
+ DAC_LD,
+ DAC_SCK,
+ PWM_OUT);
+input CLOCK_50;
+input [9:0] SW;
+output DAC_CS;
+output DAC_SDI;
+output DAC_LD;
+output DAC_SCK;
+output PWM_OUT;
+
+// Design Ports Information
+// DAC_CS => Location: PIN_AD20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
+// DAC_SDI => Location: PIN_AG18, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
+// DAC_LD => Location: PIN_AK21, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
+// DAC_SCK => Location: PIN_AF20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
+// PWM_OUT => Location: PIN_AJ20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
+// CLOCK_50 => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[3] => Location: PIN_AF10, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[2] => Location: PIN_AF9, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[1] => Location: PIN_AC12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[0] => Location: PIN_AB12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[5] => Location: PIN_AD12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[7] => Location: PIN_AC9, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[6] => Location: PIN_AE11, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[4] => Location: PIN_AD11, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[9] => Location: PIN_AE12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+// SW[8] => Location: PIN_AD10, I/O Standard: 3.3-V LVTTL, Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \CLOCK_50~input_o ;
+wire \CLOCK_50~inputCLKENA0_outclk ;
+wire \s|Add0~0_combout ;
+wire \s|ctr~1_combout ;
+wire \s|ctr[0]~DUPLICATE_q ;
+wire \s|ctr~2_combout ;
+wire \s|Add0~1_combout ;
+wire \s|ctr[3]~DUPLICATE_q ;
+wire \s|ctr~0_combout ;
+wire \s|clk_1MHz~0_combout ;
+wire \s|clk_1MHz~q ;
+wire \s|state~0_combout ;
+wire \s|state[4]~DUPLICATE_q ;
+wire \s|state~1_combout ;
+wire \s|state~2_combout ;
+wire \s|state[2]~DUPLICATE_q ;
+wire \s|state~3_combout ;
+wire \t|Add0~9_sumout ;
+wire \t|count[0]~1_combout ;
+wire \t|Add0~10 ;
+wire \t|Add0~13_sumout ;
+wire \t|count[1]~2_combout ;
+wire \t|Add0~14 ;
+wire \t|Add0~17_sumout ;
+wire \t|count[2]~3_combout ;
+wire \t|count[2]~DUPLICATE_q ;
+wire \t|Add0~18 ;
+wire \t|Add0~53_sumout ;
+wire \t|Add0~54 ;
+wire \t|Add0~49_sumout ;
+wire \t|Add0~50 ;
+wire \t|Add0~5_sumout ;
+wire \t|Add0~6 ;
+wire \t|Add0~57_sumout ;
+wire \t|count[6]~DUPLICATE_q ;
+wire \t|count[11]~DUPLICATE_q ;
+wire \t|Add0~58 ;
+wire \t|Add0~21_sumout ;
+wire \t|count[7]~4_combout ;
+wire \t|Add0~22 ;
+wire \t|Add0~25_sumout ;
+wire \t|count[8]~5_combout ;
+wire \t|count[8]~DUPLICATE_q ;
+wire \t|Add0~26 ;
+wire \t|Add0~1_sumout ;
+wire \t|count[9]~0_combout ;
+wire \t|Add0~2 ;
+wire \t|Add0~33_sumout ;
+wire \t|Add0~34 ;
+wire \t|Add0~61_sumout ;
+wire \t|count[4]~DUPLICATE_q ;
+wire \t|Equal0~2_combout ;
+wire \t|Add0~62 ;
+wire \t|Add0~29_sumout ;
+wire \t|count[12]~6_combout ;
+wire \t|Add0~30 ;
+wire \t|Add0~37_sumout ;
+wire \t|Add0~38 ;
+wire \t|Add0~41_sumout ;
+wire \t|count[14]~DUPLICATE_q ;
+wire \t|Add0~42 ;
+wire \t|Add0~45_sumout ;
+wire \t|Equal0~1_combout ;
+wire \t|count[7]~DUPLICATE_q ;
+wire \t|Equal0~0_combout ;
+wire \t|Equal0~3_combout ;
+wire \t|CLK_OUT~q ;
+wire \s|sr_state.IDLE~0_combout ;
+wire \s|sr_state.IDLE~q ;
+wire \s|Selector2~0_combout ;
+wire \s|sr_state.WAIT_CSB_HIGH~q ;
+wire \s|sr_state.WAIT_CSB_FALL~0_combout ;
+wire \s|sr_state.WAIT_CSB_FALL~q ;
+wire \s|Selector3~0_combout ;
+wire \s|WideNor0~combout ;
+wire \SW[9]~input_o ;
+wire \s|shift_reg[11]~feeder_combout ;
+wire \SW[8]~input_o ;
+wire \s|shift_reg[10]~feeder_combout ;
+wire \SW[7]~input_o ;
+wire \s|shift_reg[9]~feeder_combout ;
+wire \SW[6]~input_o ;
+wire \s|shift_reg[8]~feeder_combout ;
+wire \SW[5]~input_o ;
+wire \s|shift_reg[7]~feeder_combout ;
+wire \SW[4]~input_o ;
+wire \s|shift_reg[6]~feeder_combout ;
+wire \SW[3]~input_o ;
+wire \s|shift_reg[5]~feeder_combout ;
+wire \SW[2]~input_o ;
+wire \s|shift_reg[4]~feeder_combout ;
+wire \SW[1]~input_o ;
+wire \s|shift_reg[3]~feeder_combout ;
+wire \SW[0]~input_o ;
+wire \s|shift_reg~4_combout ;
+wire \s|always5~0_combout ;
+wire \s|shift_reg~3_combout ;
+wire \s|shift_reg~2_combout ;
+wire \s|shift_reg~1_combout ;
+wire \s|shift_reg~0_combout ;
+wire \s|Equal2~0_combout ;
+wire \s|dac_sck~combout ;
+wire \p|count[0]~0_combout ;
+wire \p|Add0~9_sumout ;
+wire \p|Add0~10 ;
+wire \p|Add0~5_sumout ;
+wire \p|Add0~6 ;
+wire \p|Add0~1_sumout ;
+wire \p|Add0~2 ;
+wire \p|Add0~25_sumout ;
+wire \p|Add0~26 ;
+wire \p|Add0~13_sumout ;
+wire \p|Add0~14 ;
+wire \p|Add0~21_sumout ;
+wire \p|Add0~22 ;
+wire \p|Add0~17_sumout ;
+wire \p|LessThan0~2_combout ;
+wire \p|LessThan0~3_combout ;
+wire \p|Add0~18 ;
+wire \p|Add0~33_sumout ;
+wire \p|count[8]~DUPLICATE_q ;
+wire \p|Add0~34 ;
+wire \p|Add0~29_sumout ;
+wire \p|LessThan0~7_combout ;
+wire \p|d[1]~feeder_combout ;
+wire \p|LessThan0~0_combout ;
+wire \p|LessThan0~1_combout ;
+wire \p|LessThan0~6_combout ;
+wire \p|LessThan0~4_combout ;
+wire \p|LessThan0~5_combout ;
+wire \p|LessThan0~8_combout ;
+wire \p|pwm_out~q ;
+wire [9:0] \p|count ;
+wire [15:0] \t|count ;
+wire [15:0] \s|shift_reg ;
+wire [4:0] \s|state ;
+wire [9:0] \p|d ;
+wire [4:0] \s|ctr ;
+
+
+// Location: IOOBUF_X82_Y0_N42
+cyclonev_io_obuf \DAC_CS~output (
+ .i(\s|WideNor0~combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(DAC_CS),
+ .obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+defparam \DAC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X58_Y0_N76
+cyclonev_io_obuf \DAC_SDI~output (
+ .i(\s|shift_reg [15]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(DAC_SDI),
+ .obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+defparam \DAC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y0_N36
+cyclonev_io_obuf \DAC_LD~output (
+ .i(!\s|Equal2~0_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(DAC_LD),
+ .obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+defparam \DAC_LD~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N2
+cyclonev_io_obuf \DAC_SCK~output (
+ .i(!\s|dac_sck~combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(DAC_SCK),
+ .obar());
+// synopsys translate_off
+defparam \DAC_SCK~output .bus_hold = "false";
+defparam \DAC_SCK~output .open_drain_output = "false";
+defparam \DAC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N36
+cyclonev_io_obuf \PWM_OUT~output (
+ .i(\p|pwm_out~q ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(16'b0000000000000000),
+ .parallelterminationcontrol(16'b0000000000000000),
+ .devoe(devoe),
+ .o(PWM_OUT),
+ .obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+defparam \PWM_OUT~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X32_Y0_N1
+cyclonev_io_ibuf \CLOCK_50~input (
+ .i(CLOCK_50),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G6
+cyclonev_clkena \CLOCK_50~inputCLKENA0 (
+ .inclk(\CLOCK_50~input_o ),
+ .ena(vcc),
+ .outclk(\CLOCK_50~inputCLKENA0_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \CLOCK_50~inputCLKENA0 .clock_type = "global clock";
+defparam \CLOCK_50~inputCLKENA0 .disable_mode = "low";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_mode = "always enabled";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_power_up = "high";
+defparam \CLOCK_50~inputCLKENA0 .test_syn = "high";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N42
+cyclonev_lcell_comb \s|Add0~0 (
+// Equation(s):
+// \s|Add0~0_combout = ( \s|ctr[3]~DUPLICATE_q & ( \s|ctr [4] ) ) # ( !\s|ctr[3]~DUPLICATE_q & ( !\s|ctr [4] $ ((((\s|ctr [1]) # (\s|ctr[0]~DUPLICATE_q )) # (\s|ctr [2]))) ) )
+
+ .dataa(!\s|ctr [2]),
+ .datab(!\s|ctr[0]~DUPLICATE_q ),
+ .datac(!\s|ctr [1]),
+ .datad(!\s|ctr [4]),
+ .datae(gnd),
+ .dataf(!\s|ctr[3]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|Add0~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|Add0~0 .extended_lut = "off";
+defparam \s|Add0~0 .lut_mask = 64'h807F807F00FF00FF;
+defparam \s|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N44
+dffeas \s|ctr[4] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|Add0~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|ctr [4]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|ctr[4] .is_wysiwyg = "true";
+defparam \s|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N8
+dffeas \s|ctr[0] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|ctr~1_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|ctr [0]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|ctr[0] .is_wysiwyg = "true";
+defparam \s|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N6
+cyclonev_lcell_comb \s|ctr~1 (
+// Equation(s):
+// \s|ctr~1_combout = ( !\s|ctr [0] & ( \s|ctr[3]~DUPLICATE_q ) ) # ( !\s|ctr [0] & ( !\s|ctr[3]~DUPLICATE_q & ( ((\s|ctr [2]) # (\s|ctr [4])) # (\s|ctr [1]) ) ) )
+
+ .dataa(!\s|ctr [1]),
+ .datab(!\s|ctr [4]),
+ .datac(!\s|ctr [2]),
+ .datad(gnd),
+ .datae(!\s|ctr [0]),
+ .dataf(!\s|ctr[3]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|ctr~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|ctr~1 .extended_lut = "off";
+defparam \s|ctr~1 .lut_mask = 64'h7F7F0000FFFF0000;
+defparam \s|ctr~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N7
+dffeas \s|ctr[0]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|ctr~1_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|ctr[0]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|ctr[0]~DUPLICATE .is_wysiwyg = "true";
+defparam \s|ctr[0]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N49
+dffeas \s|ctr[3] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|Add0~1_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|ctr [3]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|ctr[3] .is_wysiwyg = "true";
+defparam \s|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N45
+cyclonev_lcell_comb \s|ctr~2 (
+// Equation(s):
+// \s|ctr~2_combout = ( \s|ctr [4] & ( !\s|ctr[0]~DUPLICATE_q $ (\s|ctr [1]) ) ) # ( !\s|ctr [4] & ( (!\s|ctr[0]~DUPLICATE_q & (!\s|ctr [1] & ((\s|ctr [3]) # (\s|ctr [2])))) # (\s|ctr[0]~DUPLICATE_q & (((\s|ctr [1])))) ) )
+
+ .dataa(!\s|ctr [2]),
+ .datab(!\s|ctr[0]~DUPLICATE_q ),
+ .datac(!\s|ctr [3]),
+ .datad(!\s|ctr [1]),
+ .datae(gnd),
+ .dataf(!\s|ctr [4]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|ctr~2_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|ctr~2 .extended_lut = "off";
+defparam \s|ctr~2 .lut_mask = 64'h4C334C33CC33CC33;
+defparam \s|ctr~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N47
+dffeas \s|ctr[1] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|ctr~2_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|ctr [1]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|ctr[1] .is_wysiwyg = "true";
+defparam \s|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N48
+cyclonev_lcell_comb \s|Add0~1 (
+// Equation(s):
+// \s|Add0~1_combout = ( \s|ctr [3] & ( \s|ctr[0]~DUPLICATE_q ) ) # ( \s|ctr [3] & ( !\s|ctr[0]~DUPLICATE_q & ( (\s|ctr [1]) # (\s|ctr [2]) ) ) ) # ( !\s|ctr [3] & ( !\s|ctr[0]~DUPLICATE_q & ( (!\s|ctr [2] & !\s|ctr [1]) ) ) )
+
+ .dataa(!\s|ctr [2]),
+ .datab(!\s|ctr [1]),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(!\s|ctr [3]),
+ .dataf(!\s|ctr[0]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|Add0~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|Add0~1 .extended_lut = "off";
+defparam \s|Add0~1 .lut_mask = 64'h888877770000FFFF;
+defparam \s|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N50
+dffeas \s|ctr[3]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|Add0~1_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|ctr[3]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|ctr[3]~DUPLICATE .is_wysiwyg = "true";
+defparam \s|ctr[3]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N3
+cyclonev_lcell_comb \s|ctr~0 (
+// Equation(s):
+// \s|ctr~0_combout = ( \s|ctr [2] & ( \s|ctr[0]~DUPLICATE_q ) ) # ( \s|ctr [2] & ( !\s|ctr[0]~DUPLICATE_q & ( \s|ctr [1] ) ) ) # ( !\s|ctr [2] & ( !\s|ctr[0]~DUPLICATE_q & ( (!\s|ctr [1] & ((\s|ctr [4]) # (\s|ctr[3]~DUPLICATE_q ))) ) ) )
+
+ .dataa(!\s|ctr[3]~DUPLICATE_q ),
+ .datab(!\s|ctr [4]),
+ .datac(!\s|ctr [1]),
+ .datad(gnd),
+ .datae(!\s|ctr [2]),
+ .dataf(!\s|ctr[0]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|ctr~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|ctr~0 .extended_lut = "off";
+defparam \s|ctr~0 .lut_mask = 64'h70700F0F0000FFFF;
+defparam \s|ctr~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N5
+dffeas \s|ctr[2] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|ctr~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|ctr [2]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|ctr[2] .is_wysiwyg = "true";
+defparam \s|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N54
+cyclonev_lcell_comb \s|clk_1MHz~0 (
+// Equation(s):
+// \s|clk_1MHz~0_combout = ( \s|ctr [1] & ( \s|ctr [4] & ( \s|clk_1MHz~q ) ) ) # ( !\s|ctr [1] & ( \s|ctr [4] & ( \s|clk_1MHz~q ) ) ) # ( \s|ctr [1] & ( !\s|ctr [4] & ( \s|clk_1MHz~q ) ) ) # ( !\s|ctr [1] & ( !\s|ctr [4] & ( !\s|clk_1MHz~q $ ((((\s|ctr
+// [3]) # (\s|ctr [0])) # (\s|ctr [2]))) ) ) )
+
+ .dataa(!\s|ctr [2]),
+ .datab(!\s|ctr [0]),
+ .datac(!\s|clk_1MHz~q ),
+ .datad(!\s|ctr [3]),
+ .datae(!\s|ctr [1]),
+ .dataf(!\s|ctr [4]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|clk_1MHz~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|clk_1MHz~0 .extended_lut = "off";
+defparam \s|clk_1MHz~0 .lut_mask = 64'h870F0F0F0F0F0F0F;
+defparam \s|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N35
+dffeas \s|clk_1MHz (
+ .clk(\CLOCK_50~input_o ),
+ .d(gnd),
+ .asdata(\s|clk_1MHz~0_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|clk_1MHz~q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|clk_1MHz .is_wysiwyg = "true";
+defparam \s|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N0
+cyclonev_lcell_comb \s|state~0 (
+// Equation(s):
+// \s|state~0_combout = ( \s|state [0] & ( (!\s|state [3] & (\s|state[4]~DUPLICATE_q & ((\s|state [1]) # (\s|state[2]~DUPLICATE_q )))) # (\s|state [3] & (!\s|state[4]~DUPLICATE_q $ (((!\s|state[2]~DUPLICATE_q ) # (!\s|state [1]))))) ) ) # ( !\s|state [0]
+// & ( \s|state[4]~DUPLICATE_q ) )
+
+ .dataa(!\s|state[4]~DUPLICATE_q ),
+ .datab(!\s|state [3]),
+ .datac(!\s|state[2]~DUPLICATE_q ),
+ .datad(!\s|state [1]),
+ .datae(gnd),
+ .dataf(!\s|state [0]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|state~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|state~0 .extended_lut = "off";
+defparam \s|state~0 .lut_mask = 64'h5555555515561556;
+defparam \s|state~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N20
+dffeas \s|state[4]~DUPLICATE (
+ .clk(\s|clk_1MHz~q ),
+ .d(gnd),
+ .asdata(\s|state~0_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|state[4]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|state[4]~DUPLICATE .is_wysiwyg = "true";
+defparam \s|state[4]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N30
+cyclonev_lcell_comb \s|state~1 (
+// Equation(s):
+// \s|state~1_combout = ( \s|state[4]~DUPLICATE_q & ( (!\s|state [1] & (\s|state [0] & ((\s|state [3]) # (\s|state[2]~DUPLICATE_q )))) # (\s|state [1] & (!\s|state [0])) ) ) # ( !\s|state[4]~DUPLICATE_q & ( !\s|state [1] $ (!\s|state [0]) ) )
+
+ .dataa(!\s|state [1]),
+ .datab(!\s|state [0]),
+ .datac(!\s|state[2]~DUPLICATE_q ),
+ .datad(!\s|state [3]),
+ .datae(gnd),
+ .dataf(!\s|state[4]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|state~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|state~1 .extended_lut = "off";
+defparam \s|state~1 .lut_mask = 64'h6666666646664666;
+defparam \s|state~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N47
+dffeas \s|state[1] (
+ .clk(\s|clk_1MHz~q ),
+ .d(gnd),
+ .asdata(\s|state~1_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|state [1]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|state[1] .is_wysiwyg = "true";
+defparam \s|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N45
+cyclonev_lcell_comb \s|state~2 (
+// Equation(s):
+// \s|state~2_combout = !\s|state[2]~DUPLICATE_q $ (((!\s|state [0]) # (!\s|state [1])))
+
+ .dataa(!\s|state[2]~DUPLICATE_q ),
+ .datab(gnd),
+ .datac(!\s|state [0]),
+ .datad(!\s|state [1]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|state~2_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|state~2 .extended_lut = "off";
+defparam \s|state~2 .lut_mask = 64'h555A555A555A555A;
+defparam \s|state~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N56
+dffeas \s|state[2]~DUPLICATE (
+ .clk(\s|clk_1MHz~q ),
+ .d(gnd),
+ .asdata(\s|state~2_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|state[2]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|state[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \s|state[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N39
+cyclonev_lcell_comb \s|state~3 (
+// Equation(s):
+// \s|state~3_combout = !\s|state [3] $ (((!\s|state[2]~DUPLICATE_q ) # ((!\s|state [1]) # (!\s|state [0]))))
+
+ .dataa(!\s|state[2]~DUPLICATE_q ),
+ .datab(!\s|state [3]),
+ .datac(!\s|state [1]),
+ .datad(!\s|state [0]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|state~3_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|state~3 .extended_lut = "off";
+defparam \s|state~3 .lut_mask = 64'h3336333633363336;
+defparam \s|state~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N32
+dffeas \s|state[3] (
+ .clk(\s|clk_1MHz~q ),
+ .d(gnd),
+ .asdata(\s|state~3_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|state [3]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|state[3] .is_wysiwyg = "true";
+defparam \s|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N55
+dffeas \s|state[2] (
+ .clk(\s|clk_1MHz~q ),
+ .d(gnd),
+ .asdata(\s|state~2_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|state [2]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|state[2] .is_wysiwyg = "true";
+defparam \s|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N20
+dffeas \t|count[6] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~57_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [6]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[6] .is_wysiwyg = "true";
+defparam \t|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N0
+cyclonev_lcell_comb \t|Add0~9 (
+// Equation(s):
+// \t|Add0~9_sumout = SUM(( !\t|count [0] ) + ( VCC ) + ( !VCC ))
+// \t|Add0~10 = CARRY(( !\t|count [0] ) + ( VCC ) + ( !VCC ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count [0]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~9_sumout ),
+ .cout(\t|Add0~10 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~9 .extended_lut = "off";
+defparam \t|Add0~9 .lut_mask = 64'h000000000000FF00;
+defparam \t|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X10_Y3_N15
+cyclonev_lcell_comb \t|count[0]~1 (
+// Equation(s):
+// \t|count[0]~1_combout = ( !\t|Add0~9_sumout )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(!\t|Add0~9_sumout ),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|count[0]~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|count[0]~1 .extended_lut = "off";
+defparam \t|count[0]~1 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \t|count[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N56
+dffeas \t|count[0] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\t|count[0]~1_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [0]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[0] .is_wysiwyg = "true";
+defparam \t|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N3
+cyclonev_lcell_comb \t|Add0~13 (
+// Equation(s):
+// \t|Add0~13_sumout = SUM(( !\t|count [1] ) + ( VCC ) + ( \t|Add0~10 ))
+// \t|Add0~14 = CARRY(( !\t|count [1] ) + ( VCC ) + ( \t|Add0~10 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count [1]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~10 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~13_sumout ),
+ .cout(\t|Add0~14 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~13 .extended_lut = "off";
+defparam \t|Add0~13 .lut_mask = 64'h000000000000FF00;
+defparam \t|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N57
+cyclonev_lcell_comb \t|count[1]~2 (
+// Equation(s):
+// \t|count[1]~2_combout = !\t|Add0~13_sumout
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|Add0~13_sumout ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|count[1]~2_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|count[1]~2 .extended_lut = "off";
+defparam \t|count[1]~2 .lut_mask = 64'hFF00FF00FF00FF00;
+defparam \t|count[1]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N59
+dffeas \t|count[1] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[1]~2_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [1]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[1] .is_wysiwyg = "true";
+defparam \t|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N6
+cyclonev_lcell_comb \t|Add0~17 (
+// Equation(s):
+// \t|Add0~17_sumout = SUM(( !\t|count[2]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~14 ))
+// \t|Add0~18 = CARRY(( !\t|count[2]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~14 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count[2]~DUPLICATE_q ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~14 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~17_sumout ),
+ .cout(\t|Add0~18 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~17 .extended_lut = "off";
+defparam \t|Add0~17 .lut_mask = 64'h000000000000FF00;
+defparam \t|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X10_Y3_N57
+cyclonev_lcell_comb \t|count[2]~3 (
+// Equation(s):
+// \t|count[2]~3_combout = ( !\t|Add0~17_sumout )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(!\t|Add0~17_sumout ),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|count[2]~3_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|count[2]~3 .extended_lut = "off";
+defparam \t|count[2]~3 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \t|count[2]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X10_Y3_N58
+dffeas \t|count[2]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[2]~3_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count[2]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \t|count[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N9
+cyclonev_lcell_comb \t|Add0~53 (
+// Equation(s):
+// \t|Add0~53_sumout = SUM(( \t|count [3] ) + ( VCC ) + ( \t|Add0~18 ))
+// \t|Add0~54 = CARRY(( \t|count [3] ) + ( VCC ) + ( \t|Add0~18 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count [3]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~18 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~53_sumout ),
+ .cout(\t|Add0~54 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~53 .extended_lut = "off";
+defparam \t|Add0~53 .lut_mask = 64'h00000000000000FF;
+defparam \t|Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N10
+dffeas \t|count[3] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~53_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [3]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[3] .is_wysiwyg = "true";
+defparam \t|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N12
+cyclonev_lcell_comb \t|Add0~49 (
+// Equation(s):
+// \t|Add0~49_sumout = SUM(( \t|count [4] ) + ( VCC ) + ( \t|Add0~54 ))
+// \t|Add0~50 = CARRY(( \t|count [4] ) + ( VCC ) + ( \t|Add0~54 ))
+
+ .dataa(gnd),
+ .datab(!\t|count [4]),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~54 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~49_sumout ),
+ .cout(\t|Add0~50 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~49 .extended_lut = "off";
+defparam \t|Add0~49 .lut_mask = 64'h0000000000003333;
+defparam \t|Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N14
+dffeas \t|count[4] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~49_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [4]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[4] .is_wysiwyg = "true";
+defparam \t|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N15
+cyclonev_lcell_comb \t|Add0~5 (
+// Equation(s):
+// \t|Add0~5_sumout = SUM(( \t|count [5] ) + ( VCC ) + ( \t|Add0~50 ))
+// \t|Add0~6 = CARRY(( \t|count [5] ) + ( VCC ) + ( \t|Add0~50 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\t|count [5]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~50 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~5_sumout ),
+ .cout(\t|Add0~6 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~5 .extended_lut = "off";
+defparam \t|Add0~5 .lut_mask = 64'h0000000000000F0F;
+defparam \t|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N16
+dffeas \t|count[5] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~5_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [5]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[5] .is_wysiwyg = "true";
+defparam \t|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N18
+cyclonev_lcell_comb \t|Add0~57 (
+// Equation(s):
+// \t|Add0~57_sumout = SUM(( \t|count [6] ) + ( VCC ) + ( \t|Add0~6 ))
+// \t|Add0~58 = CARRY(( \t|count [6] ) + ( VCC ) + ( \t|Add0~6 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\t|count [6]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~6 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~57_sumout ),
+ .cout(\t|Add0~58 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~57 .extended_lut = "off";
+defparam \t|Add0~57 .lut_mask = 64'h0000000000000F0F;
+defparam \t|Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N19
+dffeas \t|count[6]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~57_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count[6]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[6]~DUPLICATE .is_wysiwyg = "true";
+defparam \t|count[6]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N35
+dffeas \t|count[11]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~61_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count[11]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[11]~DUPLICATE .is_wysiwyg = "true";
+defparam \t|count[11]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N21
+cyclonev_lcell_comb \t|Add0~21 (
+// Equation(s):
+// \t|Add0~21_sumout = SUM(( !\t|count [7] ) + ( VCC ) + ( \t|Add0~58 ))
+// \t|Add0~22 = CARRY(( !\t|count [7] ) + ( VCC ) + ( \t|Add0~58 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count [7]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~58 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~21_sumout ),
+ .cout(\t|Add0~22 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~21 .extended_lut = "off";
+defparam \t|Add0~21 .lut_mask = 64'h000000000000FF00;
+defparam \t|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X10_Y3_N6
+cyclonev_lcell_comb \t|count[7]~4 (
+// Equation(s):
+// \t|count[7]~4_combout = ( !\t|Add0~21_sumout )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(!\t|Add0~21_sumout ),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|count[7]~4_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|count[7]~4 .extended_lut = "off";
+defparam \t|count[7]~4 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \t|count[7]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X10_Y3_N7
+dffeas \t|count[7] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[7]~4_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [7]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[7] .is_wysiwyg = "true";
+defparam \t|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N24
+cyclonev_lcell_comb \t|Add0~25 (
+// Equation(s):
+// \t|Add0~25_sumout = SUM(( !\t|count[8]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~22 ))
+// \t|Add0~26 = CARRY(( !\t|count[8]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~22 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count[8]~DUPLICATE_q ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~22 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~25_sumout ),
+ .cout(\t|Add0~26 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~25 .extended_lut = "off";
+defparam \t|Add0~25 .lut_mask = 64'h000000000000FF00;
+defparam \t|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X10_Y3_N48
+cyclonev_lcell_comb \t|count[8]~5 (
+// Equation(s):
+// \t|count[8]~5_combout = ( !\t|Add0~25_sumout )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\t|Add0~25_sumout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|count[8]~5_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|count[8]~5 .extended_lut = "off";
+defparam \t|count[8]~5 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \t|count[8]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X10_Y3_N49
+dffeas \t|count[8]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[8]~5_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count[8]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[8]~DUPLICATE .is_wysiwyg = "true";
+defparam \t|count[8]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N27
+cyclonev_lcell_comb \t|Add0~1 (
+// Equation(s):
+// \t|Add0~1_sumout = SUM(( !\t|count [9] ) + ( VCC ) + ( \t|Add0~26 ))
+// \t|Add0~2 = CARRY(( !\t|count [9] ) + ( VCC ) + ( \t|Add0~26 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count [9]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~26 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~1_sumout ),
+ .cout(\t|Add0~2 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~1 .extended_lut = "off";
+defparam \t|Add0~1 .lut_mask = 64'h000000000000FF00;
+defparam \t|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X12_Y3_N15
+cyclonev_lcell_comb \t|count[9]~0 (
+// Equation(s):
+// \t|count[9]~0_combout = ( !\t|Add0~1_sumout )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(!\t|Add0~1_sumout ),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|count[9]~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|count[9]~0 .extended_lut = "off";
+defparam \t|count[9]~0 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \t|count[9]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X12_Y3_N17
+dffeas \t|count[9] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[9]~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [9]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[9] .is_wysiwyg = "true";
+defparam \t|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N30
+cyclonev_lcell_comb \t|Add0~33 (
+// Equation(s):
+// \t|Add0~33_sumout = SUM(( \t|count [10] ) + ( VCC ) + ( \t|Add0~2 ))
+// \t|Add0~34 = CARRY(( \t|count [10] ) + ( VCC ) + ( \t|Add0~2 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\t|count [10]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~2 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~33_sumout ),
+ .cout(\t|Add0~34 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~33 .extended_lut = "off";
+defparam \t|Add0~33 .lut_mask = 64'h0000000000000F0F;
+defparam \t|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N31
+dffeas \t|count[10] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~33_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [10]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[10] .is_wysiwyg = "true";
+defparam \t|count[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N33
+cyclonev_lcell_comb \t|Add0~61 (
+// Equation(s):
+// \t|Add0~61_sumout = SUM(( \t|count[11]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~34 ))
+// \t|Add0~62 = CARRY(( \t|count[11]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~34 ))
+
+ .dataa(!\t|count[11]~DUPLICATE_q ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~34 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~61_sumout ),
+ .cout(\t|Add0~62 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~61 .extended_lut = "off";
+defparam \t|Add0~61 .lut_mask = 64'h0000000000005555;
+defparam \t|Add0~61 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N34
+dffeas \t|count[11] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~61_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [11]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[11] .is_wysiwyg = "true";
+defparam \t|count[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N13
+dffeas \t|count[4]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~49_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count[4]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[4]~DUPLICATE .is_wysiwyg = "true";
+defparam \t|count[4]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X12_Y3_N45
+cyclonev_lcell_comb \t|Equal0~2 (
+// Equation(s):
+// \t|Equal0~2_combout = ( !\t|count[4]~DUPLICATE_q & ( !\t|count [3] & ( (!\t|count[6]~DUPLICATE_q & !\t|count [11]) ) ) )
+
+ .dataa(gnd),
+ .datab(!\t|count[6]~DUPLICATE_q ),
+ .datac(!\t|count [11]),
+ .datad(gnd),
+ .datae(!\t|count[4]~DUPLICATE_q ),
+ .dataf(!\t|count [3]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|Equal0~2_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|Equal0~2 .extended_lut = "off";
+defparam \t|Equal0~2 .lut_mask = 64'hC0C0000000000000;
+defparam \t|Equal0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N36
+cyclonev_lcell_comb \t|Add0~29 (
+// Equation(s):
+// \t|Add0~29_sumout = SUM(( !\t|count [12] ) + ( VCC ) + ( \t|Add0~62 ))
+// \t|Add0~30 = CARRY(( !\t|count [12] ) + ( VCC ) + ( \t|Add0~62 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\t|count [12]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~62 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~29_sumout ),
+ .cout(\t|Add0~30 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~29 .extended_lut = "off";
+defparam \t|Add0~29 .lut_mask = 64'h000000000000F0F0;
+defparam \t|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N48
+cyclonev_lcell_comb \t|count[12]~6 (
+// Equation(s):
+// \t|count[12]~6_combout = !\t|Add0~29_sumout
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|Add0~29_sumout ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|count[12]~6_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|count[12]~6 .extended_lut = "off";
+defparam \t|count[12]~6 .lut_mask = 64'hFF00FF00FF00FF00;
+defparam \t|count[12]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N50
+dffeas \t|count[12] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[12]~6_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [12]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[12] .is_wysiwyg = "true";
+defparam \t|count[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N39
+cyclonev_lcell_comb \t|Add0~37 (
+// Equation(s):
+// \t|Add0~37_sumout = SUM(( \t|count [13] ) + ( VCC ) + ( \t|Add0~30 ))
+// \t|Add0~38 = CARRY(( \t|count [13] ) + ( VCC ) + ( \t|Add0~30 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\t|count [13]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~30 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~37_sumout ),
+ .cout(\t|Add0~38 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~37 .extended_lut = "off";
+defparam \t|Add0~37 .lut_mask = 64'h0000000000000F0F;
+defparam \t|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N40
+dffeas \t|count[13] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~37_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [13]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[13] .is_wysiwyg = "true";
+defparam \t|count[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N42
+cyclonev_lcell_comb \t|Add0~41 (
+// Equation(s):
+// \t|Add0~41_sumout = SUM(( \t|count[14]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~38 ))
+// \t|Add0~42 = CARRY(( \t|count[14]~DUPLICATE_q ) + ( VCC ) + ( \t|Add0~38 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\t|count[14]~DUPLICATE_q ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~38 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~41_sumout ),
+ .cout(\t|Add0~42 ),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~41 .extended_lut = "off";
+defparam \t|Add0~41 .lut_mask = 64'h00000000000000FF;
+defparam \t|Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N43
+dffeas \t|count[14]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~41_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count[14]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[14]~DUPLICATE .is_wysiwyg = "true";
+defparam \t|count[14]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N45
+cyclonev_lcell_comb \t|Add0~45 (
+// Equation(s):
+// \t|Add0~45_sumout = SUM(( \t|count [15] ) + ( VCC ) + ( \t|Add0~42 ))
+
+ .dataa(gnd),
+ .datab(!\t|count [15]),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\t|Add0~42 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\t|Add0~45_sumout ),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|Add0~45 .extended_lut = "off";
+defparam \t|Add0~45 .lut_mask = 64'h0000000000003333;
+defparam \t|Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N47
+dffeas \t|count[15] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~45_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [15]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[15] .is_wysiwyg = "true";
+defparam \t|count[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N44
+dffeas \t|count[14] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|Add0~41_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(\t|Equal0~3_combout ),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [14]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[14] .is_wysiwyg = "true";
+defparam \t|count[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N51
+cyclonev_lcell_comb \t|Equal0~1 (
+// Equation(s):
+// \t|Equal0~1_combout = ( \t|count [12] & ( (!\t|count [10] & (!\t|count [15] & (!\t|count [14] & !\t|count [13]))) ) )
+
+ .dataa(!\t|count [10]),
+ .datab(!\t|count [15]),
+ .datac(!\t|count [14]),
+ .datad(!\t|count [13]),
+ .datae(gnd),
+ .dataf(!\t|count [12]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|Equal0~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|Equal0~1 .extended_lut = "off";
+defparam \t|Equal0~1 .lut_mask = 64'h0000000080008000;
+defparam \t|Equal0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X10_Y3_N59
+dffeas \t|count[2] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[2]~3_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [2]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[2] .is_wysiwyg = "true";
+defparam \t|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y3_N50
+dffeas \t|count[8] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[8]~5_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count [8]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[8] .is_wysiwyg = "true";
+defparam \t|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X10_Y3_N8
+dffeas \t|count[7]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\t|count[7]~4_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|count[7]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|count[7]~DUPLICATE .is_wysiwyg = "true";
+defparam \t|count[7]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X10_Y3_N45
+cyclonev_lcell_comb \t|Equal0~0 (
+// Equation(s):
+// \t|Equal0~0_combout = ( \t|count [0] & ( \t|count[7]~DUPLICATE_q & ( (\t|count [1] & (\t|count [2] & \t|count [8])) ) ) )
+
+ .dataa(gnd),
+ .datab(!\t|count [1]),
+ .datac(!\t|count [2]),
+ .datad(!\t|count [8]),
+ .datae(!\t|count [0]),
+ .dataf(!\t|count[7]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|Equal0~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|Equal0~0 .extended_lut = "off";
+defparam \t|Equal0~0 .lut_mask = 64'h0000000000000003;
+defparam \t|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X11_Y3_N54
+cyclonev_lcell_comb \t|Equal0~3 (
+// Equation(s):
+// \t|Equal0~3_combout = ( \t|Equal0~0_combout & ( (\t|Equal0~2_combout & (!\t|count [5] & (\t|Equal0~1_combout & \t|count [9]))) ) )
+
+ .dataa(!\t|Equal0~2_combout ),
+ .datab(!\t|count [5]),
+ .datac(!\t|Equal0~1_combout ),
+ .datad(!\t|count [9]),
+ .datae(gnd),
+ .dataf(!\t|Equal0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\t|Equal0~3_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \t|Equal0~3 .extended_lut = "off";
+defparam \t|Equal0~3 .lut_mask = 64'h0000000000040004;
+defparam \t|Equal0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X11_Y3_N53
+dffeas \t|CLK_OUT (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\t|Equal0~3_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\t|CLK_OUT~q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \t|CLK_OUT .is_wysiwyg = "true";
+defparam \t|CLK_OUT .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N9
+cyclonev_lcell_comb \s|sr_state.IDLE~0 (
+// Equation(s):
+// \s|sr_state.IDLE~0_combout = ( \s|WideNor0~combout & ( (!\s|sr_state.WAIT_CSB_HIGH~q & ((\s|sr_state.IDLE~q ) # (\t|CLK_OUT~q ))) ) ) # ( !\s|WideNor0~combout & ( ((\s|sr_state.IDLE~q ) # (\s|sr_state.WAIT_CSB_FALL~q )) # (\t|CLK_OUT~q ) ) )
+
+ .dataa(!\s|sr_state.WAIT_CSB_HIGH~q ),
+ .datab(!\t|CLK_OUT~q ),
+ .datac(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datad(!\s|sr_state.IDLE~q ),
+ .datae(gnd),
+ .dataf(!\s|WideNor0~combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|sr_state.IDLE~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|sr_state.IDLE~0 .extended_lut = "off";
+defparam \s|sr_state.IDLE~0 .lut_mask = 64'h3FFF3FFF22AA22AA;
+defparam \s|sr_state.IDLE~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N11
+dffeas \s|sr_state.IDLE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|sr_state.IDLE~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|sr_state.IDLE~q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|sr_state.IDLE .is_wysiwyg = "true";
+defparam \s|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N36
+cyclonev_lcell_comb \s|Selector2~0 (
+// Equation(s):
+// \s|Selector2~0_combout = ( \s|state [0] & ( \s|state [3] & ( \s|sr_state.IDLE~q ) ) ) # ( !\s|state [0] & ( \s|state [3] & ( \s|sr_state.IDLE~q ) ) ) # ( \s|state [0] & ( !\s|state [3] & ( (\s|sr_state.IDLE~q & ((!\s|state[4]~DUPLICATE_q ) #
+// ((\s|state [2]) # (\s|state [1])))) ) ) ) # ( !\s|state [0] & ( !\s|state [3] & ( (\s|sr_state.IDLE~q & (((\s|state [2]) # (\s|state [1])) # (\s|state[4]~DUPLICATE_q ))) ) ) )
+
+ .dataa(!\s|state[4]~DUPLICATE_q ),
+ .datab(!\s|state [1]),
+ .datac(!\s|state [2]),
+ .datad(!\s|sr_state.IDLE~q ),
+ .datae(!\s|state [0]),
+ .dataf(!\s|state [3]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|Selector2~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|Selector2~0 .extended_lut = "off";
+defparam \s|Selector2~0 .lut_mask = 64'h007F00BF00FF00FF;
+defparam \s|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X19_Y1_N38
+dffeas \s|sr_state.WAIT_CSB_HIGH (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|Selector2~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|sr_state.WAIT_CSB_HIGH~q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \s|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N6
+cyclonev_lcell_comb \s|sr_state.WAIT_CSB_FALL~0 (
+// Equation(s):
+// \s|sr_state.WAIT_CSB_FALL~0_combout = ( \s|WideNor0~combout & ( (!\s|sr_state.WAIT_CSB_HIGH~q & (((\t|CLK_OUT~q & !\s|sr_state.IDLE~q )) # (\s|sr_state.WAIT_CSB_FALL~q ))) ) ) # ( !\s|WideNor0~combout & ( (\t|CLK_OUT~q & (!\s|sr_state.IDLE~q &
+// !\s|sr_state.WAIT_CSB_FALL~q )) ) )
+
+ .dataa(!\s|sr_state.WAIT_CSB_HIGH~q ),
+ .datab(!\t|CLK_OUT~q ),
+ .datac(!\s|sr_state.IDLE~q ),
+ .datad(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datae(gnd),
+ .dataf(!\s|WideNor0~combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|sr_state.WAIT_CSB_FALL~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|sr_state.WAIT_CSB_FALL~0 .extended_lut = "off";
+defparam \s|sr_state.WAIT_CSB_FALL~0 .lut_mask = 64'h3000300020AA20AA;
+defparam \s|sr_state.WAIT_CSB_FALL~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N8
+dffeas \s|sr_state.WAIT_CSB_FALL (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\s|sr_state.WAIT_CSB_FALL~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|sr_state.WAIT_CSB_FALL~q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \s|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N57
+cyclonev_lcell_comb \s|Selector3~0 (
+// Equation(s):
+// \s|Selector3~0_combout = ( \s|state[2]~DUPLICATE_q & ( \s|sr_state.WAIT_CSB_FALL~q & ( !\s|state [0] ) ) ) # ( !\s|state[2]~DUPLICATE_q & ( \s|sr_state.WAIT_CSB_FALL~q & ( !\s|state [0] ) ) ) # ( \s|state[2]~DUPLICATE_q & (
+// !\s|sr_state.WAIT_CSB_FALL~q & ( !\s|state [0] ) ) ) # ( !\s|state[2]~DUPLICATE_q & ( !\s|sr_state.WAIT_CSB_FALL~q & ( (!\s|state [0] & (((\s|state[4]~DUPLICATE_q ) # (\s|state [1])) # (\s|state [3]))) ) ) )
+
+ .dataa(!\s|state [0]),
+ .datab(!\s|state [3]),
+ .datac(!\s|state [1]),
+ .datad(!\s|state[4]~DUPLICATE_q ),
+ .datae(!\s|state[2]~DUPLICATE_q ),
+ .dataf(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|Selector3~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|Selector3~0 .extended_lut = "off";
+defparam \s|Selector3~0 .lut_mask = 64'h2AAAAAAAAAAAAAAA;
+defparam \s|Selector3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N41
+dffeas \s|state[0] (
+ .clk(\s|clk_1MHz~q ),
+ .d(gnd),
+ .asdata(\s|Selector3~0_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|state [0]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|state[0] .is_wysiwyg = "true";
+defparam \s|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N19
+dffeas \s|state[4] (
+ .clk(\s|clk_1MHz~q ),
+ .d(gnd),
+ .asdata(\s|state~0_combout ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|state [4]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|state[4] .is_wysiwyg = "true";
+defparam \s|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N27
+cyclonev_lcell_comb \s|WideNor0 (
+// Equation(s):
+// \s|WideNor0~combout = ( !\s|state [2] & ( (!\s|state [1] & (!\s|state [3] & (!\s|state [0] $ (\s|state [4])))) ) )
+
+ .dataa(!\s|state [0]),
+ .datab(!\s|state [1]),
+ .datac(!\s|state [4]),
+ .datad(!\s|state [3]),
+ .datae(gnd),
+ .dataf(!\s|state [2]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|WideNor0~combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|WideNor0 .extended_lut = "off";
+defparam \s|WideNor0 .lut_mask = 64'h8400840000000000;
+defparam \s|WideNor0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N58
+cyclonev_io_ibuf \SW[9]~input (
+ .i(SW[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[9]~input_o ));
+// synopsys translate_off
+defparam \SW[9]~input .bus_hold = "false";
+defparam \SW[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N42
+cyclonev_lcell_comb \s|shift_reg[11]~feeder (
+// Equation(s):
+// \s|shift_reg[11]~feeder_combout = \SW[9]~input_o
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\SW[9]~input_o ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[11]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[11]~feeder .extended_lut = "off";
+defparam \s|shift_reg[11]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \s|shift_reg[11]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N18
+cyclonev_io_ibuf \SW[8]~input (
+ .i(SW[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[8]~input_o ));
+// synopsys translate_off
+defparam \SW[8]~input .bus_hold = "false";
+defparam \SW[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N36
+cyclonev_lcell_comb \s|shift_reg[10]~feeder (
+// Equation(s):
+// \s|shift_reg[10]~feeder_combout = \SW[8]~input_o
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\SW[8]~input_o ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[10]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[10]~feeder .extended_lut = "off";
+defparam \s|shift_reg[10]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \s|shift_reg[10]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N1
+cyclonev_io_ibuf \SW[7]~input (
+ .i(SW[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[7]~input_o ));
+// synopsys translate_off
+defparam \SW[7]~input .bus_hold = "false";
+defparam \SW[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N3
+cyclonev_lcell_comb \s|shift_reg[9]~feeder (
+// Equation(s):
+// \s|shift_reg[9]~feeder_combout = \SW[7]~input_o
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\SW[7]~input_o ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[9]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[9]~feeder .extended_lut = "off";
+defparam \s|shift_reg[9]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \s|shift_reg[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N35
+cyclonev_io_ibuf \SW[6]~input (
+ .i(SW[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[6]~input_o ));
+// synopsys translate_off
+defparam \SW[6]~input .bus_hold = "false";
+defparam \SW[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N24
+cyclonev_lcell_comb \s|shift_reg[8]~feeder (
+// Equation(s):
+// \s|shift_reg[8]~feeder_combout = \SW[6]~input_o
+
+ .dataa(gnd),
+ .datab(!\SW[6]~input_o ),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[8]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[8]~feeder .extended_lut = "off";
+defparam \s|shift_reg[8]~feeder .lut_mask = 64'h3333333333333333;
+defparam \s|shift_reg[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N18
+cyclonev_io_ibuf \SW[5]~input (
+ .i(SW[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[5]~input_o ));
+// synopsys translate_off
+defparam \SW[5]~input .bus_hold = "false";
+defparam \SW[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N27
+cyclonev_lcell_comb \s|shift_reg[7]~feeder (
+// Equation(s):
+// \s|shift_reg[7]~feeder_combout = \SW[5]~input_o
+
+ .dataa(!\SW[5]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[7]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[7]~feeder .extended_lut = "off";
+defparam \s|shift_reg[7]~feeder .lut_mask = 64'h5555555555555555;
+defparam \s|shift_reg[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N41
+cyclonev_io_ibuf \SW[4]~input (
+ .i(SW[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[4]~input_o ));
+// synopsys translate_off
+defparam \SW[4]~input .bus_hold = "false";
+defparam \SW[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N12
+cyclonev_lcell_comb \s|shift_reg[6]~feeder (
+// Equation(s):
+// \s|shift_reg[6]~feeder_combout = \SW[4]~input_o
+
+ .dataa(gnd),
+ .datab(!\SW[4]~input_o ),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[6]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[6]~feeder .extended_lut = "off";
+defparam \s|shift_reg[6]~feeder .lut_mask = 64'h3333333333333333;
+defparam \s|shift_reg[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N52
+cyclonev_io_ibuf \SW[3]~input (
+ .i(SW[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[3]~input_o ));
+// synopsys translate_off
+defparam \SW[3]~input .bus_hold = "false";
+defparam \SW[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N15
+cyclonev_lcell_comb \s|shift_reg[5]~feeder (
+// Equation(s):
+// \s|shift_reg[5]~feeder_combout = \SW[3]~input_o
+
+ .dataa(!\SW[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[5]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[5]~feeder .extended_lut = "off";
+defparam \s|shift_reg[5]~feeder .lut_mask = 64'h5555555555555555;
+defparam \s|shift_reg[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X8_Y0_N35
+cyclonev_io_ibuf \SW[2]~input (
+ .i(SW[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[2]~input_o ));
+// synopsys translate_off
+defparam \SW[2]~input .bus_hold = "false";
+defparam \SW[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N48
+cyclonev_lcell_comb \s|shift_reg[4]~feeder (
+// Equation(s):
+// \s|shift_reg[4]~feeder_combout = \SW[2]~input_o
+
+ .dataa(gnd),
+ .datab(!\SW[2]~input_o ),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[4]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[4]~feeder .extended_lut = "off";
+defparam \s|shift_reg[4]~feeder .lut_mask = 64'h3333333333333333;
+defparam \s|shift_reg[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N1
+cyclonev_io_ibuf \SW[1]~input (
+ .i(SW[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[1]~input_o ));
+// synopsys translate_off
+defparam \SW[1]~input .bus_hold = "false";
+defparam \SW[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N51
+cyclonev_lcell_comb \s|shift_reg[3]~feeder (
+// Equation(s):
+// \s|shift_reg[3]~feeder_combout = \SW[1]~input_o
+
+ .dataa(!\SW[1]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg[3]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg[3]~feeder .extended_lut = "off";
+defparam \s|shift_reg[3]~feeder .lut_mask = 64'h5555555555555555;
+defparam \s|shift_reg[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X12_Y0_N18
+cyclonev_io_ibuf \SW[0]~input (
+ .i(SW[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\SW[0]~input_o ));
+// synopsys translate_off
+defparam \SW[0]~input .bus_hold = "false";
+defparam \SW[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N33
+cyclonev_lcell_comb \s|shift_reg~4 (
+// Equation(s):
+// \s|shift_reg~4_combout = ( \s|WideNor0~combout & ( (\SW[0]~input_o & \s|sr_state.WAIT_CSB_FALL~q ) ) )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\SW[0]~input_o ),
+ .datad(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datae(gnd),
+ .dataf(!\s|WideNor0~combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg~4_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg~4 .extended_lut = "off";
+defparam \s|shift_reg~4 .lut_mask = 64'h00000000000F000F;
+defparam \s|shift_reg~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N34
+dffeas \s|shift_reg[2] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg~4_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [2]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[2] .is_wysiwyg = "true";
+defparam \s|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X18_Y1_N21
+cyclonev_lcell_comb \s|always5~0 (
+// Equation(s):
+// \s|always5~0_combout = ( \s|state[2]~DUPLICATE_q & ( \s|sr_state.WAIT_CSB_FALL~q ) ) # ( !\s|state[2]~DUPLICATE_q & ( \s|sr_state.WAIT_CSB_FALL~q & ( ((!\s|state [0] $ (!\s|state[4]~DUPLICATE_q )) # (\s|state [1])) # (\s|state [3]) ) ) ) # (
+// \s|state[2]~DUPLICATE_q & ( !\s|sr_state.WAIT_CSB_FALL~q ) ) # ( !\s|state[2]~DUPLICATE_q & ( !\s|sr_state.WAIT_CSB_FALL~q ) )
+
+ .dataa(!\s|state [3]),
+ .datab(!\s|state [1]),
+ .datac(!\s|state [0]),
+ .datad(!\s|state[4]~DUPLICATE_q ),
+ .datae(!\s|state[2]~DUPLICATE_q ),
+ .dataf(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|always5~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|always5~0 .extended_lut = "off";
+defparam \s|always5~0 .lut_mask = 64'hFFFFFFFF7FF7FFFF;
+defparam \s|always5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N52
+dffeas \s|shift_reg[3] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[3]~feeder_combout ),
+ .asdata(\s|shift_reg [2]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [3]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[3] .is_wysiwyg = "true";
+defparam \s|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N49
+dffeas \s|shift_reg[4] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[4]~feeder_combout ),
+ .asdata(\s|shift_reg [3]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [4]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[4] .is_wysiwyg = "true";
+defparam \s|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N16
+dffeas \s|shift_reg[5] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[5]~feeder_combout ),
+ .asdata(\s|shift_reg [4]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [5]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[5] .is_wysiwyg = "true";
+defparam \s|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N13
+dffeas \s|shift_reg[6] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[6]~feeder_combout ),
+ .asdata(\s|shift_reg [5]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [6]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[6] .is_wysiwyg = "true";
+defparam \s|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N29
+dffeas \s|shift_reg[7] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[7]~feeder_combout ),
+ .asdata(\s|shift_reg [6]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [7]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[7] .is_wysiwyg = "true";
+defparam \s|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N25
+dffeas \s|shift_reg[8] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[8]~feeder_combout ),
+ .asdata(\s|shift_reg [7]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [8]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[8] .is_wysiwyg = "true";
+defparam \s|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N4
+dffeas \s|shift_reg[9] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[9]~feeder_combout ),
+ .asdata(\s|shift_reg [8]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [9]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[9] .is_wysiwyg = "true";
+defparam \s|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N37
+dffeas \s|shift_reg[10] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[10]~feeder_combout ),
+ .asdata(\s|shift_reg [9]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [10]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[10] .is_wysiwyg = "true";
+defparam \s|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X18_Y1_N43
+dffeas \s|shift_reg[11] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg[11]~feeder_combout ),
+ .asdata(\s|shift_reg [10]),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(\s|always5~0_combout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [11]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[11] .is_wysiwyg = "true";
+defparam \s|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N15
+cyclonev_lcell_comb \s|shift_reg~3 (
+// Equation(s):
+// \s|shift_reg~3_combout = ( \s|WideNor0~combout & ( \s|shift_reg [11] ) ) # ( !\s|WideNor0~combout & ( \s|shift_reg [11] ) ) # ( \s|WideNor0~combout & ( !\s|shift_reg [11] & ( \s|sr_state.WAIT_CSB_FALL~q ) ) )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datad(gnd),
+ .datae(!\s|WideNor0~combout ),
+ .dataf(!\s|shift_reg [11]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg~3_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg~3 .extended_lut = "off";
+defparam \s|shift_reg~3 .lut_mask = 64'h00000F0FFFFFFFFF;
+defparam \s|shift_reg~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X19_Y1_N17
+dffeas \s|shift_reg[12] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg~3_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [12]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[12] .is_wysiwyg = "true";
+defparam \s|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N18
+cyclonev_lcell_comb \s|shift_reg~2 (
+// Equation(s):
+// \s|shift_reg~2_combout = ( \s|WideNor0~combout & ( (\s|sr_state.WAIT_CSB_FALL~q ) # (\s|shift_reg [12]) ) ) # ( !\s|WideNor0~combout & ( \s|shift_reg [12] ) )
+
+ .dataa(gnd),
+ .datab(!\s|shift_reg [12]),
+ .datac(gnd),
+ .datad(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datae(gnd),
+ .dataf(!\s|WideNor0~combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg~2_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg~2 .extended_lut = "off";
+defparam \s|shift_reg~2 .lut_mask = 64'h3333333333FF33FF;
+defparam \s|shift_reg~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X19_Y1_N19
+dffeas \s|shift_reg[13] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg~2_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [13]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[13] .is_wysiwyg = "true";
+defparam \s|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N24
+cyclonev_lcell_comb \s|shift_reg~1 (
+// Equation(s):
+// \s|shift_reg~1_combout = ( \s|WideNor0~combout & ( (\s|shift_reg [13]) # (\s|sr_state.WAIT_CSB_FALL~q ) ) ) # ( !\s|WideNor0~combout & ( \s|shift_reg [13] ) )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .datad(!\s|shift_reg [13]),
+ .datae(gnd),
+ .dataf(!\s|WideNor0~combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg~1 .extended_lut = "off";
+defparam \s|shift_reg~1 .lut_mask = 64'h00FF00FF0FFF0FFF;
+defparam \s|shift_reg~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X19_Y1_N26
+dffeas \s|shift_reg[14] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg~1_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [14]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[14] .is_wysiwyg = "true";
+defparam \s|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N42
+cyclonev_lcell_comb \s|shift_reg~0 (
+// Equation(s):
+// \s|shift_reg~0_combout = ( !\s|sr_state.WAIT_CSB_FALL~q & ( \s|WideNor0~combout & ( \s|shift_reg [14] ) ) ) # ( \s|sr_state.WAIT_CSB_FALL~q & ( !\s|WideNor0~combout & ( \s|shift_reg [14] ) ) ) # ( !\s|sr_state.WAIT_CSB_FALL~q & (
+// !\s|WideNor0~combout & ( \s|shift_reg [14] ) ) )
+
+ .dataa(gnd),
+ .datab(!\s|shift_reg [14]),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(!\s|sr_state.WAIT_CSB_FALL~q ),
+ .dataf(!\s|WideNor0~combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|shift_reg~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|shift_reg~0 .extended_lut = "off";
+defparam \s|shift_reg~0 .lut_mask = 64'h3333333333330000;
+defparam \s|shift_reg~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X19_Y1_N43
+dffeas \s|shift_reg[15] (
+ .clk(\s|clk_1MHz~q ),
+ .d(\s|shift_reg~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\s|shift_reg [15]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \s|shift_reg[15] .is_wysiwyg = "true";
+defparam \s|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N48
+cyclonev_lcell_comb \s|Equal2~0 (
+// Equation(s):
+// \s|Equal2~0_combout = ( !\s|state [2] & ( \s|state[4]~DUPLICATE_q & ( (!\s|state [3] & (\s|state [0] & !\s|state [1])) ) ) )
+
+ .dataa(gnd),
+ .datab(!\s|state [3]),
+ .datac(!\s|state [0]),
+ .datad(!\s|state [1]),
+ .datae(!\s|state [2]),
+ .dataf(!\s|state[4]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|Equal2~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|Equal2~0 .extended_lut = "off";
+defparam \s|Equal2~0 .lut_mask = 64'h000000000C000000;
+defparam \s|Equal2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X19_Y1_N54
+cyclonev_lcell_comb \s|dac_sck (
+// Equation(s):
+// \s|dac_sck~combout = ( \s|clk_1MHz~q & ( \s|state[4]~DUPLICATE_q ) ) # ( !\s|clk_1MHz~q & ( \s|state[4]~DUPLICATE_q & ( (!\s|state [1] & (!\s|state [2] & (!\s|state [3] & \s|state [0]))) ) ) ) # ( \s|clk_1MHz~q & ( !\s|state[4]~DUPLICATE_q ) ) # (
+// !\s|clk_1MHz~q & ( !\s|state[4]~DUPLICATE_q & ( (!\s|state [1] & (!\s|state [2] & (!\s|state [3] & !\s|state [0]))) ) ) )
+
+ .dataa(!\s|state [1]),
+ .datab(!\s|state [2]),
+ .datac(!\s|state [3]),
+ .datad(!\s|state [0]),
+ .datae(!\s|clk_1MHz~q ),
+ .dataf(!\s|state[4]~DUPLICATE_q ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\s|dac_sck~combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \s|dac_sck .extended_lut = "off";
+defparam \s|dac_sck .lut_mask = 64'h8000FFFF0080FFFF;
+defparam \s|dac_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N54
+cyclonev_lcell_comb \p|count[0]~0 (
+// Equation(s):
+// \p|count[0]~0_combout = ( !\p|count [0] )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(!\p|count [0]),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|count[0]~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|count[0]~0 .extended_lut = "off";
+defparam \p|count[0]~0 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \p|count[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N56
+dffeas \p|count[0] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|count[0]~0_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [0]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[0] .is_wysiwyg = "true";
+defparam \p|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N0
+cyclonev_lcell_comb \p|Add0~9 (
+// Equation(s):
+// \p|Add0~9_sumout = SUM(( \p|count [1] ) + ( \p|count [0] ) + ( !VCC ))
+// \p|Add0~10 = CARRY(( \p|count [1] ) + ( \p|count [0] ) + ( !VCC ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(!\p|count [0]),
+ .datad(!\p|count [1]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~9_sumout ),
+ .cout(\p|Add0~10 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~9 .extended_lut = "off";
+defparam \p|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
+defparam \p|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N2
+dffeas \p|count[1] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~9_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [1]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[1] .is_wysiwyg = "true";
+defparam \p|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N3
+cyclonev_lcell_comb \p|Add0~5 (
+// Equation(s):
+// \p|Add0~5_sumout = SUM(( \p|count [2] ) + ( GND ) + ( \p|Add0~10 ))
+// \p|Add0~6 = CARRY(( \p|count [2] ) + ( GND ) + ( \p|Add0~10 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [2]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~10 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~5_sumout ),
+ .cout(\p|Add0~6 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~5 .extended_lut = "off";
+defparam \p|Add0~5 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N5
+dffeas \p|count[2] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~5_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [2]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[2] .is_wysiwyg = "true";
+defparam \p|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N6
+cyclonev_lcell_comb \p|Add0~1 (
+// Equation(s):
+// \p|Add0~1_sumout = SUM(( \p|count [3] ) + ( GND ) + ( \p|Add0~6 ))
+// \p|Add0~2 = CARRY(( \p|count [3] ) + ( GND ) + ( \p|Add0~6 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [3]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~6 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~1_sumout ),
+ .cout(\p|Add0~2 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~1 .extended_lut = "off";
+defparam \p|Add0~1 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N8
+dffeas \p|count[3] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~1_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [3]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[3] .is_wysiwyg = "true";
+defparam \p|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N9
+cyclonev_lcell_comb \p|Add0~25 (
+// Equation(s):
+// \p|Add0~25_sumout = SUM(( \p|count [4] ) + ( GND ) + ( \p|Add0~2 ))
+// \p|Add0~26 = CARRY(( \p|count [4] ) + ( GND ) + ( \p|Add0~2 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [4]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~2 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~25_sumout ),
+ .cout(\p|Add0~26 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~25 .extended_lut = "off";
+defparam \p|Add0~25 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N10
+dffeas \p|count[4] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~25_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [4]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[4] .is_wysiwyg = "true";
+defparam \p|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N12
+cyclonev_lcell_comb \p|Add0~13 (
+// Equation(s):
+// \p|Add0~13_sumout = SUM(( \p|count [5] ) + ( GND ) + ( \p|Add0~26 ))
+// \p|Add0~14 = CARRY(( \p|count [5] ) + ( GND ) + ( \p|Add0~26 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [5]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~26 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~13_sumout ),
+ .cout(\p|Add0~14 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~13 .extended_lut = "off";
+defparam \p|Add0~13 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N13
+dffeas \p|count[5] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~13_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [5]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[5] .is_wysiwyg = "true";
+defparam \p|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N56
+dffeas \p|d[5] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[5]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [5]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[5] .is_wysiwyg = "true";
+defparam \p|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N22
+dffeas \p|d[4] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[4]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [4]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[4] .is_wysiwyg = "true";
+defparam \p|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N15
+cyclonev_lcell_comb \p|Add0~21 (
+// Equation(s):
+// \p|Add0~21_sumout = SUM(( \p|count [6] ) + ( GND ) + ( \p|Add0~14 ))
+// \p|Add0~22 = CARRY(( \p|count [6] ) + ( GND ) + ( \p|Add0~14 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [6]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~14 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~21_sumout ),
+ .cout(\p|Add0~22 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~21 .extended_lut = "off";
+defparam \p|Add0~21 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N17
+dffeas \p|count[6] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~21_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [6]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[6] .is_wysiwyg = "true";
+defparam \p|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N18
+cyclonev_lcell_comb \p|Add0~17 (
+// Equation(s):
+// \p|Add0~17_sumout = SUM(( \p|count [7] ) + ( GND ) + ( \p|Add0~22 ))
+// \p|Add0~18 = CARRY(( \p|count [7] ) + ( GND ) + ( \p|Add0~22 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [7]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~22 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~17_sumout ),
+ .cout(\p|Add0~18 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~17 .extended_lut = "off";
+defparam \p|Add0~17 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N19
+dffeas \p|count[7] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~17_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [7]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[7] .is_wysiwyg = "true";
+defparam \p|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N59
+dffeas \p|d[6] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[6]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [6]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[6] .is_wysiwyg = "true";
+defparam \p|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N25
+dffeas \p|d[7] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[7]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [7]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[7] .is_wysiwyg = "true";
+defparam \p|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N39
+cyclonev_lcell_comb \p|LessThan0~2 (
+// Equation(s):
+// \p|LessThan0~2_combout = ( \p|d [7] & ( (\p|count [7] & (!\p|count [6] $ (\p|d [6]))) ) ) # ( !\p|d [7] & ( (!\p|count [7] & (!\p|count [6] $ (\p|d [6]))) ) )
+
+ .dataa(gnd),
+ .datab(!\p|count [7]),
+ .datac(!\p|count [6]),
+ .datad(!\p|d [6]),
+ .datae(gnd),
+ .dataf(!\p|d [7]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~2_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~2 .extended_lut = "off";
+defparam \p|LessThan0~2 .lut_mask = 64'hC00CC00C30033003;
+defparam \p|LessThan0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N21
+cyclonev_lcell_comb \p|LessThan0~3 (
+// Equation(s):
+// \p|LessThan0~3_combout = ( \p|d [4] & ( \p|LessThan0~2_combout & ( (\p|count [4] & (!\p|count [5] $ (\p|d [5]))) ) ) ) # ( !\p|d [4] & ( \p|LessThan0~2_combout & ( (!\p|count [4] & (!\p|count [5] $ (\p|d [5]))) ) ) )
+
+ .dataa(!\p|count [5]),
+ .datab(gnd),
+ .datac(!\p|count [4]),
+ .datad(!\p|d [5]),
+ .datae(!\p|d [4]),
+ .dataf(!\p|LessThan0~2_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~3_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~3 .extended_lut = "off";
+defparam \p|LessThan0~3 .lut_mask = 64'h00000000A0500A05;
+defparam \p|LessThan0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N37
+dffeas \p|d[8] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[8]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [8]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[8] .is_wysiwyg = "true";
+defparam \p|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N23
+dffeas \p|count[8] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~33_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [8]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[8] .is_wysiwyg = "true";
+defparam \p|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N21
+cyclonev_lcell_comb \p|Add0~33 (
+// Equation(s):
+// \p|Add0~33_sumout = SUM(( \p|count [8] ) + ( GND ) + ( \p|Add0~18 ))
+// \p|Add0~34 = CARRY(( \p|count [8] ) + ( GND ) + ( \p|Add0~18 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [8]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~18 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~33_sumout ),
+ .cout(\p|Add0~34 ),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~33 .extended_lut = "off";
+defparam \p|Add0~33 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N22
+dffeas \p|count[8]~DUPLICATE (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~33_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count[8]~DUPLICATE_q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[8]~DUPLICATE .is_wysiwyg = "true";
+defparam \p|count[8]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N29
+dffeas \p|d[9] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[9]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [9]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[9] .is_wysiwyg = "true";
+defparam \p|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N24
+cyclonev_lcell_comb \p|Add0~29 (
+// Equation(s):
+// \p|Add0~29_sumout = SUM(( \p|count [9] ) + ( GND ) + ( \p|Add0~34 ))
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\p|count [9]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(\p|Add0~34 ),
+ .sharein(gnd),
+ .combout(),
+ .sumout(\p|Add0~29_sumout ),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|Add0~29 .extended_lut = "off";
+defparam \p|Add0~29 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N25
+dffeas \p|count[9] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|Add0~29_sumout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|count [9]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|count[9] .is_wysiwyg = "true";
+defparam \p|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N27
+cyclonev_lcell_comb \p|LessThan0~7 (
+// Equation(s):
+// \p|LessThan0~7_combout = ( \p|count [9] & ( (!\p|d [9]) # ((!\p|d [8] & \p|count[8]~DUPLICATE_q )) ) ) # ( !\p|count [9] & ( (!\p|d [8] & (\p|count[8]~DUPLICATE_q & !\p|d [9])) ) )
+
+ .dataa(!\p|d [8]),
+ .datab(gnd),
+ .datac(!\p|count[8]~DUPLICATE_q ),
+ .datad(!\p|d [9]),
+ .datae(gnd),
+ .dataf(!\p|count [9]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~7_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~7 .extended_lut = "off";
+defparam \p|LessThan0~7 .lut_mask = 64'h0A000A00FF0AFF0A;
+defparam \p|LessThan0~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N32
+dffeas \p|d[3] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[3]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [3]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[3] .is_wysiwyg = "true";
+defparam \p|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N53
+dffeas \p|d[2] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[2]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [2]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[2] .is_wysiwyg = "true";
+defparam \p|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N45
+cyclonev_lcell_comb \p|d[1]~feeder (
+// Equation(s):
+// \p|d[1]~feeder_combout = ( \SW[1]~input_o )
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\SW[1]~input_o ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|d[1]~feeder_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|d[1]~feeder .extended_lut = "off";
+defparam \p|d[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \p|d[1]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N47
+dffeas \p|d[1] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|d[1]~feeder_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [1]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[1] .is_wysiwyg = "true";
+defparam \p|d[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X16_Y1_N37
+dffeas \p|d[0] (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(gnd),
+ .asdata(\SW[0]~input_o ),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(vcc),
+ .ena(\t|CLK_OUT~q ),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|d [0]),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|d[0] .is_wysiwyg = "true";
+defparam \p|d[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N33
+cyclonev_lcell_comb \p|LessThan0~0 (
+// Equation(s):
+// \p|LessThan0~0_combout = ( \p|count [1] & ( (!\p|d [1]) # ((\p|count [0] & !\p|d [0])) ) ) # ( !\p|count [1] & ( (\p|count [0] & (!\p|d [1] & !\p|d [0])) ) )
+
+ .dataa(!\p|count [0]),
+ .datab(!\p|d [1]),
+ .datac(!\p|d [0]),
+ .datad(gnd),
+ .datae(!\p|count [1]),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~0 .extended_lut = "off";
+defparam \p|LessThan0~0 .lut_mask = 64'h4040DCDC4040DCDC;
+defparam \p|LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X16_Y1_N51
+cyclonev_lcell_comb \p|LessThan0~1 (
+// Equation(s):
+// \p|LessThan0~1_combout = ( \p|d [2] & ( \p|LessThan0~0_combout & ( (!\p|count [2] & (\p|count [3] & !\p|d [3])) # (\p|count [2] & ((!\p|d [3]) # (\p|count [3]))) ) ) ) # ( !\p|d [2] & ( \p|LessThan0~0_combout & ( (!\p|d [3]) # (\p|count [3]) ) ) ) # (
+// \p|d [2] & ( !\p|LessThan0~0_combout & ( (\p|count [3] & !\p|d [3]) ) ) ) # ( !\p|d [2] & ( !\p|LessThan0~0_combout & ( (!\p|count [2] & (\p|count [3] & !\p|d [3])) # (\p|count [2] & ((!\p|d [3]) # (\p|count [3]))) ) ) )
+
+ .dataa(!\p|count [2]),
+ .datab(!\p|count [3]),
+ .datac(!\p|d [3]),
+ .datad(gnd),
+ .datae(!\p|d [2]),
+ .dataf(!\p|LessThan0~0_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~1 .extended_lut = "off";
+defparam \p|LessThan0~1 .lut_mask = 64'h71713030F3F37171;
+defparam \p|LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N36
+cyclonev_lcell_comb \p|LessThan0~6 (
+// Equation(s):
+// \p|LessThan0~6_combout = ( \p|count [9] & ( (\p|d [9] & (!\p|count [8] $ (\p|d [8]))) ) ) # ( !\p|count [9] & ( (!\p|d [9] & (!\p|count [8] $ (\p|d [8]))) ) )
+
+ .dataa(!\p|count [8]),
+ .datab(gnd),
+ .datac(!\p|d [9]),
+ .datad(!\p|d [8]),
+ .datae(gnd),
+ .dataf(!\p|count [9]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~6_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~6 .extended_lut = "off";
+defparam \p|LessThan0~6 .lut_mask = 64'hA050A0500A050A05;
+defparam \p|LessThan0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N24
+cyclonev_lcell_comb \p|LessThan0~4 (
+// Equation(s):
+// \p|LessThan0~4_combout = ( \p|count [6] & ( (!\p|d [6] & ((!\p|d [7]) # (\p|count [7]))) # (\p|d [6] & (\p|count [7] & !\p|d [7])) ) ) # ( !\p|count [6] & ( (\p|count [7] & !\p|d [7]) ) )
+
+ .dataa(gnd),
+ .datab(!\p|d [6]),
+ .datac(!\p|count [7]),
+ .datad(!\p|d [7]),
+ .datae(gnd),
+ .dataf(!\p|count [6]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~4_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~4 .extended_lut = "off";
+defparam \p|LessThan0~4 .lut_mask = 64'h0F000F00CF0CCF0C;
+defparam \p|LessThan0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N30
+cyclonev_lcell_comb \p|LessThan0~5 (
+// Equation(s):
+// \p|LessThan0~5_combout = ( \p|d [5] & ( \p|count [4] & ( (!\p|LessThan0~4_combout & ((!\p|LessThan0~2_combout ) # ((!\p|count [5]) # (\p|d [4])))) ) ) ) # ( !\p|d [5] & ( \p|count [4] & ( (!\p|LessThan0~4_combout & ((!\p|LessThan0~2_combout ) #
+// ((!\p|count [5] & \p|d [4])))) ) ) ) # ( \p|d [5] & ( !\p|count [4] & ( !\p|LessThan0~4_combout ) ) ) # ( !\p|d [5] & ( !\p|count [4] & ( (!\p|LessThan0~4_combout & ((!\p|LessThan0~2_combout ) # (!\p|count [5]))) ) ) )
+
+ .dataa(!\p|LessThan0~4_combout ),
+ .datab(!\p|LessThan0~2_combout ),
+ .datac(!\p|count [5]),
+ .datad(!\p|d [4]),
+ .datae(!\p|d [5]),
+ .dataf(!\p|count [4]),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~5_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~5 .extended_lut = "off";
+defparam \p|LessThan0~5 .lut_mask = 64'hA8A8AAAA88A8A8AA;
+defparam \p|LessThan0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X17_Y1_N15
+cyclonev_lcell_comb \p|LessThan0~8 (
+// Equation(s):
+// \p|LessThan0~8_combout = ( \p|LessThan0~6_combout & ( \p|LessThan0~5_combout & ( (!\p|LessThan0~7_combout & ((!\p|LessThan0~3_combout ) # (!\p|LessThan0~1_combout ))) ) ) ) # ( !\p|LessThan0~6_combout & ( \p|LessThan0~5_combout & (
+// !\p|LessThan0~7_combout ) ) ) # ( !\p|LessThan0~6_combout & ( !\p|LessThan0~5_combout & ( !\p|LessThan0~7_combout ) ) )
+
+ .dataa(!\p|LessThan0~3_combout ),
+ .datab(gnd),
+ .datac(!\p|LessThan0~7_combout ),
+ .datad(!\p|LessThan0~1_combout ),
+ .datae(!\p|LessThan0~6_combout ),
+ .dataf(!\p|LessThan0~5_combout ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\p|LessThan0~8_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \p|LessThan0~8 .extended_lut = "off";
+defparam \p|LessThan0~8 .lut_mask = 64'hF0F00000F0F0F0A0;
+defparam \p|LessThan0~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X17_Y1_N16
+dffeas \p|pwm_out (
+ .clk(\CLOCK_50~inputCLKENA0_outclk ),
+ .d(\p|LessThan0~8_combout ),
+ .asdata(vcc),
+ .clrn(vcc),
+ .aload(gnd),
+ .sclr(gnd),
+ .sload(gnd),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .q(\p|pwm_out~q ),
+ .prn(vcc));
+// synopsys translate_off
+defparam \p|pwm_out .is_wysiwyg = "true";
+defparam \p|pwm_out .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X39_Y27_N3
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\~QUARTUS_CREATED_GND~I_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
diff --git a/part_3/ex11/simulation/modelsim/ex10_modelsim.xrf b/part_3/ex11/simulation/modelsim/ex10_modelsim.xrf new file mode 100755 index 0000000..afcc3b9 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/ex10_modelsim.xrf @@ -0,0 +1,182 @@ +vendor_name = ModelSim
+source_file = 1, C:/New folder/ex11/ex11.v
+source_file = 1, C:/New folder/ex11/verilog_files/tick_5000.v
+source_file = 1, C:/New folder/ex11/verilog_files/spi2dac.v
+source_file = 1, C:/New folder/ex11/verilog_files/pwm.v
+source_file = 1, C:/New folder/ex11/db/ex10.cbx.xml
+design_name = ex11
+instance = comp, \DAC_CS~output , DAC_CS~output, ex11, 1
+instance = comp, \DAC_SDI~output , DAC_SDI~output, ex11, 1
+instance = comp, \DAC_LD~output , DAC_LD~output, ex11, 1
+instance = comp, \DAC_SCK~output , DAC_SCK~output, ex11, 1
+instance = comp, \PWM_OUT~output , PWM_OUT~output, ex11, 1
+instance = comp, \CLOCK_50~input , CLOCK_50~input, ex11, 1
+instance = comp, \CLOCK_50~inputCLKENA0 , CLOCK_50~inputCLKENA0, ex11, 1
+instance = comp, \s|Add0~0 , s|Add0~0, ex11, 1
+instance = comp, \s|ctr[4] , s|ctr[4], ex11, 1
+instance = comp, \s|ctr[0] , s|ctr[0], ex11, 1
+instance = comp, \s|ctr~1 , s|ctr~1, ex11, 1
+instance = comp, \s|ctr[0]~DUPLICATE , s|ctr[0]~DUPLICATE, ex11, 1
+instance = comp, \s|ctr[3] , s|ctr[3], ex11, 1
+instance = comp, \s|ctr~2 , s|ctr~2, ex11, 1
+instance = comp, \s|ctr[1] , s|ctr[1], ex11, 1
+instance = comp, \s|Add0~1 , s|Add0~1, ex11, 1
+instance = comp, \s|ctr[3]~DUPLICATE , s|ctr[3]~DUPLICATE, ex11, 1
+instance = comp, \s|ctr~0 , s|ctr~0, ex11, 1
+instance = comp, \s|ctr[2] , s|ctr[2], ex11, 1
+instance = comp, \s|clk_1MHz~0 , s|clk_1MHz~0, ex11, 1
+instance = comp, \s|clk_1MHz , s|clk_1MHz, ex11, 1
+instance = comp, \s|state~0 , s|state~0, ex11, 1
+instance = comp, \s|state[4]~DUPLICATE , s|state[4]~DUPLICATE, ex11, 1
+instance = comp, \s|state~1 , s|state~1, ex11, 1
+instance = comp, \s|state[1] , s|state[1], ex11, 1
+instance = comp, \s|state~2 , s|state~2, ex11, 1
+instance = comp, \s|state[2]~DUPLICATE , s|state[2]~DUPLICATE, ex11, 1
+instance = comp, \s|state~3 , s|state~3, ex11, 1
+instance = comp, \s|state[3] , s|state[3], ex11, 1
+instance = comp, \s|state[2] , s|state[2], ex11, 1
+instance = comp, \t|count[6] , t|count[6], ex11, 1
+instance = comp, \t|Add0~9 , t|Add0~9, ex11, 1
+instance = comp, \t|count[0]~1 , t|count[0]~1, ex11, 1
+instance = comp, \t|count[0] , t|count[0], ex11, 1
+instance = comp, \t|Add0~13 , t|Add0~13, ex11, 1
+instance = comp, \t|count[1]~2 , t|count[1]~2, ex11, 1
+instance = comp, \t|count[1] , t|count[1], ex11, 1
+instance = comp, \t|Add0~17 , t|Add0~17, ex11, 1
+instance = comp, \t|count[2]~3 , t|count[2]~3, ex11, 1
+instance = comp, \t|count[2]~DUPLICATE , t|count[2]~DUPLICATE, ex11, 1
+instance = comp, \t|Add0~53 , t|Add0~53, ex11, 1
+instance = comp, \t|count[3] , t|count[3], ex11, 1
+instance = comp, \t|Add0~49 , t|Add0~49, ex11, 1
+instance = comp, \t|count[4] , t|count[4], ex11, 1
+instance = comp, \t|Add0~5 , t|Add0~5, ex11, 1
+instance = comp, \t|count[5] , t|count[5], ex11, 1
+instance = comp, \t|Add0~57 , t|Add0~57, ex11, 1
+instance = comp, \t|count[6]~DUPLICATE , t|count[6]~DUPLICATE, ex11, 1
+instance = comp, \t|count[11]~DUPLICATE , t|count[11]~DUPLICATE, ex11, 1
+instance = comp, \t|Add0~21 , t|Add0~21, ex11, 1
+instance = comp, \t|count[7]~4 , t|count[7]~4, ex11, 1
+instance = comp, \t|count[7] , t|count[7], ex11, 1
+instance = comp, \t|Add0~25 , t|Add0~25, ex11, 1
+instance = comp, \t|count[8]~5 , t|count[8]~5, ex11, 1
+instance = comp, \t|count[8]~DUPLICATE , t|count[8]~DUPLICATE, ex11, 1
+instance = comp, \t|Add0~1 , t|Add0~1, ex11, 1
+instance = comp, \t|count[9]~0 , t|count[9]~0, ex11, 1
+instance = comp, \t|count[9] , t|count[9], ex11, 1
+instance = comp, \t|Add0~33 , t|Add0~33, ex11, 1
+instance = comp, \t|count[10] , t|count[10], ex11, 1
+instance = comp, \t|Add0~61 , t|Add0~61, ex11, 1
+instance = comp, \t|count[11] , t|count[11], ex11, 1
+instance = comp, \t|count[4]~DUPLICATE , t|count[4]~DUPLICATE, ex11, 1
+instance = comp, \t|Equal0~2 , t|Equal0~2, ex11, 1
+instance = comp, \t|Add0~29 , t|Add0~29, ex11, 1
+instance = comp, \t|count[12]~6 , t|count[12]~6, ex11, 1
+instance = comp, \t|count[12] , t|count[12], ex11, 1
+instance = comp, \t|Add0~37 , t|Add0~37, ex11, 1
+instance = comp, \t|count[13] , t|count[13], ex11, 1
+instance = comp, \t|Add0~41 , t|Add0~41, ex11, 1
+instance = comp, \t|count[14]~DUPLICATE , t|count[14]~DUPLICATE, ex11, 1
+instance = comp, \t|Add0~45 , t|Add0~45, ex11, 1
+instance = comp, \t|count[15] , t|count[15], ex11, 1
+instance = comp, \t|count[14] , t|count[14], ex11, 1
+instance = comp, \t|Equal0~1 , t|Equal0~1, ex11, 1
+instance = comp, \t|count[2] , t|count[2], ex11, 1
+instance = comp, \t|count[8] , t|count[8], ex11, 1
+instance = comp, \t|count[7]~DUPLICATE , t|count[7]~DUPLICATE, ex11, 1
+instance = comp, \t|Equal0~0 , t|Equal0~0, ex11, 1
+instance = comp, \t|Equal0~3 , t|Equal0~3, ex11, 1
+instance = comp, \t|CLK_OUT , t|CLK_OUT, ex11, 1
+instance = comp, \s|sr_state.IDLE~0 , s|sr_state.IDLE~0, ex11, 1
+instance = comp, \s|sr_state.IDLE , s|sr_state.IDLE, ex11, 1
+instance = comp, \s|Selector2~0 , s|Selector2~0, ex11, 1
+instance = comp, \s|sr_state.WAIT_CSB_HIGH , s|sr_state.WAIT_CSB_HIGH, ex11, 1
+instance = comp, \s|sr_state.WAIT_CSB_FALL~0 , s|sr_state.WAIT_CSB_FALL~0, ex11, 1
+instance = comp, \s|sr_state.WAIT_CSB_FALL , s|sr_state.WAIT_CSB_FALL, ex11, 1
+instance = comp, \s|Selector3~0 , s|Selector3~0, ex11, 1
+instance = comp, \s|state[0] , s|state[0], ex11, 1
+instance = comp, \s|state[4] , s|state[4], ex11, 1
+instance = comp, \s|WideNor0 , s|WideNor0, ex11, 1
+instance = comp, \SW[9]~input , SW[9]~input, ex11, 1
+instance = comp, \s|shift_reg[11]~feeder , s|shift_reg[11]~feeder, ex11, 1
+instance = comp, \SW[8]~input , SW[8]~input, ex11, 1
+instance = comp, \s|shift_reg[10]~feeder , s|shift_reg[10]~feeder, ex11, 1
+instance = comp, \SW[7]~input , SW[7]~input, ex11, 1
+instance = comp, \s|shift_reg[9]~feeder , s|shift_reg[9]~feeder, ex11, 1
+instance = comp, \SW[6]~input , SW[6]~input, ex11, 1
+instance = comp, \s|shift_reg[8]~feeder , s|shift_reg[8]~feeder, ex11, 1
+instance = comp, \SW[5]~input , SW[5]~input, ex11, 1
+instance = comp, \s|shift_reg[7]~feeder , s|shift_reg[7]~feeder, ex11, 1
+instance = comp, \SW[4]~input , SW[4]~input, ex11, 1
+instance = comp, \s|shift_reg[6]~feeder , s|shift_reg[6]~feeder, ex11, 1
+instance = comp, \SW[3]~input , SW[3]~input, ex11, 1
+instance = comp, \s|shift_reg[5]~feeder , s|shift_reg[5]~feeder, ex11, 1
+instance = comp, \SW[2]~input , SW[2]~input, ex11, 1
+instance = comp, \s|shift_reg[4]~feeder , s|shift_reg[4]~feeder, ex11, 1
+instance = comp, \SW[1]~input , SW[1]~input, ex11, 1
+instance = comp, \s|shift_reg[3]~feeder , s|shift_reg[3]~feeder, ex11, 1
+instance = comp, \SW[0]~input , SW[0]~input, ex11, 1
+instance = comp, \s|shift_reg~4 , s|shift_reg~4, ex11, 1
+instance = comp, \s|shift_reg[2] , s|shift_reg[2], ex11, 1
+instance = comp, \s|always5~0 , s|always5~0, ex11, 1
+instance = comp, \s|shift_reg[3] , s|shift_reg[3], ex11, 1
+instance = comp, \s|shift_reg[4] , s|shift_reg[4], ex11, 1
+instance = comp, \s|shift_reg[5] , s|shift_reg[5], ex11, 1
+instance = comp, \s|shift_reg[6] , s|shift_reg[6], ex11, 1
+instance = comp, \s|shift_reg[7] , s|shift_reg[7], ex11, 1
+instance = comp, \s|shift_reg[8] , s|shift_reg[8], ex11, 1
+instance = comp, \s|shift_reg[9] , s|shift_reg[9], ex11, 1
+instance = comp, \s|shift_reg[10] , s|shift_reg[10], ex11, 1
+instance = comp, \s|shift_reg[11] , s|shift_reg[11], ex11, 1
+instance = comp, \s|shift_reg~3 , s|shift_reg~3, ex11, 1
+instance = comp, \s|shift_reg[12] , s|shift_reg[12], ex11, 1
+instance = comp, \s|shift_reg~2 , s|shift_reg~2, ex11, 1
+instance = comp, \s|shift_reg[13] , s|shift_reg[13], ex11, 1
+instance = comp, \s|shift_reg~1 , s|shift_reg~1, ex11, 1
+instance = comp, \s|shift_reg[14] , s|shift_reg[14], ex11, 1
+instance = comp, \s|shift_reg~0 , s|shift_reg~0, ex11, 1
+instance = comp, \s|shift_reg[15] , s|shift_reg[15], ex11, 1
+instance = comp, \s|Equal2~0 , s|Equal2~0, ex11, 1
+instance = comp, \s|dac_sck , s|dac_sck, ex11, 1
+instance = comp, \p|count[0]~0 , p|count[0]~0, ex11, 1
+instance = comp, \p|count[0] , p|count[0], ex11, 1
+instance = comp, \p|Add0~9 , p|Add0~9, ex11, 1
+instance = comp, \p|count[1] , p|count[1], ex11, 1
+instance = comp, \p|Add0~5 , p|Add0~5, ex11, 1
+instance = comp, \p|count[2] , p|count[2], ex11, 1
+instance = comp, \p|Add0~1 , p|Add0~1, ex11, 1
+instance = comp, \p|count[3] , p|count[3], ex11, 1
+instance = comp, \p|Add0~25 , p|Add0~25, ex11, 1
+instance = comp, \p|count[4] , p|count[4], ex11, 1
+instance = comp, \p|Add0~13 , p|Add0~13, ex11, 1
+instance = comp, \p|count[5] , p|count[5], ex11, 1
+instance = comp, \p|d[5] , p|d[5], ex11, 1
+instance = comp, \p|d[4] , p|d[4], ex11, 1
+instance = comp, \p|Add0~21 , p|Add0~21, ex11, 1
+instance = comp, \p|count[6] , p|count[6], ex11, 1
+instance = comp, \p|Add0~17 , p|Add0~17, ex11, 1
+instance = comp, \p|count[7] , p|count[7], ex11, 1
+instance = comp, \p|d[6] , p|d[6], ex11, 1
+instance = comp, \p|d[7] , p|d[7], ex11, 1
+instance = comp, \p|LessThan0~2 , p|LessThan0~2, ex11, 1
+instance = comp, \p|LessThan0~3 , p|LessThan0~3, ex11, 1
+instance = comp, \p|d[8] , p|d[8], ex11, 1
+instance = comp, \p|count[8] , p|count[8], ex11, 1
+instance = comp, \p|Add0~33 , p|Add0~33, ex11, 1
+instance = comp, \p|count[8]~DUPLICATE , p|count[8]~DUPLICATE, ex11, 1
+instance = comp, \p|d[9] , p|d[9], ex11, 1
+instance = comp, \p|Add0~29 , p|Add0~29, ex11, 1
+instance = comp, \p|count[9] , p|count[9], ex11, 1
+instance = comp, \p|LessThan0~7 , p|LessThan0~7, ex11, 1
+instance = comp, \p|d[3] , p|d[3], ex11, 1
+instance = comp, \p|d[2] , p|d[2], ex11, 1
+instance = comp, \p|d[1]~feeder , p|d[1]~feeder, ex11, 1
+instance = comp, \p|d[1] , p|d[1], ex11, 1
+instance = comp, \p|d[0] , p|d[0], ex11, 1
+instance = comp, \p|LessThan0~0 , p|LessThan0~0, ex11, 1
+instance = comp, \p|LessThan0~1 , p|LessThan0~1, ex11, 1
+instance = comp, \p|LessThan0~6 , p|LessThan0~6, ex11, 1
+instance = comp, \p|LessThan0~4 , p|LessThan0~4, ex11, 1
+instance = comp, \p|LessThan0~5 , p|LessThan0~5, ex11, 1
+instance = comp, \p|LessThan0~8 , p|LessThan0~8, ex11, 1
+instance = comp, \p|pwm_out , p|pwm_out, ex11, 1
+instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, ex11, 1
diff --git a/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do b/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do new file mode 100755 index 0000000..281cccf --- /dev/null +++ b/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do @@ -0,0 +1,9 @@ +transcript on
+if {[file exists rtl_work]} {
+ vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
diff --git a/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak b/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak new file mode 100755 index 0000000..281cccf --- /dev/null +++ b/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak @@ -0,0 +1,9 @@ +transcript on
+if {[file exists rtl_work]} {
+ vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
diff --git a/part_3/ex11/simulation/modelsim/modelsim.ini b/part_3/ex11/simulation/modelsim/modelsim.ini new file mode 100755 index 0000000..3912feb --- /dev/null +++ b/part_3/ex11/simulation/modelsim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+work = rtl_work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer). The other settings
+; are to send messages only to the transcript or only to the
+; wlf file. The valid values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
diff --git a/part_3/ex11/simulation/modelsim/msim_transcript b/part_3/ex11/simulation/modelsim/msim_transcript new file mode 100755 index 0000000..cb744ab --- /dev/null +++ b/part_3/ex11/simulation/modelsim/msim_transcript @@ -0,0 +1,20 @@ +# Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl
+# do ex10_run_msim_rtl_verilog.do
+# if {[file exists rtl_work]} {
+# vdel -lib rtl_work -all
+# }
+# vlib rtl_work
+# vmap work rtl_work
+# Copying C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
+# Modifying modelsim.ini
+# ** Warning: Copied C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
+# Updated modelsim.ini.
+#
+# vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
+# -- Compiling module spi2dac
+#
+# Top level modules:
+# spi2dac
+#
+# Load canceled
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_info b/part_3/ex11/simulation/modelsim/rtl_work/_info new file mode 100755 index 0000000..499bdd4 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/rtl_work/_info @@ -0,0 +1,25 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\New folder\ex10\simulation\modelsim +vspi2dac +!i10b 1 +!s100 Yc_:?1WP<4LKj7cQXiUbl1 +IzTNjHgWKkeSFYc0]WM5Gm2 +VFNOGDa=aYhJTn=76LYB@A2 +Z1 dC:\New folder\ex10\simulation\modelsim +w1478805578 +8C:/New folder/ex10/verilog_files/spi2dac.v +FC:/New folder/ex10/verilog_files/spi2dac.v +L0 9 +OV;L;10.1d;51 +r1 +!s85 0 +31 +!s108 1480413939.783000 +!s107 C:/New folder/ex10/verilog_files/spi2dac.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v| +!s101 -O0 +o-vlog01compat -work work -O0 +!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0 diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_vmake b/part_3/ex11/simulation/modelsim/rtl_work/_vmake new file mode 100755 index 0000000..2f7e729 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/rtl_work/_vmake @@ -0,0 +1,3 @@ +m255 +K3 +cModel Technology diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.dat b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.dat Binary files differnew file mode 100755 index 0000000..a728b27 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.dat diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.dbs b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.dbs Binary files differnew file mode 100755 index 0000000..740ad04 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.dbs diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd new file mode 100755 index 0000000..e874ed3 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd @@ -0,0 +1,30 @@ +library verilog; +use verilog.vl_types.all; +entity spi2dac is + generic( + BUF : vl_logic := Hi1; + GA_N : vl_logic := Hi1; + SHDN_N : vl_logic := Hi1; + TC : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0); + IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0); + WAIT_CSB_FALL : vl_logic_vector(0 to 1) := (Hi0, Hi1); + WAIT_CSB_HIGH : vl_logic_vector(0 to 1) := (Hi1, Hi0) + ); + port( + sysclk : in vl_logic; + data_in : in vl_logic_vector(9 downto 0); + load : in vl_logic; + dac_sdi : out vl_logic; + dac_cs : out vl_logic; + dac_sck : out vl_logic; + dac_ld : out vl_logic + ); + attribute mti_svvh_generic_type : integer; + attribute mti_svvh_generic_type of BUF : constant is 1; + attribute mti_svvh_generic_type of GA_N : constant is 1; + attribute mti_svvh_generic_type of SHDN_N : constant is 1; + attribute mti_svvh_generic_type of TC : constant is 1; + attribute mti_svvh_generic_type of IDLE : constant is 1; + attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1; + attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1; +end spi2dac; diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/verilog.prw b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/verilog.prw Binary files differnew file mode 100755 index 0000000..ca1d7f3 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/verilog.prw diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/verilog.psm b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/verilog.psm Binary files differnew file mode 100755 index 0000000..97c417f --- /dev/null +++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/verilog.psm diff --git a/part_3/ex11/simulation/modelsim/vsim.wlf b/part_3/ex11/simulation/modelsim/vsim.wlf Binary files differnew file mode 100755 index 0000000..54e1dca --- /dev/null +++ b/part_3/ex11/simulation/modelsim/vsim.wlf |