| Mode | Name | Size | |
|---|---|---|---|
| d--------- | .qsys_edit | 82 | logstatsplain |
| -rwxr-xr-x | c5_pin_model_dump.txt | 4875 | logstatsplain |
| d--------- | db | 2988 | logstatsplain |
| -rwxr-xr-x | ex10.qpf | 1350 | logstatsplain |
| -rwxr-xr-x | ex10.qsf | 15910 | logstatsplain |
| -rwxr-xr-x | ex10.qws | 1745 | logstatsplain |
| -rwxr-xr-x | ex10.v.bak | 1 | logstatsplain |
| -rwxr-xr-x | ex10_assignment_defaults.qdf | 55089 | logstatsplain |
| -rwxr-xr-x | ex10_nativelink_simulation.rpt | 977 | logstatsplain |
| -rwxr-xr-x | ex11.v | 328 | logstatsplain |
| -rwxr-xr-x | ex11.v.bak | 310 | logstatsplain |
| d--------- | incremental_db | 80 | logstatsplain |
| d--------- | output_files | 595 | logstatsplain |
| d--------- | simulation / modelsim | 35 | logstatsplain |
| d--------- | verilog_files | 152 | logstatsplain |
 |
index : VerilogCoursework | |
| Unnamed repository; edit this file 'description' to name the repository. |
| summaryrefslogtreecommitdiffstats |