Added resource utilization to xilinx eval

4 files changed, 148 insertions, 6 deletions

diff --git a/scripts/vivado/.gitignore b/scripts/vivado/.gitignore
index 6103060..bdaae89 100644
--- a/scripts/vivado/.gitignore
+++ b/scripts/vivado/.gitignore
@@ -1,5 +1,4 @@
 synth_*.log
 synth_*.mmi
 synth_*.bit
-synth_*.v
 tab_*/
diff --git a/scripts/vivado/synth_area.tcl b/scripts/vivado/synth_area.tcl
index 3f52644..f77be21 100644
--- a/scripts/vivado/synth_area.tcl
+++ b/scripts/vivado/synth_area.tcl
@@ -1,12 +1,14 @@
 
 read_verilog ../../picorv32.v
+read_verilog synth_area_top.v
 read_xdc synth_area.xdc
 
 synth_design -part xc7k70t-fbg676 -top picorv32_axi
-opt_design
+# synth_design -part xc7k70t-fbg676 -top top_small
+# synth_design -part xc7k70t-fbg676 -top top_regular
+# synth_design -part xc7k70t-fbg676 -top top_large
+opt_design -resynth_seq_area
 
 report_utilization
 # report_timing
 
-write_verilog -force synth_area.v
-
diff --git a/scripts/vivado/synth_area_top.v b/scripts/vivado/synth_area_top.v
new file mode 100644
index 0000000..559ae6e
--- /dev/null
+++ b/scripts/vivado/synth_area_top.v
@@ -0,0 +1,143 @@
+
+module top_small (
+	input clk, resetn,
+	output trap,
+
+	output        mem_valid,
+	output        mem_instr,
+	input         mem_ready,
+
+	output [31:0] mem_addr,
+	output [31:0] mem_wdata,
+	output [ 3:0] mem_wstrb,
+	input  [31:0] mem_rdata
+);
+	picorv32 #(
+		.ENABLE_COUNTERS(0),
+		.ENABLE_REGS_16_31(0),
+		.ENABLE_REGS_DUALPORT(1),
+		.LATCHED_MEM_RDATA(1)
+	) picorv32 (
+		.clk      (clk      ),
+		.resetn   (resetn   ),
+		.trap     (trap     ),
+		.mem_valid(mem_valid),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_rdata(mem_rdata)
+	);
+endmodule
+
+module top_regular (
+	input clk, resetn,
+	output trap,
+
+	output        mem_valid,
+	output        mem_instr,
+	input         mem_ready,
+
+	output [31:0] mem_addr,
+	output [31:0] mem_wdata,
+	output [ 3:0] mem_wstrb,
+	input  [31:0] mem_rdata,
+
+	// Look-Ahead Interface
+	output        mem_la_read,
+	output        mem_la_write,
+	output [31:0] mem_la_addr,
+	output [31:0] mem_la_wdata,
+	output [ 3:0] mem_la_wstrb
+);
+	picorv32 picorv32 (
+		.clk         (clk         ),
+		.resetn      (resetn      ),
+		.trap        (trap        ),
+		.mem_valid   (mem_valid   ),
+		.mem_instr   (mem_instr   ),
+		.mem_ready   (mem_ready   ),
+		.mem_addr    (mem_addr    ),
+		.mem_wdata   (mem_wdata   ),
+		.mem_wstrb   (mem_wstrb   ),
+		.mem_rdata   (mem_rdata   ),
+		.mem_la_read (mem_la_read ),
+		.mem_la_write(mem_la_write),
+		.mem_la_addr (mem_la_addr ),
+		.mem_la_wdata(mem_la_wdata),
+		.mem_la_wstrb(mem_la_wstrb)
+	);
+endmodule
+
+module top_large (
+	input clk, resetn,
+	output trap,
+
+	output        mem_valid,
+	output        mem_instr,
+	input         mem_ready,
+
+	output [31:0] mem_addr,
+	output [31:0] mem_wdata,
+	output [ 3:0] mem_wstrb,
+	input  [31:0] mem_rdata,
+
+	// Look-Ahead Interface
+	output        mem_la_read,
+	output        mem_la_write,
+	output [31:0] mem_la_addr,
+	output [31:0] mem_la_wdata,
+	output [ 3:0] mem_la_wstrb,
+
+	// Pico Co-Processor Interface (PCPI)
+	output        pcpi_insn_valid,
+	output [31:0] pcpi_insn,
+	output        pcpi_rs1_valid,
+	output [31:0] pcpi_rs1,
+	output        pcpi_rs2_valid,
+	output [31:0] pcpi_rs2,
+	input         pcpi_rd_valid,
+	input  [31:0] pcpi_rd,
+	input         pcpi_wait,
+	input         pcpi_ready,
+
+	// IRQ Interface
+	input  [31:0] irq,
+	output [31:0] eoi
+);
+	picorv32 #(
+		.ENABLE_PCPI(1),
+		.ENABLE_MUL(1),
+		.ENABLE_IRQ(1)
+	) picorv32 (
+		.clk            (clk            ),
+		.resetn         (resetn         ),
+		.trap           (trap           ),
+		.mem_valid      (mem_valid      ),
+		.mem_instr      (mem_instr      ),
+		.mem_ready      (mem_ready      ),
+		.mem_addr       (mem_addr       ),
+		.mem_wdata      (mem_wdata      ),
+		.mem_wstrb      (mem_wstrb      ),
+		.mem_rdata      (mem_rdata      ),
+		.mem_la_read    (mem_la_read    ),
+		.mem_la_write   (mem_la_write   ),
+		.mem_la_addr    (mem_la_addr    ),
+		.mem_la_wdata   (mem_la_wdata   ),
+		.mem_la_wstrb   (mem_la_wstrb   ),
+		.pcpi_insn_valid(pcpi_insn_valid),
+		.pcpi_insn      (pcpi_insn      ),
+		.pcpi_rs1_valid (pcpi_rs1_valid ),
+		.pcpi_rs1       (pcpi_rs1       ),
+		.pcpi_rs2_valid (pcpi_rs2_valid ),
+		.pcpi_rs2       (pcpi_rs2       ),
+		.pcpi_rd_valid  (pcpi_rd_valid  ),
+		.pcpi_rd        (pcpi_rd        ),
+		.pcpi_wait      (pcpi_wait      ),
+		.pcpi_ready     (pcpi_ready     ),
+		.irq            (irq            ),
+		.eoi            (eoi            )
+	);
+endmodule
+
diff --git a/scripts/vivado/synth_speed.tcl b/scripts/vivado/synth_speed.tcl
index ae81560..f3874e4 100644
--- a/scripts/vivado/synth_speed.tcl
+++ b/scripts/vivado/synth_speed.tcl
@@ -11,5 +11,3 @@ route_design
 report_utilization
 report_timing
 
-write_verilog -force synth_speed.v
-