Add initial filesHEADmaster

1 files changed, 8 insertions, 0 deletions

diff --git a/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v b/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v
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index 0000000..0700c08
--- /dev/null
+++ b/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v
@@ -0,0 +1,8 @@
+module top (y_1, y_2, clk, wire0, wire1, wire2, wire3);
+  top_gen top_gen (.y(y_1), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3));
+  top_syn top_syn (.y(y_2), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3));
+  always
+    @(posedge clk) begin
+      assert ((y_1 == y_2));
+    end
+endmodule