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path: root/src/translation/Veriloggen.v
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* Add more operators and print themYann Herklotz2020-03-311-37/+69
* Improve Verilog error messagesYann Herklotz2020-03-311-1/+7
* Rename to transf_programYann Herklotz2020-03-291-1/+1
* Complete conversion from HTL to VerilogYann Herklotz2020-03-291-8/+91
* Add Verilog generation from HTLYann Herklotz2020-03-291-0/+135