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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-02 11:28:42 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-02 11:28:42 +0100 |
| commit | db5b066ad6ad7e05295209ffd8f003a6d5b6bb5a (patch) | |
| tree | 5a18fe11118a25f5562c75c515687ba00f3ae836 /src | |
| parent | 5e3abd02be92f801a86d17501d82b22c644946b7 (diff) | |
| download | verismith-db5b066ad6ad7e05295209ffd8f003a6d5b6bb5a.tar.gz verismith-db5b066ad6ad7e05295209ffd8f003a6d5b6bb5a.zip | |
Fix indentation
Diffstat (limited to 'src')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/AST.hs | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 4f2c52d..184390e 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -213,16 +213,16 @@ data ContAssign = ContAssign { _contAssignNetLVal :: Identifier data Stmnt = TimeCtrl { _statDelay :: Delay , _statDStat :: Maybe Stmnt } -- ^ Time control (@#NUM@) - | EventCtrl { _statEvent :: Event - , _statEStat :: Maybe Stmnt - } - | SeqBlock { _statements :: [Stmnt] } -- ^ Sequential block (@begin ... end@) - | BlockAssign Assign -- ^ blocking assignment (@=@) - | NonBlockAssign Assign -- ^ Non blocking assignment (@<=@) - | StatCA ContAssign -- ^ Stmnt continuous assignment. May not be correct. - | TaskEnable Task - | SysTaskEnable Task - deriving (Eq) + | EventCtrl { _statEvent :: Event + , _statEStat :: Maybe Stmnt + } + | SeqBlock { _statements :: [Stmnt] } -- ^ Sequential block (@begin ... end@) + | BlockAssign Assign -- ^ blocking assignment (@=@) + | NonBlockAssign Assign -- ^ Non blocking assignment (@<=@) + | StatCA ContAssign -- ^ Stmnt continuous assignment. May not be correct. + | TaskEnable Task + | SysTaskEnable Task + deriving (Eq) instance Semigroup Stmnt where (SeqBlock a) <> (SeqBlock b) = SeqBlock $ a <> b |