diff options
author | Yann Herklotz <ymherklotz@gmail.com> | 2017-02-22 00:14:38 +0000 |
---|---|---|
committer | Yann Herklotz <ymherklotz@gmail.com> | 2017-02-22 00:14:38 +0000 |
commit | e318230b35fc130d74f1b4c6b70bbb2d5afe6780 (patch) | |
tree | 1a1730eb8f35f6932ce82e349c2dba1c089b1b64 /planAhead_run_2 | |
parent | 0446c43ffae38888dfad9120281acde6a7954509 (diff) | |
download | FPGA_Playground-master.tar.gz FPGA_Playground-master.zip |
Diffstat (limited to 'planAhead_run_2')
17 files changed, 1700 insertions, 0 deletions
diff --git a/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif b/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif new file mode 100644 index 0000000..ad5dec0 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif @@ -0,0 +1,1149 @@ +(edif led + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2017 2 21 20 23 20) + (program "Xilinx ngc2edif" (version "P.20131013")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure led.ngc led.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDS + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDR + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell BUFGP + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4_L + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port LO + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library led_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell led + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CLK + (direction INPUT) + ) + (port A0 + (direction OUTPUT) + ) + (designator "xc3s250e-4-vq100") + (property TYPE (string "led") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "led_led") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XST_VCC + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename A0_renamed_0 "A0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_1 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_0 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_2 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_3 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_4 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_5 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_6 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_7 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_8 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_9 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_10 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_11 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_12 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_13 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_14 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_15 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_0___renamed_1 "Mcount_count_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_0__ "Mcount_count_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_1___renamed_2 "Mcount_count_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_1__ "Mcount_count_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_2___renamed_3 "Mcount_count_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_2__ "Mcount_count_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_3___renamed_4 "Mcount_count_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_3__ "Mcount_count_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_4___renamed_5 "Mcount_count_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_4__ "Mcount_count_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_5___renamed_6 "Mcount_count_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_5__ "Mcount_count_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_6___renamed_7 "Mcount_count_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_6__ "Mcount_count_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_7___renamed_8 "Mcount_count_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_7__ "Mcount_count_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_8___renamed_9 "Mcount_count_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_8__ "Mcount_count_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_9___renamed_10 "Mcount_count_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_9__ "Mcount_count_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_10___renamed_11 "Mcount_count_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_10__ "Mcount_count_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_11___renamed_12 "Mcount_count_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_11__ "Mcount_count_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_12___renamed_13 "Mcount_count_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_12__ "Mcount_count_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_13___renamed_14 "Mcount_count_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_13__ "Mcount_count_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_14___renamed_15 "Mcount_count_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_14__ "Mcount_count_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_15__ "Mcount_count_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000025_renamed_16 "A0_cmp_eq000025") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000049_renamed_17 "A0_cmp_eq000049") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000062_renamed_18 "A0_cmp_eq000062") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance A0_cmp_eq000076 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename A0_OBUF_renamed_19 "A0_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_1__rt_renamed_20 "Mcount_count_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_2__rt_renamed_21 "Mcount_count_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_3__rt_renamed_22 "Mcount_count_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_4__rt_renamed_23 "Mcount_count_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_5__rt_renamed_24 "Mcount_count_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_6__rt_renamed_25 "Mcount_count_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_7__rt_renamed_26 "Mcount_count_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_8__rt_renamed_27 "Mcount_count_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_9__rt_renamed_28 "Mcount_count_cy<9>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_10__rt_renamed_29 "Mcount_count_cy<10>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_11__rt_renamed_30 "Mcount_count_cy<11>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_12__rt_renamed_31 "Mcount_count_cy<12>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_13__rt_renamed_32 "Mcount_count_cy<13>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_14__rt_renamed_33 "Mcount_count_cy<14>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_15__rt_renamed_34 "Mcount_count_xor<15>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename CLK_BUFGP_renamed_35 "CLK_BUFGP") + (viewRef view_1 (cellRef BUFGP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_lut_0__INV_0 "Mcount_count_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance A0_not00031_INV_0 + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000012_renamed_36 "A0_cmp_eq000012") + (viewRef view_1 (cellRef LUT4_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (net A0 + (joined + (portRef A0) + (portRef O (instanceRef A0_OBUF_renamed_19)) + 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Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <File Path="$PDATADIR/constrs_1/designprops.xml"> + <FileInfo SFType="CompatPartsDb"/> + </File> + <File Path="$PDATADIR/constrs_1/usercols.xml"> + <FileInfo SFType="UserColsDb"/> + </File> + <Config> + <Option Name="TargetConstrsFile" Val="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf"/> + <Option Name="ConstrsType" Val="UCF"/> + </Config> + </FileSet> +</DARoots> diff --git a/planAhead_run_2/FPGA-led-lights.data/constrs_1/usercols.xml b/planAhead_run_2/FPGA-led-lights.data/constrs_1/usercols.xml new file mode 100644 index 0000000..eb20735 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/constrs_1/usercols.xml @@ -0,0 +1,4 @@ +<?xml version="1.0"?> +<UserColInfo Version="1" Minor="0"> +</UserColInfo> + diff --git a/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg b/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg new file mode 100644 index 0000000..147f3a9 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg @@ -0,0 +1,20 @@ +<?xml version="1.0"?> +<Strategy Version="1" Minor="2"> + <StratHandle Name="ISE Defaults" Flow="ISE14"> + <Desc>ISE Defaults, including packing registers in IOs off</Desc> + </StratHandle> + <Step Id="ngdbuild"> + </Step> + <Step Id="map"> + <Option Id="FFPackEnum">3</Option> + </Step> + <Step Id="par"> + </Step> + <Step Id="trce"> + </Step> + <Step Id="xdl"> + </Step> + <Step Id="bitgen"> + </Step> +</Strategy> + diff --git a/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml new file mode 100644 index 0000000..fe0b8b1 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="8"> + <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc3s250evq100-4" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/> +</Runs> + diff --git a/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml b/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml new file mode 100644 index 0000000..65babe3 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" Minor="26"> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> +</DARoots> diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml new file mode 100644 index 0000000..3fd9702 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml @@ -0,0 +1,6 @@ +<?xml version="1.0"?> +<ChipScope Version="1" Minor="3"> + <UnassignedNets> + </UnassignedNets> +</ChipScope> + diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml new file mode 100644 index 0000000..9fa644d --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml @@ -0,0 +1,24 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" Minor="26"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> + <Filter Type="EDIFSrcs"/> + <File Path="$PPRDIR/../led.ngc"> + <FileInfo> + <Attr Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <File Path="$PDATADIR/sources_1/ports.xml"> + <FileInfo SFType="PortsDb"/> + </File> + <File Path="$PDATADIR/sources_1/chipscope.xml"> + <FileInfo SFType="ChipscopeDb"/> + </File> + <Config> + <Option Name="DesignMode" Val="GateLvl"/> + <Option Name="GateLvlMode" Val="EDIF"/> + <Option Name="TopFile" Val="$PPRDIR/../led.ngc"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> +</DARoots> diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml new file mode 100644 index 0000000..6edcb86 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml @@ -0,0 +1,8 @@ +<?xml version="1.0"?> +<Interface Version="1" Minor="1"> + <Ifc Id="ROOT" Top="1"> + <Port Id="CLK" Dir="IN"/> + <Port Id="A0" Dir="OUT"/> + </Ifc> +</Interface> + diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf b/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf new file mode 100644 index 0000000..9880428 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf @@ -0,0 +1,3 @@ +version:1 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00 +eof:3611541694 diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc b/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc new file mode 100644 index 0000000..5fed558 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +6d6f64655f636f756e7465727c4953454d6f6465:1 +eof: diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml new file mode 100644 index 0000000..8f356a2 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml @@ -0,0 +1,29 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<document> +<!--The data in this file is primarily intended for consumption by Xilinx tools. +The structure and the elements are likely to change over the next few releases. +This means code written to parse this file will need to be revisited each subsequent release.--> +<application name="pa" timeStamp="Tue Feb 21 20:24:50 2017"> +<section name="Project Information" visible="false"> +<property name="ProjectID" value="a3587ea880e14b0e9bda22648980fcfc" type="ProjectID"/> +<property name="ProjectIteration" value="1" type="ProjectIteration"/> +</section> +<section name="PlanAhead Usage" visible="true"> +<item name="Project Data"> +<property name="SrcSetCount" value="1" type="SrcSetCount"/> +<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> +<property name="DesignMode" value="GateLvl" type="DesignMode"/> +<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/> +</item> +<item name="Java Command Handlers"> +<property name="SaveDesign" value="1" type="JavaHandler"/> +</item> +<item name="Other"> +<property name="GuiMode" value="0" type="GuiMode"/> +<property name="BatchMode" value="0" type="BatchMode"/> +<property name="TclMode" value="0" type="TclMode"/> +<property name="ISEMode" value="3" type="ISEMode"/> +</item> +</section> +</application> +</document> diff --git a/planAhead_run_2/FPGA-led-lights.ppr b/planAhead_run_2/FPGA-led-lights.ppr new file mode 100644 index 0000000..96f3b15 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.ppr @@ -0,0 +1,28 @@ +<?xml version="1.0"?> +<!--Product Version: PlanAhead v14.7 (64-bit)--> +<Project Version="4" Minor="36"> + <FileSet Dir="sources_1" File="fileset.xml"/> + <FileSet Dir="constrs_1" File="fileset.xml"/> + <FileSet Dir="sim_1" File="fileset.xml"/> + <RunSet Dir="runs" File="runs.xml"/> + <DefaultLaunch Dir="$PRUNDIR"/> + <DefaultPromote Dir="$PROMOTEDIR"/> + <Config> + <Option Name="Id" Val="78311367463f4d3c9b887dc98454a31b"/> + <Option Name="Part" Val="xc3s250evq100-4"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="TargetLanguage" Val="Verilog"/> + <Option Name="TargetSimulator" Val="ISim"/> + <Option Name="Board" Val=""/> + <Option Name="SourceMgmtMode" Val="All"/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="CxlOverwriteLibs" Val="1"/> + <Option Name="CxlFuncsim" Val="1"/> + <Option Name="CxlTimesim" Val="1"/> + <Option Name="CxlCore" Val="1"/> + <Option Name="CxlEdk" Val="0"/> + <Option Name="CxlExcludeCores" Val="1"/> + <Option Name="CxlExcludeSubLibs" Val="0"/> + </Config> +</Project> + diff --git a/planAhead_run_2/planAhead.jou b/planAhead_run_2/planAhead.jou new file mode 100644 index 0000000..2c63572 --- /dev/null +++ b/planAhead_run_2/planAhead.jou @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 +# Start of session at: Tue Feb 21 20:23:09 2017 +# Process ID: 7744 +# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.log +# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.jou +#----------------------------------------------------------- +start_gui +source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl +startgroup +set_property package_pin P48 [get_ports A0] +endgroup +set_property is_loc_fixed false [get_ports [list A0]] +set_property is_loc_fixed true [get_ports [list A0]] +set_property iostandard LVTTL [get_ports [list A0]] +save_constraints diff --git a/planAhead_run_2/planAhead.log b/planAhead_run_2/planAhead.log new file mode 100644 index 0000000..cc59684 --- /dev/null +++ b/planAhead_run_2/planAhead.log @@ -0,0 +1,182 @@ +#----------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 +# Start of session at: Tue Feb 21 20:23:09 2017 +# Process ID: 7744 +# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.log +# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.jou +#----------------------------------------------------------- +INFO: [Common 17-78] Attempting to get a license: PlanAhead +INFO: [Common 17-290] Got license for PlanAhead +INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml +Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl +# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2" -part xc3s250evq100-4 +# set_property design_mode GateLvl [get_property srcset [current_run -impl]] +# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ] +# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} } +# set_param project.pinAheadLayout yes +# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset] +Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1' +# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]] +# link_design +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +Design is defaulting to project part: xc3s250evq100-4 +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design led.ngc ... +WARNING:NetListWriters:298 - No output is written to led.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file led.edif ... +ngc2edif: Total memory usage is 103520 kilobytes + +Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif] +Finished Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif] +INFO: [Designutils 20-910] Reading macro library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn +Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn] +Finished Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn] +Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockRegion.xml +Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockBuffers.xml +Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/Package.xml +Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/IOStandards.xml +INFO: [Device 21-19] Loading pkg sso from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/SSORules.xml +Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/drc.xml +INFO: [Timing 38-77] Reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib. +INFO: [Timing 38-34] Done reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib. +Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P144 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:25] +WARNING: [Constraints 18-7] Clock terminal CLK is located on a non-clock IO location P94 this can produce sub-optimal results [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:29] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P101 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:30] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P51 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:33] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P56 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:34] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P75 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:39] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P81 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:41] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P93 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:45] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P100 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:47] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P97 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:49] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P87 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:51] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P82 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:53] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P80 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:54] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P74 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:56] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P59 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:59] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P55 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:61] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P114 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:64] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P115 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:65] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P116 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:66] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P117 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:67] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P118 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:68] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P119 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:69] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P120 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:70] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P121 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:71] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P123 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:72] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P124 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:73] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P126 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:74] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P127 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:75] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P131 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:76] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P132 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:77] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P133 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:78] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P134 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:79] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P140 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:80] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P139 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:81] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P138 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:82] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P137 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:83] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P46 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:84] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P45 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:85] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P141 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:90] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92] +INFO: [Common 17-14] Message 'Constraints 18-11' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings. +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P14 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:97] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P8 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:100] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P21 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:101] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P29 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:107] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P7 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:109] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P143 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:111] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P142 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:112] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P6 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:113] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P1 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:116] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P112 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:119] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P107 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:120] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P109 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:121] +INFO: [Common 17-14] Message 'Designutils 20-30' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings. +Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf] +INFO: [Designutils 20-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Phase 0 | Netlist Checksum: 790793e2 +link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 2818.992 ; gain = 132.293 +startgroup +set_property package_pin P48 [get_ports A0] +endgroup +set_property is_loc_fixed false [get_ports [list A0]] +set_property is_loc_fixed true [get_ports [list A0]] +set_property iostandard LVTTL [get_ports [list A0]] +save_constraints +exit +ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR + (See /home/yannherklotz/Github/FPGA-led-lights/planAhead_pid7744.debug) +ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors. +INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 20:24:51 2017... +INFO: [Common 17-83] Releasing license: PlanAhead diff --git a/planAhead_run_2/planAhead_run.log b/planAhead_run_2/planAhead_run.log new file mode 100644 index 0000000..319ae82 --- /dev/null +++ b/planAhead_run_2/planAhead_run.log @@ -0,0 +1,179 @@ + +****** PlanAhead v14.7 (64-bit) + **** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 + ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. + +INFO: [Common 17-78] Attempting to get a license: PlanAhead +INFO: [Common 17-290] Got license for PlanAhead +INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml +Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl +# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2" -part xc3s250evq100-4 +# set_property design_mode GateLvl [get_property srcset [current_run -impl]] +# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ] +# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} } +# set_param project.pinAheadLayout yes +# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset] +Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1' +# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]] +# link_design +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +Design is defaulting to project part: xc3s250evq100-4 +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design led.ngc ... +WARNING:NetListWriters:298 - No output is written to led.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file led.edif ... +ngc2edif: Total memory usage is 103520 kilobytes + +Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif] +Finished Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif] +INFO: [Designutils 20-910] Reading macro library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn +Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn] +Finished Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn] +Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockRegion.xml +Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockBuffers.xml +Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/Package.xml +Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/IOStandards.xml +INFO: [Device 21-19] Loading pkg sso from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/SSORules.xml +Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/drc.xml +INFO: [Timing 38-77] Reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib. +INFO: [Timing 38-34] Done reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib. +Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P144 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:25] +WARNING: [Constraints 18-7] Clock terminal CLK is located on a non-clock IO location P94 this can produce sub-optimal results [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:29] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P101 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:30] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P51 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:33] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P56 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:34] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P75 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:39] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P81 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:41] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P93 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:45] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P100 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:47] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P97 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:49] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P87 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:51] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P82 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:53] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P80 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:54] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P74 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:56] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P59 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:59] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P55 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:61] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P114 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:64] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P115 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:65] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P116 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:66] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P117 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:67] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P118 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:68] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P119 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:69] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P120 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:70] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P121 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:71] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P123 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:72] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P124 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:73] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P126 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:74] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P127 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:75] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P131 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:76] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P132 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:77] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P133 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:78] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P134 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:79] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P140 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:80] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P139 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:81] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P138 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:82] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P137 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:83] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P46 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:84] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P45 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:85] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P141 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:90] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92] +CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92] +INFO: [Common 17-14] Message 'Constraints 18-11' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings. +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P14 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:97] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P8 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:100] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P21 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:101] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P29 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:107] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P7 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:109] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P143 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:111] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P142 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:112] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P6 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:113] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P1 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:116] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P112 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:119] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P107 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:120] +CRITICAL WARNING: [Designutils 20-30] Unrecognized site P109 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:121] +INFO: [Common 17-14] Message 'Designutils 20-30' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings. +Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf] +INFO: [Designutils 20-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Phase 0 | Netlist Checksum: 790793e2 +link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 2818.992 ; gain = 132.293 +startgroup +set_property package_pin P48 [get_ports A0] +endgroup +set_property is_loc_fixed false [get_ports [list A0]] +set_property is_loc_fixed true [get_ports [list A0]] +set_property iostandard LVTTL [get_ports [list A0]] +MEvent. CASE! +MEvent. CASE! +MEvent. CASE! +MEvent. CASE! +MEvent. CASE! +MEvent. CASE! +save_constraints +exit +ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors. +INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 20:24:51 2017... +INFO: [Common 17-83] Releasing license: PlanAhead |