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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-11-15 21:51:17 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-11-15 21:51:17 +0000 |
| commit | 2ba9d114765aa1b50e5a7dd8ae3511af08dbf1eb (patch) | |
| tree | 8f3298c353b249a80b06c798d99fdb1596c58744 | |
| parent | 2819e673167ff6a259be4f3caf5ecb7276c3799c (diff) | |
| download | VerilogCoursework-2ba9d114765aa1b50e5a7dd8ae3511af08dbf1eb.tar.gz VerilogCoursework-2ba9d114765aa1b50e5a7dd8ae3511af08dbf1eb.zip | |
Create README.md
| -rw-r--r-- | part_1/README.md | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/part_1/README.md b/part_1/README.md new file mode 100644 index 0000000..c787a1b --- /dev/null +++ b/part_1/README.md @@ -0,0 +1,3 @@ +# Experiment VERI: FPGA Design with Verilog (Part 1) +In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1-SoC Board that was made by Terasicas +We will minsdawdaw |