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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-11-15 21:52:32 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-11-15 21:52:32 +0000 |
| commit | 8f0d3245aec1a679394a9defc853418703fddbf8 (patch) | |
| tree | c9b1d765efc23757feb128e570a5e9791781fd4b | |
| parent | 2ba9d114765aa1b50e5a7dd8ae3511af08dbf1eb (diff) | |
| download | VerilogCoursework-8f0d3245aec1a679394a9defc853418703fddbf8.tar.gz VerilogCoursework-8f0d3245aec1a679394a9defc853418703fddbf8.zip | |
Update README.md
| -rw-r--r-- | part_1/README.md | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/part_1/README.md b/part_1/README.md index c787a1b..c575738 100644 --- a/part_1/README.md +++ b/part_1/README.md @@ -1,3 +1,2 @@ # Experiment VERI: FPGA Design with Verilog (Part 1) -In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1-SoC Board that was made by Terasicas -We will minsdawdaw +In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1-SoC Board that was made by Terasicas. We will mainy be |