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| author | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
| commit | ee5d729de8ea22b4d7524bf839ba08fcb4b3843d (patch) | |
| tree | a6cbbd40144834affb26acfeaaa8e9159b7cf4a9 /part_1/ex1/db/ex1.lpc.html | |
| download | VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.tar.gz VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.zip | |
adding first project and initial files
Diffstat (limited to 'part_1/ex1/db/ex1.lpc.html')
| -rw-r--r-- | part_1/ex1/db/ex1.lpc.html | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/part_1/ex1/db/ex1.lpc.html b/part_1/ex1/db/ex1.lpc.html new file mode 100644 index 0000000..75daae6 --- /dev/null +++ b/part_1/ex1/db/ex1.lpc.html @@ -0,0 +1,34 @@ +<TABLE>
+<TR bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
|