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| author | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-11-15 21:33:02 +0000 |
| commit | ee5d729de8ea22b4d7524bf839ba08fcb4b3843d (patch) | |
| tree | a6cbbd40144834affb26acfeaaa8e9159b7cf4a9 /part_1/ex1/db/ex1.tmw_info | |
| download | VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.tar.gz VerilogCoursework-ee5d729de8ea22b4d7524bf839ba08fcb4b3843d.zip | |
adding first project and initial files
Diffstat (limited to 'part_1/ex1/db/ex1.tmw_info')
| -rw-r--r-- | part_1/ex1/db/ex1.tmw_info | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/part_1/ex1/db/ex1.tmw_info b/part_1/ex1/db/ex1.tmw_info new file mode 100644 index 0000000..46ba178 --- /dev/null +++ b/part_1/ex1/db/ex1.tmw_info @@ -0,0 +1,3 @@ +start_analysis_synthesis:s:00:00:13-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:35-start_full_compilation
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