adding part 2 and 3

54 files changed, 259 insertions, 0 deletions

diff --git a/part_2/ex5/db/.cmp.kpt b/part_2/ex5/db/.cmp.kpt
new file mode 100755
index 0000000..1dafbef
--- /dev/null
+++ b/part_2/ex5/db/.cmp.kpt
diff --git a/part_2/ex5/db/ex5.(0).cnf.cdb b/part_2/ex5/db/ex5.(0).cnf.cdb
new file mode 100755
index 0000000..5df78fc
--- /dev/null
+++ b/part_2/ex5/db/ex5.(0).cnf.cdb
diff --git a/part_2/ex5/db/ex5.(0).cnf.hdb b/part_2/ex5/db/ex5.(0).cnf.hdb
new file mode 100755
index 0000000..169e96a
--- /dev/null
+++ b/part_2/ex5/db/ex5.(0).cnf.hdb
diff --git a/part_2/ex5/db/ex5.analyze_file.qmsg b/part_2/ex5/db/ex5.analyze_file.qmsg
new file mode 100755
index 0000000..d39cdf7
--- /dev/null
+++ b/part_2/ex5/db/ex5.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806631495 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:23:51 2016 " "Processing started: Tue Nov 22 09:23:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "652 " "Peak virtual memory: 652 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:24:08 2016 " "Processing ended: Tue Nov 22 09:24:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}

diff --git a/part_2/ex5/db/ex5.asm.qmsg b/part_2/ex5/db/ex5.asm.qmsg
new file mode 100755
index 0000000..822de0a
--- /dev/null
+++ b/part_2/ex5/db/ex5.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806915392 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806915398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:28:35 2016 " "Processing started: Tue Nov 22 09:28:35 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806915398 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479806915398 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479806915398 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479806916542 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479806936975 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "708 " "Peak virtual memory: 708 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:28:58 2016 " "Processing ended: Tue Nov 22 09:28:58 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479806938289 ""}

diff --git a/part_2/ex5/db/ex5.asm.rdb b/part_2/ex5/db/ex5.asm.rdb
new file mode 100755
index 0000000..cb19986
--- /dev/null
+++ b/part_2/ex5/db/ex5.asm.rdb
diff --git a/part_2/ex5/db/ex5.cbx.xml b/part_2/ex5/db/ex5.cbx.xml
new file mode 100755
index 0000000..2959ffa
--- /dev/null
+++ b/part_2/ex5/db/ex5.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex5">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex5/db/ex5.cmp.bpm b/part_2/ex5/db/ex5.cmp.bpm
new file mode 100755
index 0000000..7a0383d
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.bpm
diff --git a/part_2/ex5/db/ex5.cmp.cdb b/part_2/ex5/db/ex5.cmp.cdb
new file mode 100755
index 0000000..bf4e81f
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.cdb
diff --git a/part_2/ex5/db/ex5.cmp.hdb b/part_2/ex5/db/ex5.cmp.hdb
new file mode 100755
index 0000000..64b27e8
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.hdb
diff --git a/part_2/ex5/db/ex5.cmp.idb b/part_2/ex5/db/ex5.cmp.idb
new file mode 100755
index 0000000..39203dc
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.idb
diff --git a/part_2/ex5/db/ex5.cmp.logdb b/part_2/ex5/db/ex5.cmp.logdb
new file mode 100755
index 0000000..0866a7b
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.logdb
@@ -0,0 +1,50 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;10;0;0;10;10;0;8;0;0;0;0;8;0;0;0;0;8;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,10;10;10;10;10;0;10;10;0;0;10;2;10;10;10;10;2;10;10;10;10;2;10;10;10;10;10;10,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,count[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,clock,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,enable,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex5/db/ex5.cmp.rdb b/part_2/ex5/db/ex5.cmp.rdb
new file mode 100755
index 0000000..a1fc9aa
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.rdb
diff --git a/part_2/ex5/db/ex5.cmp_merge.kpt b/part_2/ex5/db/ex5.cmp_merge.kpt
new file mode 100755
index 0000000..46430f8
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp_merge.kpt
diff --git a/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..71fed4b
--- /dev/null
+++ b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd
new file mode 100755
index 0000000..c53e8d2
--- /dev/null
+++ b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd
diff --git a/part_2/ex5/db/ex5.db_info b/part_2/ex5/db/ex5.db_info
new file mode 100755
index 0000000..83604aa
--- /dev/null
+++ b/part_2/ex5/db/ex5.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Version_Index = 419480576

+Creation_Time = Tue Nov 22 09:10:44 2016

diff --git a/part_2/ex5/db/ex5.fit.qmsg b/part_2/ex5/db/ex5.fit.qmsg
new file mode 100755
index 0000000..a42b5fb
--- /dev/null
+++ b/part_2/ex5/db/ex5.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479806830418 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479806830418 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex5 5CGXFC7C7F23C8 " "Selected device 5CGXFC7C7F23C8 for design \"ex5\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479806830529 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1479806830770 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1479806830770 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479806832299 ""}

+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1479806833191 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479806834602 ""}

+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "10 10 " "No exact pin location assignment(s) for 10 pins of 10 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1479806835217 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479806850286 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clock~inputCLKENA0 8 global CLKCTRL_G10 " "clock~inputCLKENA0 with 8 fanout uses global clock CLKCTRL_G10" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479806850601 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479806850601 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806850602 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479806850862 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479806850870 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479806850871 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479806850872 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479806850880 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479806850881 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex5.sdc " "Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479806854662 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479806854669 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479806854672 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479806854672 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479806854673 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479806854690 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479806854690 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479806854690 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:21 " "Fitter preparation operations ending: elapsed time is 00:00:21" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806855238 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479806869358 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479806870144 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:05 " "Fitter placement preparation operations ending: elapsed time is 00:00:05" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806874879 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479806877557 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479806881279 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806881280 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479806883680 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y35 X89_Y45 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45" {  } { { "loc" "" { Generic "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45"} { { 12 { 0 ""} 78 35 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479806897785 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479806897785 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479806898158 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479806898158 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806898163 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.42 " "Total time spent on timing analysis during the Fitter is 0.42 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479806902813 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479806902906 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479806903630 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479806903630 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479806905010 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:07 " "Fitter post-fit operations ending: elapsed time is 00:00:07" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806909506 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg " "Generated suppressed messages file C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479806910231 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2264 " "Peak virtual memory: 2264 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:28:31 2016 " "Processing ended: Tue Nov 22 09:28:31 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:28 " "Elapsed time: 00:01:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:40 " "Total CPU time (on all processors): 00:01:40" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479806911666 ""}

diff --git a/part_2/ex5/db/ex5.hier_info b/part_2/ex5/db/ex5.hier_info
new file mode 100755
index 0000000..8d49b87
--- /dev/null
+++ b/part_2/ex5/db/ex5.hier_info
@@ -0,0 +1,27 @@
+|ex5

+clock => count[0]~reg0.CLK

+clock => count[1]~reg0.CLK

+clock => count[2]~reg0.CLK

+clock => count[3]~reg0.CLK

+clock => count[4]~reg0.CLK

+clock => count[5]~reg0.CLK

+clock => count[6]~reg0.CLK

+clock => count[7]~reg0.CLK

+enable => count[0]~reg0.ENA

+enable => count[1]~reg0.ENA

+enable => count[2]~reg0.ENA

+enable => count[3]~reg0.ENA

+enable => count[4]~reg0.ENA

+enable => count[5]~reg0.ENA

+enable => count[6]~reg0.ENA

+enable => count[7]~reg0.ENA

+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

diff --git a/part_2/ex5/db/ex5.hif b/part_2/ex5/db/ex5.hif
new file mode 100755
index 0000000..a9b1b07
--- /dev/null
+++ b/part_2/ex5/db/ex5.hif
diff --git a/part_2/ex5/db/ex5.lpc.html b/part_2/ex5/db/ex5.lpc.html
new file mode 100755
index 0000000..7d68592
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+</TABLE>

diff --git a/part_2/ex5/db/ex5.lpc.rdb b/part_2/ex5/db/ex5.lpc.rdb
new file mode 100755
index 0000000..c179f4d
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.rdb
diff --git a/part_2/ex5/db/ex5.lpc.txt b/part_2/ex5/db/ex5.lpc.txt
new file mode 100755
index 0000000..dbfe520
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex5/db/ex5.map.ammdb b/part_2/ex5/db/ex5.map.ammdb
new file mode 100755
index 0000000..a4afc79
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.ammdb
diff --git a/part_2/ex5/db/ex5.map.bpm b/part_2/ex5/db/ex5.map.bpm
new file mode 100755
index 0000000..3592b20
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.bpm
diff --git a/part_2/ex5/db/ex5.map.cdb b/part_2/ex5/db/ex5.map.cdb
new file mode 100755
index 0000000..256c526
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.cdb
diff --git a/part_2/ex5/db/ex5.map.hdb b/part_2/ex5/db/ex5.map.hdb
new file mode 100755
index 0000000..3d0d6f2
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.hdb
diff --git a/part_2/ex5/db/ex5.map.kpt b/part_2/ex5/db/ex5.map.kpt
new file mode 100755
index 0000000..6a235ab
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.kpt
diff --git a/part_2/ex5/db/ex5.map.logdb b/part_2/ex5/db/ex5.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/db/ex5.map.qmsg b/part_2/ex5/db/ex5.map.qmsg
new file mode 100755
index 0000000..342e059
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806798609 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806798617 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:26:38 2016 " "Processing started: Tue Nov 22 09:26:38 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806798617 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806798617 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806798617 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479806799115 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479806799115 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog files/counter_8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog files/counter_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_8 " "Found entity 1: counter_8" {  } { { "verilog files/counter_8.v" "" { Text "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/counter_8.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479806815578 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806815578 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog files/ex5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog files/ex5.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex5 " "Found entity 1: ex5" {  } { { "verilog files/ex5.v" "" { Text "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479806815580 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806815580 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex5 " "Elaborating entity \"ex5\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479806815642 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479806818460 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479806820436 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479806820436 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479806821948 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479806821948 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479806821948 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479806821948 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "698 " "Peak virtual memory: 698 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:27:02 2016 " "Processing ended: Tue Nov 22 09:27:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Elapsed time: 00:00:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806822084 ""}

diff --git a/part_2/ex5/db/ex5.map.rdb b/part_2/ex5/db/ex5.map.rdb
new file mode 100755
index 0000000..d90a0c1
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.rdb
diff --git a/part_2/ex5/db/ex5.map_bb.cdb b/part_2/ex5/db/ex5.map_bb.cdb
new file mode 100755
index 0000000..ebced3a
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.cdb
diff --git a/part_2/ex5/db/ex5.map_bb.hdb b/part_2/ex5/db/ex5.map_bb.hdb
new file mode 100755
index 0000000..bb6499e
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.hdb
diff --git a/part_2/ex5/db/ex5.map_bb.logdb b/part_2/ex5/db/ex5.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/db/ex5.pre_map.hdb b/part_2/ex5/db/ex5.pre_map.hdb
new file mode 100755
index 0000000..fecb803
--- /dev/null
+++ b/part_2/ex5/db/ex5.pre_map.hdb
diff --git a/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb b/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..5cd114f
--- /dev/null
+++ b/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb
diff --git a/part_2/ex5/db/ex5.routing.rdb b/part_2/ex5/db/ex5.routing.rdb
new file mode 100755
index 0000000..34ca13b
--- /dev/null
+++ b/part_2/ex5/db/ex5.routing.rdb
diff --git a/part_2/ex5/db/ex5.rtlv.hdb b/part_2/ex5/db/ex5.rtlv.hdb
new file mode 100755
index 0000000..a8a9b60
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv.hdb
diff --git a/part_2/ex5/db/ex5.rtlv_sg.cdb b/part_2/ex5/db/ex5.rtlv_sg.cdb
new file mode 100755
index 0000000..6214e3f
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv_sg.cdb
diff --git a/part_2/ex5/db/ex5.rtlv_sg_swap.cdb b/part_2/ex5/db/ex5.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..0be030c
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv_sg_swap.cdb
diff --git a/part_2/ex5/db/ex5.sld_design_entry.sci b/part_2/ex5/db/ex5.sld_design_entry.sci
new file mode 100755
index 0000000..1bd84ed
--- /dev/null
+++ b/part_2/ex5/db/ex5.sld_design_entry.sci
diff --git a/part_2/ex5/db/ex5.sld_design_entry_dsc.sci b/part_2/ex5/db/ex5.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..1bd84ed
--- /dev/null
+++ b/part_2/ex5/db/ex5.sld_design_entry_dsc.sci
diff --git a/part_2/ex5/db/ex5.smart_action.txt b/part_2/ex5/db/ex5.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex5/db/ex5.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex5/db/ex5.sta.qmsg b/part_2/ex5/db/ex5.sta.qmsg
new file mode 100755
index 0000000..b8bb557
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta.qmsg
@@ -0,0 +1,21 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806941525 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806941531 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:29:00 2016 " "Processing started: Tue Nov 22 09:29:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806941531 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806941531 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex5 -c ex5 " "Command: quartus_sta ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806941531 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806941769 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942710 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942710 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942796 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942796 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex5.sdc " "Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944125 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944125 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clock clock " "create_clock -period 1.000 -name clock clock" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1479806944126 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944126 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944128 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944128 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806944143 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806944169 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479806944219 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944219 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.444 " "Worst-case setup slack is -1.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.444              -8.970 clock  " "   -1.444              -8.970 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944241 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.487 " "Worst-case hold slack is 0.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.487               0.000 clock  " "    0.487               0.000 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944250 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944259 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944268 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.724 " "Worst-case minimum pulse width slack is -0.724" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724              -8.917 clock  " "   -0.724              -8.917 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""}  } {
\ No newline at end of file
diff --git a/part_2/ex5/db/ex5.sta.rdb b/part_2/ex5/db/ex5.sta.rdb
new file mode 100755
index 0000000..2a68d94
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta.rdb
diff --git a/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb b/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..29b23ee
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb
diff --git a/part_2/ex5/db/ex5.tis_db_list.ddb b/part_2/ex5/db/ex5.tis_db_list.ddb
new file mode 100755
index 0000000..dec6bed
--- /dev/null
+++ b/part_2/ex5/db/ex5.tis_db_list.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb b/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..06cd923
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb b/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb
new file mode 100755
index 0000000..0c58cfe
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb b/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..6bedbe6
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex5/db/ex5.tmw_info b/part_2/ex5/db/ex5.tmw_info
new file mode 100755
index 0000000..fcbb322
--- /dev/null
+++ b/part_2/ex5/db/ex5.tmw_info
@@ -0,0 +1,4 @@
+start_analysis_synthesis:s:00:00:24-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:01:30-start_full_compilation

+start_assembler:s:00:00:27-start_full_compilation

diff --git a/part_2/ex5/db/ex5.vpr.ammdb b/part_2/ex5/db/ex5.vpr.ammdb
new file mode 100755
index 0000000..8dd3884
--- /dev/null
+++ b/part_2/ex5/db/ex5.vpr.ammdb
diff --git a/part_2/ex5/db/ex5_partition_pins.json b/part_2/ex5/db/ex5_partition_pins.json
new file mode 100755
index 0000000..1c05513
--- /dev/null
+++ b/part_2/ex5/db/ex5_partition_pins.json
@@ -0,0 +1,49 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "count[0]",

+					"strict" : false

+				},

+				{

+					"name" : "count[1]",

+					"strict" : false

+				},

+				{

+					"name" : "count[2]",

+					"strict" : false

+				},

+				{

+					"name" : "count[3]",

+					"strict" : false

+				},

+				{

+					"name" : "count[4]",

+					"strict" : false

+				},

+				{

+					"name" : "count[5]",

+					"strict" : false

+				},

+				{

+					"name" : "count[6]",

+					"strict" : false

+				},

+				{

+					"name" : "count[7]",

+					"strict" : false

+				},

+				{

+					"name" : "clock",

+					"strict" : false

+				},

+				{

+					"name" : "enable",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex5/db/prev_cmp_ex5.qmsg b/part_2/ex5/db/prev_cmp_ex5.qmsg
new file mode 100755
index 0000000..d39cdf7
--- /dev/null
+++ b/part_2/ex5/db/prev_cmp_ex5.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806631495 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:23:51 2016 " "Processing started: Tue Nov 22 09:23:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "652 " "Peak virtual memory: 652 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:24:08 2016 " "Processing ended: Tue Nov 22 09:24:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}