adding part 2 and 3

120 files changed, 3690 insertions, 0 deletions

diff --git a/part_2/ex5/c5_pin_model_dump.txt b/part_2/ex5/c5_pin_model_dump.txt
new file mode 100755
index 0000000..d8a635e
--- /dev/null
+++ b/part_2/ex5/c5_pin_model_dump.txt
@@ -0,0 +1,120 @@
+io_4iomodule_c5_index: 77gpio_index: 2

+io_4iomodule_c5_index: 60gpio_index: 476

+io_4iomodule_c5_index: 62gpio_index: 6

+io_4iomodule_c5_index: 26gpio_index: 472

+io_4iomodule_c5_index: 20gpio_index: 10

+io_4iomodule_c5_index: 12gpio_index: 468

+io_4iomodule_c5_index: 27gpio_index: 14

+io_4iomodule_c5_index: 71gpio_index: 464

+io_4iomodule_c5_index: 56gpio_index: 19

+io_4iomodule_c5_index: 14gpio_index: 460

+io_4iomodule_c5_index: 22gpio_index: 22

+io_4iomodule_c5_index: 10gpio_index: 456

+io_4iomodule_c5_index: 11gpio_index: 27

+io_4iomodule_c5_index: 73gpio_index: 452

+io_4iomodule_c5_index: 74gpio_index: 30

+io_4iomodule_c5_index: 76gpio_index: 448

+io_4iomodule_c5_index: 2gpio_index: 35

+io_4iomodule_c5_index: 78gpio_index: 444

+io_4iomodule_c5_index: 9gpio_index: 38

+io_4iomodule_c5_index: 36gpio_index: 440

+io_4iomodule_c5_index: 51gpio_index: 43

+io_4iomodule_c5_index: 23gpio_index: 436

+io_4iomodule_c5_index: 53gpio_index: 46

+io_4iomodule_c5_index: 50gpio_index: 432

+io_4iomodule_c5_index: 0gpio_index: 51

+io_4iomodule_c5_index: 43gpio_index: 428

+io_4iomodule_c5_index: 67gpio_index: 54

+io_4iomodule_c5_index: 16gpio_index: 424

+io_4iomodule_c5_index: 44gpio_index: 59

+io_4iomodule_c5_index: 29gpio_index: 420

+io_4iomodule_c5_index: 1gpio_index: 62

+io_4iomodule_c5_index: 8gpio_index: 416

+io_4iomodule_c5_index: 65gpio_index: 67

+io_4iomodule_c5_index: 25gpio_index: 412

+io_4iomodule_c5_index: 40gpio_index: 70

+io_4iomodule_c5_index: 55gpio_index: 408

+io_4iomodule_c5_index: 66gpio_index: 75

+io_4iomodule_c5_index: 5gpio_index: 404

+io_4iomodule_c5_index: 61gpio_index: 78

+io_4iomodule_c5_index: 17gpio_index: 400

+io_4iomodule_c5_index: 42gpio_index: 83

+io_4iomodule_c5_index: 59gpio_index: 396

+io_4iomodule_c5_index: 54gpio_index: 86

+io_4iomodule_c5_index: 58gpio_index: 392

+io_4iomodule_c5_index: 33gpio_index: 91

+io_4iomodule_c5_index: 41gpio_index: 388

+io_4iomodule_c5_index: 69gpio_index: 94

+io_4iomodule_c5_index: 3gpio_index: 384

+io_4iomodule_c5_index: 18gpio_index: 99

+io_4iomodule_c5_index: 15gpio_index: 380

+io_4iomodule_c5_index: 6gpio_index: 102

+io_4iomodule_c5_index: 7gpio_index: 376

+io_4iomodule_c5_index: 47gpio_index: 107

+io_4iomodule_c5_index: 39gpio_index: 372

+io_4iomodule_c5_index: 32gpio_index: 110

+io_4iomodule_c5_index: 24gpio_index: 368

+io_4iomodule_c5_index: 48gpio_index: 115

+io_4iomodule_c5_index: 57gpio_index: 364

+io_4iomodule_c5_index: 64gpio_index: 118

+io_4iomodule_c5_index: 31gpio_index: 360

+io_4iomodule_c5_index: 46gpio_index: 123

+io_4iomodule_c5_index: 21gpio_index: 356

+io_4iomodule_c5_index: 72gpio_index: 126

+io_4iomodule_c5_index: 70gpio_index: 352

+io_4iomodule_c5_index: 49gpio_index: 131

+io_4iomodule_c5_index: 63gpio_index: 348

+io_4iomodule_c5_index: 79gpio_index: 134

+io_4iomodule_c5_index: 28gpio_index: 344

+io_4iomodule_c5_index: 34gpio_index: 139

+io_4iomodule_c5_index: 4gpio_index: 340

+io_4iomodule_c5_index: 68gpio_index: 142

+io_4iomodule_c5_index: 37gpio_index: 336

+io_4iomodule_c5_index: 45gpio_index: 147

+io_4iomodule_c5_index: 35gpio_index: 332

+io_4iomodule_c5_index: 38gpio_index: 150

+io_4iomodule_c5_index: 19gpio_index: 328

+io_4iomodule_c5_index: 52gpio_index: 155

+io_4iomodule_c5_index: 30gpio_index: 324

+io_4iomodule_c5_index: 75gpio_index: 158

+io_4iomodule_c5_index: 13gpio_index: 320

+io_4iomodule_h_c5_index: 0gpio_index: 161

+io_4iomodule_h_c5_index: 15gpio_index: 165

+io_4iomodule_h_c5_index: 27gpio_index: 169

+io_4iomodule_h_c5_index: 30gpio_index: 173

+io_4iomodule_h_c5_index: 36gpio_index: 176

+io_4iomodule_h_c5_index: 37gpio_index: 180

+io_4iomodule_h_c5_index: 26gpio_index: 184

+io_4iomodule_h_c5_index: 24gpio_index: 188

+io_4iomodule_h_c5_index: 1gpio_index: 192

+io_4iomodule_h_c5_index: 21gpio_index: 196

+io_4iomodule_h_c5_index: 18gpio_index: 200

+io_4iomodule_h_c5_index: 6gpio_index: 204

+io_4iomodule_h_c5_index: 31gpio_index: 208

+io_4iomodule_h_c5_index: 3gpio_index: 212

+io_4iomodule_h_c5_index: 20gpio_index: 216

+io_4iomodule_h_c5_index: 4gpio_index: 220

+io_4iomodule_h_c5_index: 29gpio_index: 224

+io_4iomodule_h_c5_index: 22gpio_index: 228

+io_4iomodule_h_c5_index: 16gpio_index: 232

+io_4iomodule_h_c5_index: 9gpio_index: 236

+io_4iomodule_h_c5_index: 25gpio_index: 240

+io_4iomodule_h_c5_index: 11gpio_index: 244

+io_4iomodule_h_c5_index: 19gpio_index: 248

+io_4iomodule_h_c5_index: 23gpio_index: 252

+io_4iomodule_h_c5_index: 17gpio_index: 256

+io_4iomodule_h_c5_index: 8gpio_index: 260

+io_4iomodule_h_c5_index: 38gpio_index: 264

+io_4iomodule_h_c5_index: 2gpio_index: 268

+io_4iomodule_h_c5_index: 12gpio_index: 272

+io_4iomodule_h_c5_index: 35gpio_index: 276

+io_4iomodule_h_c5_index: 13gpio_index: 280

+io_4iomodule_h_c5_index: 5gpio_index: 284

+io_4iomodule_h_c5_index: 28gpio_index: 288

+io_4iomodule_h_c5_index: 7gpio_index: 292

+io_4iomodule_h_c5_index: 34gpio_index: 296

+io_4iomodule_h_c5_index: 14gpio_index: 300

+io_4iomodule_h_c5_index: 33gpio_index: 304

+io_4iomodule_h_c5_index: 39gpio_index: 308

+io_4iomodule_h_c5_index: 32gpio_index: 312

+io_4iomodule_h_c5_index: 10gpio_index: 316

diff --git a/part_2/ex5/db/.cmp.kpt b/part_2/ex5/db/.cmp.kpt
new file mode 100755
index 0000000..1dafbef
--- /dev/null
+++ b/part_2/ex5/db/.cmp.kpt
diff --git a/part_2/ex5/db/ex5.(0).cnf.cdb b/part_2/ex5/db/ex5.(0).cnf.cdb
new file mode 100755
index 0000000..5df78fc
--- /dev/null
+++ b/part_2/ex5/db/ex5.(0).cnf.cdb
diff --git a/part_2/ex5/db/ex5.(0).cnf.hdb b/part_2/ex5/db/ex5.(0).cnf.hdb
new file mode 100755
index 0000000..169e96a
--- /dev/null
+++ b/part_2/ex5/db/ex5.(0).cnf.hdb
diff --git a/part_2/ex5/db/ex5.analyze_file.qmsg b/part_2/ex5/db/ex5.analyze_file.qmsg
new file mode 100755
index 0000000..d39cdf7
--- /dev/null
+++ b/part_2/ex5/db/ex5.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806631495 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:23:51 2016 " "Processing started: Tue Nov 22 09:23:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "652 " "Peak virtual memory: 652 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:24:08 2016 " "Processing ended: Tue Nov 22 09:24:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}

diff --git a/part_2/ex5/db/ex5.asm.qmsg b/part_2/ex5/db/ex5.asm.qmsg
new file mode 100755
index 0000000..822de0a
--- /dev/null
+++ b/part_2/ex5/db/ex5.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806915392 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806915398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:28:35 2016 " "Processing started: Tue Nov 22 09:28:35 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806915398 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479806915398 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479806915398 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479806916542 ""}

+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479806936975 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "708 " "Peak virtual memory: 708 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:28:58 2016 " "Processing ended: Tue Nov 22 09:28:58 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806938289 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479806938289 ""}

diff --git a/part_2/ex5/db/ex5.asm.rdb b/part_2/ex5/db/ex5.asm.rdb
new file mode 100755
index 0000000..cb19986
--- /dev/null
+++ b/part_2/ex5/db/ex5.asm.rdb
diff --git a/part_2/ex5/db/ex5.cbx.xml b/part_2/ex5/db/ex5.cbx.xml
new file mode 100755
index 0000000..2959ffa
--- /dev/null
+++ b/part_2/ex5/db/ex5.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>

+<LOG_ROOT>

+	<PROJECT NAME="ex5">

+	</PROJECT>

+</LOG_ROOT>

diff --git a/part_2/ex5/db/ex5.cmp.bpm b/part_2/ex5/db/ex5.cmp.bpm
new file mode 100755
index 0000000..7a0383d
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.bpm
diff --git a/part_2/ex5/db/ex5.cmp.cdb b/part_2/ex5/db/ex5.cmp.cdb
new file mode 100755
index 0000000..bf4e81f
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.cdb
diff --git a/part_2/ex5/db/ex5.cmp.hdb b/part_2/ex5/db/ex5.cmp.hdb
new file mode 100755
index 0000000..64b27e8
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.hdb
diff --git a/part_2/ex5/db/ex5.cmp.idb b/part_2/ex5/db/ex5.cmp.idb
new file mode 100755
index 0000000..39203dc
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.idb
diff --git a/part_2/ex5/db/ex5.cmp.logdb b/part_2/ex5/db/ex5.cmp.logdb
new file mode 100755
index 0000000..0866a7b
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.logdb
@@ -0,0 +1,50 @@
+v1

+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,

+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,

+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,

+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,

+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,

+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,

+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,

+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,

+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,

+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,

+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,

+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,

+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;10;0;0;10;10;0;8;0;0;0;0;8;0;0;0;0;8;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,Total Inapplicable,10;10;10;10;10;0;10;10;0;0;10;2;10;10;10;10;2;10;10;10;10;2;10;10;10;10;10;10,

+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,

+IO_RULES_MATRIX,count[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,count[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,clock,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_MATRIX,enable,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,

+IO_RULES_SUMMARY,Total I/O Rules,28,

+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,

+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,

+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,

diff --git a/part_2/ex5/db/ex5.cmp.rdb b/part_2/ex5/db/ex5.cmp.rdb
new file mode 100755
index 0000000..a1fc9aa
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp.rdb
diff --git a/part_2/ex5/db/ex5.cmp_merge.kpt b/part_2/ex5/db/ex5.cmp_merge.kpt
new file mode 100755
index 0000000..46430f8
--- /dev/null
+++ b/part_2/ex5/db/ex5.cmp_merge.kpt
diff --git a/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..71fed4b
--- /dev/null
+++ b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd
new file mode 100755
index 0000000..c53e8d2
--- /dev/null
+++ b/part_2/ex5/db/ex5.cyclonev_io_sim_cache.ss_85c_slow.hsd
diff --git a/part_2/ex5/db/ex5.db_info b/part_2/ex5/db/ex5.db_info
new file mode 100755
index 0000000..83604aa
--- /dev/null
+++ b/part_2/ex5/db/ex5.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Version_Index = 419480576

+Creation_Time = Tue Nov 22 09:10:44 2016

diff --git a/part_2/ex5/db/ex5.fit.qmsg b/part_2/ex5/db/ex5.fit.qmsg
new file mode 100755
index 0000000..a42b5fb
--- /dev/null
+++ b/part_2/ex5/db/ex5.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479806830418 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479806830418 ""}

+{ "Info" "IMPP_MPP_USER_DEVICE" "ex5 5CGXFC7C7F23C8 " "Selected device 5CGXFC7C7F23C8 for design \"ex5\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479806830529 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1479806830770 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1479806830770 ""}

+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479806832299 ""}

+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1479806833191 ""}

+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479806834602 ""}

+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "10 10 " "No exact pin location assignment(s) for 10 pins of 10 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1479806835217 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479806850286 ""}

+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clock~inputCLKENA0 8 global CLKCTRL_G10 " "clock~inputCLKENA0 with 8 fanout uses global clock CLKCTRL_G10" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479806850601 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479806850601 ""}

+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806850602 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479806850862 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479806850870 ""}

+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479806850871 ""}

+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479806850872 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479806850880 ""}

+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479806850881 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex5.sdc " "Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1479806854662 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1479806854669 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479806854672 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479806854672 ""}

+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1479806854673 ""}

+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479806854690 ""}

+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479806854690 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479806854690 ""}

+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:21 " "Fitter preparation operations ending: elapsed time is 00:00:21" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806855238 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479806869358 ""}

+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479806870144 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:05 " "Fitter placement preparation operations ending: elapsed time is 00:00:05" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806874879 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479806877557 ""}

+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479806881279 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806881280 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479806883680 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y35 X89_Y45 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45" {  } { { "loc" "" { Generic "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45"} { { 12 { 0 ""} 78 35 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479806897785 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479806897785 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479806898158 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479806898158 ""}

+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806898163 ""}

+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.42 " "Total time spent on timing analysis during the Fitter is 0.42 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479806902813 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479806902906 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479806903630 ""}

+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479806903630 ""}

+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479806905010 ""}

+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:07 " "Fitter post-fit operations ending: elapsed time is 00:00:07" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479806909506 ""}

+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg " "Generated suppressed messages file C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479806910231 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2264 " "Peak virtual memory: 2264 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:28:31 2016 " "Processing ended: Tue Nov 22 09:28:31 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:28 " "Elapsed time: 00:01:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:40 " "Total CPU time (on all processors): 00:01:40" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806911666 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479806911666 ""}

diff --git a/part_2/ex5/db/ex5.hier_info b/part_2/ex5/db/ex5.hier_info
new file mode 100755
index 0000000..8d49b87
--- /dev/null
+++ b/part_2/ex5/db/ex5.hier_info
@@ -0,0 +1,27 @@
+|ex5

+clock => count[0]~reg0.CLK

+clock => count[1]~reg0.CLK

+clock => count[2]~reg0.CLK

+clock => count[3]~reg0.CLK

+clock => count[4]~reg0.CLK

+clock => count[5]~reg0.CLK

+clock => count[6]~reg0.CLK

+clock => count[7]~reg0.CLK

+enable => count[0]~reg0.ENA

+enable => count[1]~reg0.ENA

+enable => count[2]~reg0.ENA

+enable => count[3]~reg0.ENA

+enable => count[4]~reg0.ENA

+enable => count[5]~reg0.ENA

+enable => count[6]~reg0.ENA

+enable => count[7]~reg0.ENA

+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE

+

+

diff --git a/part_2/ex5/db/ex5.hif b/part_2/ex5/db/ex5.hif
new file mode 100755
index 0000000..a9b1b07
--- /dev/null
+++ b/part_2/ex5/db/ex5.hif
diff --git a/part_2/ex5/db/ex5.lpc.html b/part_2/ex5/db/ex5.lpc.html
new file mode 100755
index 0000000..7d68592
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>

+<TR  bgcolor="#C0C0C0">

+<TH>Hierarchy</TH>

+<TH>Input</TH>

+<TH>Constant Input</TH>

+<TH>Unused Input</TH>

+<TH>Floating Input</TH>

+<TH>Output</TH>

+<TH>Constant Output</TH>

+<TH>Unused Output</TH>

+<TH>Floating Output</TH>

+<TH>Bidir</TH>

+<TH>Constant Bidir</TH>

+<TH>Unused Bidir</TH>

+<TH>Input only Bidir</TH>

+<TH>Output only Bidir</TH>

+</TR>

+</TABLE>

diff --git a/part_2/ex5/db/ex5.lpc.rdb b/part_2/ex5/db/ex5.lpc.rdb
new file mode 100755
index 0000000..c179f4d
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.rdb
diff --git a/part_2/ex5/db/ex5.lpc.txt b/part_2/ex5/db/ex5.lpc.txt
new file mode 100755
index 0000000..dbfe520
--- /dev/null
+++ b/part_2/ex5/db/ex5.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Legal Partition Candidates                                                                                                                                                                                     ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;

++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

diff --git a/part_2/ex5/db/ex5.map.ammdb b/part_2/ex5/db/ex5.map.ammdb
new file mode 100755
index 0000000..a4afc79
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.ammdb
diff --git a/part_2/ex5/db/ex5.map.bpm b/part_2/ex5/db/ex5.map.bpm
new file mode 100755
index 0000000..3592b20
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.bpm
diff --git a/part_2/ex5/db/ex5.map.cdb b/part_2/ex5/db/ex5.map.cdb
new file mode 100755
index 0000000..256c526
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.cdb
diff --git a/part_2/ex5/db/ex5.map.hdb b/part_2/ex5/db/ex5.map.hdb
new file mode 100755
index 0000000..3d0d6f2
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.hdb
diff --git a/part_2/ex5/db/ex5.map.kpt b/part_2/ex5/db/ex5.map.kpt
new file mode 100755
index 0000000..6a235ab
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.kpt
diff --git a/part_2/ex5/db/ex5.map.logdb b/part_2/ex5/db/ex5.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/db/ex5.map.qmsg b/part_2/ex5/db/ex5.map.qmsg
new file mode 100755
index 0000000..342e059
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806798609 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806798617 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:26:38 2016 " "Processing started: Tue Nov 22 09:26:38 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806798617 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806798617 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806798617 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479806799115 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479806799115 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog files/counter_8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog files/counter_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_8 " "Found entity 1: counter_8" {  } { { "verilog files/counter_8.v" "" { Text "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/counter_8.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479806815578 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806815578 ""}

+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog files/ex5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog files/ex5.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex5 " "Found entity 1: ex5" {  } { { "verilog files/ex5.v" "" { Text "C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479806815580 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806815580 ""}

+{ "Info" "ISGN_START_ELABORATION_TOP" "ex5 " "Elaborating entity \"ex5\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479806815642 ""}

+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479806818460 ""}

+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479806820436 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479806820436 ""}

+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479806821948 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479806821948 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479806821948 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479806821948 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "698 " "Peak virtual memory: 698 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:27:02 2016 " "Processing ended: Tue Nov 22 09:27:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Elapsed time: 00:00:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806822084 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479806822084 ""}

diff --git a/part_2/ex5/db/ex5.map.rdb b/part_2/ex5/db/ex5.map.rdb
new file mode 100755
index 0000000..d90a0c1
--- /dev/null
+++ b/part_2/ex5/db/ex5.map.rdb
diff --git a/part_2/ex5/db/ex5.map_bb.cdb b/part_2/ex5/db/ex5.map_bb.cdb
new file mode 100755
index 0000000..ebced3a
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.cdb
diff --git a/part_2/ex5/db/ex5.map_bb.hdb b/part_2/ex5/db/ex5.map_bb.hdb
new file mode 100755
index 0000000..bb6499e
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.hdb
diff --git a/part_2/ex5/db/ex5.map_bb.logdb b/part_2/ex5/db/ex5.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/db/ex5.map_bb.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/db/ex5.pre_map.hdb b/part_2/ex5/db/ex5.pre_map.hdb
new file mode 100755
index 0000000..fecb803
--- /dev/null
+++ b/part_2/ex5/db/ex5.pre_map.hdb
diff --git a/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb b/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..5cd114f
--- /dev/null
+++ b/part_2/ex5/db/ex5.root_partition.map.reg_db.cdb
diff --git a/part_2/ex5/db/ex5.routing.rdb b/part_2/ex5/db/ex5.routing.rdb
new file mode 100755
index 0000000..34ca13b
--- /dev/null
+++ b/part_2/ex5/db/ex5.routing.rdb
diff --git a/part_2/ex5/db/ex5.rtlv.hdb b/part_2/ex5/db/ex5.rtlv.hdb
new file mode 100755
index 0000000..a8a9b60
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv.hdb
diff --git a/part_2/ex5/db/ex5.rtlv_sg.cdb b/part_2/ex5/db/ex5.rtlv_sg.cdb
new file mode 100755
index 0000000..6214e3f
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv_sg.cdb
diff --git a/part_2/ex5/db/ex5.rtlv_sg_swap.cdb b/part_2/ex5/db/ex5.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..0be030c
--- /dev/null
+++ b/part_2/ex5/db/ex5.rtlv_sg_swap.cdb
diff --git a/part_2/ex5/db/ex5.sld_design_entry.sci b/part_2/ex5/db/ex5.sld_design_entry.sci
new file mode 100755
index 0000000..1bd84ed
--- /dev/null
+++ b/part_2/ex5/db/ex5.sld_design_entry.sci
diff --git a/part_2/ex5/db/ex5.sld_design_entry_dsc.sci b/part_2/ex5/db/ex5.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..1bd84ed
--- /dev/null
+++ b/part_2/ex5/db/ex5.sld_design_entry_dsc.sci
diff --git a/part_2/ex5/db/ex5.smart_action.txt b/part_2/ex5/db/ex5.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_2/ex5/db/ex5.smart_action.txt
@@ -0,0 +1 @@
+DONE

diff --git a/part_2/ex5/db/ex5.sta.qmsg b/part_2/ex5/db/ex5.sta.qmsg
new file mode 100755
index 0000000..b8bb557
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta.qmsg
@@ -0,0 +1,21 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806941525 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806941531 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:29:00 2016 " "Processing started: Tue Nov 22 09:29:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806941531 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806941531 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex5 -c ex5 " "Command: quartus_sta ex5 -c ex5" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806941531 ""}

+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806941769 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942710 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942710 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942796 ""}

+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806942796 ""}

+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex5.sdc " "Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944125 ""}

+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944125 ""}

+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clock clock " "create_clock -period 1.000 -name clock clock" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1479806944126 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944126 ""}

+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944128 ""}

+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944128 ""}

+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806944143 ""}

+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479806944169 ""}

+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1479806944219 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944219 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.444 " "Worst-case setup slack is -1.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.444              -8.970 clock  " "   -1.444              -8.970 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944241 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944241 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.487 " "Worst-case hold slack is 0.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.487               0.000 clock  " "    0.487               0.000 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944250 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944250 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944259 ""}

+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479806944268 ""}

+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.724 " "Worst-case minimum pulse width slack is -0.724" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724              -8.917 clock  " "   -0.724              -8.917 clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479806944284 ""}  } {
\ No newline at end of file
diff --git a/part_2/ex5/db/ex5.sta.rdb b/part_2/ex5/db/ex5.sta.rdb
new file mode 100755
index 0000000..2a68d94
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta.rdb
diff --git a/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb b/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..29b23ee
--- /dev/null
+++ b/part_2/ex5/db/ex5.sta_cmp.8_H7_slow_1100mv_85c.tdb
diff --git a/part_2/ex5/db/ex5.tis_db_list.ddb b/part_2/ex5/db/ex5.tis_db_list.ddb
new file mode 100755
index 0000000..dec6bed
--- /dev/null
+++ b/part_2/ex5/db/ex5.tis_db_list.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb b/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..06cd923
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb b/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb
new file mode 100755
index 0000000..0c58cfe
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.fastest_slow_1100mv_85c.ddb
diff --git a/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb b/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..6bedbe6
--- /dev/null
+++ b/part_2/ex5/db/ex5.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex5/db/ex5.tmw_info b/part_2/ex5/db/ex5.tmw_info
new file mode 100755
index 0000000..fcbb322
--- /dev/null
+++ b/part_2/ex5/db/ex5.tmw_info
@@ -0,0 +1,4 @@
+start_analysis_synthesis:s:00:00:24-start_full_compilation

+start_analysis_elaboration:s-start_full_compilation

+start_fitter:s:00:01:30-start_full_compilation

+start_assembler:s:00:00:27-start_full_compilation

diff --git a/part_2/ex5/db/ex5.vpr.ammdb b/part_2/ex5/db/ex5.vpr.ammdb
new file mode 100755
index 0000000..8dd3884
--- /dev/null
+++ b/part_2/ex5/db/ex5.vpr.ammdb
diff --git a/part_2/ex5/db/ex5_partition_pins.json b/part_2/ex5/db/ex5_partition_pins.json
new file mode 100755
index 0000000..1c05513
--- /dev/null
+++ b/part_2/ex5/db/ex5_partition_pins.json
@@ -0,0 +1,49 @@
+{

+	"partitions" : [

+		{

+			"name" : "Top",

+			"pins" : [

+				{

+					"name" : "count[0]",

+					"strict" : false

+				},

+				{

+					"name" : "count[1]",

+					"strict" : false

+				},

+				{

+					"name" : "count[2]",

+					"strict" : false

+				},

+				{

+					"name" : "count[3]",

+					"strict" : false

+				},

+				{

+					"name" : "count[4]",

+					"strict" : false

+				},

+				{

+					"name" : "count[5]",

+					"strict" : false

+				},

+				{

+					"name" : "count[6]",

+					"strict" : false

+				},

+				{

+					"name" : "count[7]",

+					"strict" : false

+				},

+				{

+					"name" : "clock",

+					"strict" : false

+				},

+				{

+					"name" : "enable",

+					"strict" : false

+				}

+			]

+		}

+	]

+}
\ No newline at end of file
diff --git a/part_2/ex5/db/prev_cmp_ex5.qmsg b/part_2/ex5/db/prev_cmp_ex5.qmsg
new file mode 100755
index 0000000..d39cdf7
--- /dev/null
+++ b/part_2/ex5/db/prev_cmp_ex5.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479806631495 ""}

+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 09:23:51 2016 " "Processing started: Tue Nov 22 09:23:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5 --analyze_file=\"C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479806631496 ""}

+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479806632107 ""}

+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "652 " "Peak virtual memory: 652 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 09:24:08 2016 " "Processing ended: Tue Nov 22 09:24:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479806648609 ""}

diff --git a/part_2/ex5/ex5.qpf b/part_2/ex5/ex5.qpf
new file mode 100755
index 0000000..ffc3e43
--- /dev/null
+++ b/part_2/ex5/ex5.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 2016  Intel Corporation. All rights reserved.

+# Your use of Intel Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Intel Program License 

+# Subscription Agreement, the Intel Quartus Prime License Agreement,

+# the Intel MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Intel and sold by Intel or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+# Date created = 09:10:34  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "16.1"

+DATE = "09:10:34  November 22, 2016"

+

+# Revisions

+

+PROJECT_REVISION = "ex5"

diff --git a/part_2/ex5/ex5.qsf b/part_2/ex5/ex5.qsf
new file mode 100755
index 0000000..c70ecfe
--- /dev/null
+++ b/part_2/ex5/ex5.qsf
@@ -0,0 +1,53 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 2016  Intel Corporation. All rights reserved.

+# Your use of Intel Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Intel Program License 

+# Subscription Agreement, the Intel Quartus Prime License Agreement,

+# the Intel MegaCore Function License Agreement, or other 

+# applicable license agreement, including, without limitation, 

+# that your use is for the sole purpose of programming logic 

+# devices manufactured by Intel and sold by Intel or its 

+# authorized distributors.  Please refer to the applicable 

+# agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus Prime

+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+# Date created = 09:10:35  November 22, 2016

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		ex5_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus Prime software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone V"

+set_global_assignment -name DEVICE 5CGXFC7C7F23C8

+set_global_assignment -name TOP_LEVEL_ENTITY ex5

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:10:35  NOVEMBER 22, 2016"

+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"

+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

+set_global_assignment -name VERILOG_FILE "verilog files/counter_8.v"

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_global_assignment -name VERILOG_FILE "verilog files/ex5.v"

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/part_2/ex5/ex5.qws b/part_2/ex5/ex5.qws
new file mode 100755
index 0000000..b27ab95
--- /dev/null
+++ b/part_2/ex5/ex5.qws
diff --git a/part_2/ex5/ex5_nativelink_simulation.rpt b/part_2/ex5/ex5_nativelink_simulation.rpt
new file mode 100755
index 0000000..833b429
--- /dev/null
+++ b/part_2/ex5/ex5_nativelink_simulation.rpt
@@ -0,0 +1,21 @@
+Info: Start Nativelink Simulation process

+Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

+

+========= EDA Simulation Settings =====================

+

+Sim Mode              :  RTL

+Family                :  cyclonev

+Quartus root          :  c:/altera/16.0/quartus/bin64/

+Quartus sim root      :  c:/altera/16.0/quartus/eda/sim_lib

+Simulation Tool       :  modelsim-altera

+Simulation Language   :  verilog

+Simulation Mode       :  GUI

+Sim Output File       :  

+Sim SDF file          :  

+Sim dir               :  simulation\modelsim

+

+=======================================================

+

+Info: Starting NativeLink simulation with ModelSim-Altera software

+Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl

+Info: Spawning ModelSim-Altera Simulation software 

diff --git a/part_2/ex5/incremental_db/README b/part_2/ex5/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_2/ex5/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.

+

+The compiled_partitions sub-folder contains previous compilation results for each partition.

+As long as this folder is preserved, incremental compilation results from earlier compiles

+can be re-used.  To perform a clean compilation from source files for all partitions, both

+the db and incremental_db folder should be removed.

+

+The imported_partitions sub-folder contains the last imported QXP for each imported partition.

+As long as this folder is preserved, imported partitions will be automatically re-imported

+when the db or incremental_db/compiled_partitions folders are removed.

+

diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.db_info b/part_2/ex5/incremental_db/compiled_partitions/ex5.db_info
new file mode 100755
index 0000000..d20478d
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Version_Index = 419480576

+Creation_Time = Tue Nov 22 09:26:56 2016

diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.ammdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.ammdb
new file mode 100755
index 0000000..b275595
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.ammdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.cdb
new file mode 100755
index 0000000..3d7e429
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.dfp b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.dfp
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..1e1fcec
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..3645c01
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.sig b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hdb
new file mode 100755
index 0000000..89aab09
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.logdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1

diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.rcfdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..521454b
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.cmp.rcfdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.cdb
new file mode 100755
index 0000000..80c6973
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.dpi b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.dpi
new file mode 100755
index 0000000..6955961
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.dpi
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..46fb310
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hb_info b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..a4a4882
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.sig b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hdb
new file mode 100755
index 0000000..7dfc1cd
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.kpt b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.kpt
new file mode 100755
index 0000000..40bb8bb
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.kpt
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olf.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olf.cdb
new file mode 100755
index 0000000..a6a7b4a
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olf.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olm.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olm.cdb
new file mode 100755
index 0000000..c6265be
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.olm.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.oln.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.oln.cdb
new file mode 100755
index 0000000..a4c2895
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.oln.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.opi b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.opi
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orf.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orf.cdb
new file mode 100755
index 0000000..a6a7b4a
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orf.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orm.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orm.cdb
new file mode 100755
index 0000000..cd4104f
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orm.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orn.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orn.cdb
new file mode 100755
index 0000000..0494107
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.root_partition.map.orn.cdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.rrp.hdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrp.hdb
new file mode 100755
index 0000000..45ff64f
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrp.hdb
diff --git a/part_2/ex5/incremental_db/compiled_partitions/ex5.rrs.cdb b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrs.cdb
new file mode 100755
index 0000000..27a2c00
--- /dev/null
+++ b/part_2/ex5/incremental_db/compiled_partitions/ex5.rrs.cdb
diff --git a/part_2/ex5/output_files/ex5.asm.rpt b/part_2/ex5/output_files/ex5.asm.rpt
new file mode 100755
index 0000000..c6bb855
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex5

+Tue Nov 22 09:28:58 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Assembler Summary

+  3. Assembler Settings

+  4. Assembler Generated Files

+  5. Assembler Device Options: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.sof

+  6. Assembler Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++---------------------------------------------------------------+

+; Assembler Summary                                             ;

++-----------------------+---------------------------------------+

+; Assembler Status      ; Successful - Tue Nov 22 09:28:58 2016 ;

+; Revision Name         ; ex5                                   ;

+; Top-level Entity Name ; ex5                                   ;

+; Family                ; Cyclone V                             ;

+; Device                ; 5CGXFC7C7F23C8                        ;

++-----------------------+---------------------------------------+

+

+

++----------------------------------+

+; Assembler Settings               ;

++--------+---------+---------------+

+; Option ; Setting ; Default Value ;

++--------+---------+---------------+

+

+

++------------------------------------------------------------------------------------------------------+

+; Assembler Generated Files                                                                            ;

++------------------------------------------------------------------------------------------------------+

+; File Name                                                                                            ;

++------------------------------------------------------------------------------------------------------+

+; C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.sof ;

++------------------------------------------------------------------------------------------------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------------+

+; Assembler Device Options: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.sof ;

++----------------+---------------------------------------------------------------------------------------------------------------+

+; Option         ; Setting                                                                                                       ;

++----------------+---------------------------------------------------------------------------------------------------------------+

+; Device         ; 5CGXFC7C7F23C8                                                                                                ;

+; JTAG usercode  ; 0x00EC478F                                                                                                    ;

+; Checksum       ; 0x00EC478F                                                                                                    ;

++----------------+---------------------------------------------------------------------------------------------------------------+

+

+

++--------------------+

+; Assembler Messages ;

++--------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Assembler

+    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+    Info: Processing started: Tue Nov 22 09:28:35 2016

+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (115030): Assembler is generating device programming files

+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 708 megabytes

+    Info: Processing ended: Tue Nov 22 09:28:58 2016

+    Info: Elapsed time: 00:00:23

+    Info: Total CPU time (on all processors): 00:00:15

+

+

diff --git a/part_2/ex5/output_files/ex5.done b/part_2/ex5/output_files/ex5.done
new file mode 100755
index 0000000..da27f96
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.done
@@ -0,0 +1 @@
+Tue Nov 22 09:24:09 2016

diff --git a/part_2/ex5/output_files/ex5.fit.rpt b/part_2/ex5/output_files/ex5.fit.rpt
new file mode 100755
index 0000000..63955aa
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.fit.rpt
@@ -0,0 +1,1228 @@
+Fitter report for ex5

+Tue Nov 22 09:28:30 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Fitter Summary

+  3. Fitter Settings

+  4. Parallel Compilation

+  5. Fitter Netlist Optimizations

+  6. Incremental Compilation Preservation Summary

+  7. Incremental Compilation Partition Settings

+  8. Incremental Compilation Placement Preservation

+  9. Pin-Out File

+ 10. Fitter Resource Usage Summary

+ 11. Fitter Partition Statistics

+ 12. Input Pins

+ 13. Output Pins

+ 14. I/O Bank Usage

+ 15. All Package Pins

+ 16. I/O Assignment Warnings

+ 17. Fitter Resource Utilization by Entity

+ 18. Delay Chain Summary

+ 19. Pad To Core Delay Chain Fanout

+ 20. Control Signals

+ 21. Global & Other Fast Signals

+ 22. Routing Usage Summary

+ 23. I/O Rules Summary

+ 24. I/O Rules Details

+ 25. I/O Rules Matrix

+ 26. Fitter Device Options

+ 27. Operating Settings and Conditions

+ 28. Estimated Delay Added for Hold Timing Summary

+ 29. Estimated Delay Added for Hold Timing Details

+ 30. Fitter Messages

+ 31. Fitter Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-------------------------------------------------------------------------------+

+; Fitter Summary                                                                ;

++---------------------------------+---------------------------------------------+

+; Fitter Status                   ; Successful - Tue Nov 22 09:28:30 2016       ;

+; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;

+; Revision Name                   ; ex5                                         ;

+; Top-level Entity Name           ; ex5                                         ;

+; Family                          ; Cyclone V                                   ;

+; Device                          ; 5CGXFC7C7F23C8                              ;

+; Timing Models                   ; Final                                       ;

+; Logic utilization (in ALMs)     ; 5 / 56,480 ( < 1 % )                        ;

+; Total registers                 ; 8                                           ;

+; Total pins                      ; 10 / 268 ( 4 % )                            ;

+; Total virtual pins              ; 0                                           ;

+; Total block memory bits         ; 0 / 7,024,640 ( 0 % )                       ;

+; Total RAM Blocks                ; 0 / 686 ( 0 % )                             ;

+; Total DSP Blocks                ; 0 / 156 ( 0 % )                             ;

+; Total HSSI RX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % )                               ;

+; Total HSSI TX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA TX Serializers   ; 0 / 6 ( 0 % )                               ;

+; Total PLLs                      ; 0 / 13 ( 0 % )                              ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                               ;

++---------------------------------+---------------------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Settings                                                                                                                                            ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Option                                                                     ; Setting                               ; Default Value                         ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+; Device                                                                     ; 5CGXFC7C7F23C8                        ;                                       ;

+; Use smart compilation                                                      ; Off                                   ; Off                                   ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;

+; Enable compact report table                                                ; Off                                   ; Off                                   ;

+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;

+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;

+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;

+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;

+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;

+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;

+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;

+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;

+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;

+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;

+; SSN Optimization                                                           ; Off                                   ; Off                                   ;

+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;

+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;

+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;

+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;

+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;

+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;

+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;

+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;

+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;

+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;

+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;

+; Auto Delay Chains                                                          ; On                                    ; On                                    ;

+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;

+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;

+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;

+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;

+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;

+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;

+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;

+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;

+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;

+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;

+; Auto Global Clock                                                          ; On                                    ; On                                    ;

+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;

+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;

+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;

+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;

+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;

+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;

+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;

+; Clamping Diode                                                             ; Off                                   ; Off                                   ;

+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;

+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;

++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 4           ;

+; Maximum allowed            ; 2           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 2           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.3%      ;

++----------------------------+-------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Netlist Optimizations                                                                                                                                     ;

++--------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+

+; Node               ; Action  ; Operation ; Reason                     ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;

++--------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+

+; clock~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ;           ;                ;                  ;                  ;                       ;

++--------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+

+

+

++-------------------------------------------------------------------------------------------------+

+; Incremental Compilation Preservation Summary                                                    ;

++---------------------+-------------------+----------------------------+--------------------------+

+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;

++---------------------+-------------------+----------------------------+--------------------------+

+; Placement (by node) ;                   ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 38 ) ; 0.00 % ( 0 / 38 )          ; 0.00 % ( 0 / 38 )        ;

+;     -- Achieved     ; 0.00 % ( 0 / 38 ) ; 0.00 % ( 0 / 38 )          ; 0.00 % ( 0 / 38 )        ;

+;                     ;                   ;                            ;                          ;

+; Routing (by net)    ;                   ;                            ;                          ;

+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;

++---------------------+-------------------+----------------------------+--------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Partition Settings                                                                                                                                             ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;

+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;

++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+

+

+

++------------------------------------------------------------------------------------------------------------------------------------+

+; Incremental Compilation Placement Preservation                                                                                     ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+; Top                            ; 0.00 % ( 0 / 38 )     ; N/A                     ; Source File       ; N/A                 ;       ;

+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;

++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+

+

+

++--------------+

+; Pin-Out File ;

++--------------+

+The pin-out file can be found in C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.pin.

+

+

++------------------------------------------------------------------------------------------+

+; Fitter Resource Usage Summary                                                            ;

++-------------------------------------------------------------+--------------------+-------+

+; Resource                                                    ; Usage              ; %     ;

++-------------------------------------------------------------+--------------------+-------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 5 / 56,480         ; < 1 % ;

+; ALMs needed [=A-B+C]                                        ; 5                  ;       ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 5 / 56,480         ; < 1 % ;

+;         [a] ALMs used for LUT logic and registers           ; 4                  ;       ;

+;         [b] ALMs used for LUT logic                         ; 1                  ;       ;

+;         [c] ALMs used for registers                         ; 0                  ;       ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 56,480         ; 0 %   ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 56,480         ; 0 %   ;

+;         [a] Due to location constrained logic               ; 0                  ;       ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;

+;         [c] Due to LAB input limits                         ; 0                  ;       ;

+;         [d] Due to virtual I/Os                             ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Difficulty packing design                                   ; Low                ;       ;

+;                                                             ;                    ;       ;

+; Total LABs:  partially or completely used                   ; 2 / 5,648          ; < 1 % ;

+;     -- Logic LABs                                           ; 2                  ;       ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Combinational ALUT usage for logic                          ; 9                  ;       ;

+;     -- 7 input functions                                    ; 0                  ;       ;

+;     -- 6 input functions                                    ; 0                  ;       ;

+;     -- 5 input functions                                    ; 0                  ;       ;

+;     -- 4 input functions                                    ; 0                  ;       ;

+;     -- <=3 input functions                                  ; 9                  ;       ;

+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Dedicated logic registers                                   ; 8                  ;       ;

+;     -- By type:                                             ;                    ;       ;

+;         -- Primary logic registers                          ; 8 / 112,960        ; < 1 % ;

+;         -- Secondary logic registers                        ; 0 / 112,960        ; 0 %   ;

+;     -- By function:                                         ;                    ;       ;

+;         -- Design implementation registers                  ; 8                  ;       ;

+;         -- Routing optimization registers                   ; 0                  ;       ;

+;                                                             ;                    ;       ;

+; Virtual pins                                                ; 0                  ;       ;

+; I/O pins                                                    ; 10 / 268           ; 4 %   ;

+;     -- Clock pins                                           ; 1 / 11             ; 9 %   ;

+;     -- Dedicated input pins                                 ; 0 / 23             ; 0 %   ;

+;                                                             ;                    ;       ;

+; M10K blocks                                                 ; 0 / 686            ; 0 %   ;

+; Total MLAB memory bits                                      ; 0                  ;       ;

+; Total block memory bits                                     ; 0 / 7,024,640      ; 0 %   ;

+; Total block memory implementation bits                      ; 0 / 7,024,640      ; 0 %   ;

+;                                                             ;                    ;       ;

+; Total DSP Blocks                                            ; 0 / 156            ; 0 %   ;

+;                                                             ;                    ;       ;

+; Fractional PLLs                                             ; 0 / 7              ; 0 %   ;

+; Global signals                                              ; 1                  ;       ;

+;     -- Global clocks                                        ; 1 / 16             ; 6 %   ;

+;     -- Quadrant clocks                                      ; 0 / 88             ; 0 %   ;

+;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;

+; SERDES Transmitters                                         ; 0 / 120            ; 0 %   ;

+; SERDES Receivers                                            ; 0 / 120            ; 0 %   ;

+; JTAGs                                                       ; 0 / 1              ; 0 %   ;

+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;

+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;

+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;

+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;

+; Hard IPs                                                    ; 0 / 1              ; 0 %   ;

+; Standard RX PCSs                                            ; 0 / 6              ; 0 %   ;

+; HSSI PMA RX Deserializers                                   ; 0 / 6              ; 0 %   ;

+; Standard TX PCSs                                            ; 0 / 6              ; 0 %   ;

+; HSSI PMA TX Serializers                                     ; 0 / 6              ; 0 %   ;

+; Channel PLLs                                                ; 0 / 6              ; 0 %   ;

+; Impedance control blocks                                    ; 0 / 3              ; 0 %   ;

+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;

+; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.0% ;       ;

+; Peak interconnect usage (total/H/V)                         ; 0.0% / 0.0% / 0.1% ;       ;

+; Maximum fan-out                                             ; 8                  ;       ;

+; Highest non-global fan-out                                  ; 8                  ;       ;

+; Total fan-out                                               ; 58                 ;       ;

+; Average fan-out                                             ; 1.53               ;       ;

++-------------------------------------------------------------+--------------------+-------+

+

+

++---------------------------------------------------------------------------------------------------------------------+

+; Fitter Partition Statistics                                                                                         ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Statistic                                                   ; Top                  ; hard_block:auto_generated_inst ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+; Logic utilization (ALMs needed / total ALMs on device)      ; 5 / 56480 ( < 1 % )  ; 0 / 56480 ( 0 % )              ;

+; ALMs needed [=A-B+C]                                        ; 5                    ; 0                              ;

+;     [A] ALMs used in final placement [=a+b+c+d]             ; 5 / 56480 ( < 1 % )  ; 0 / 56480 ( 0 % )              ;

+;         [a] ALMs used for LUT logic and registers           ; 4                    ; 0                              ;

+;         [b] ALMs used for LUT logic                         ; 1                    ; 0                              ;

+;         [c] ALMs used for registers                         ; 0                    ; 0                              ;

+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                    ; 0                              ;

+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 56480 ( 0 % )    ; 0 / 56480 ( 0 % )              ;

+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 56480 ( 0 % )    ; 0 / 56480 ( 0 % )              ;

+;         [a] Due to location constrained logic               ; 0                    ; 0                              ;

+;         [b] Due to LAB-wide signal conflicts                ; 0                    ; 0                              ;

+;         [c] Due to LAB input limits                         ; 0                    ; 0                              ;

+;         [d] Due to virtual I/Os                             ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Difficulty packing design                                   ; Low                  ; Low                            ;

+;                                                             ;                      ;                                ;

+; Total LABs:  partially or completely used                   ; 2 / 5648 ( < 1 % )   ; 0 / 5648 ( 0 % )               ;

+;     -- Logic LABs                                           ; 2                    ; 0                              ;

+;     -- Memory LABs (up to half of total LABs)               ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Combinational ALUT usage for logic                          ; 9                    ; 0                              ;

+;     -- 7 input functions                                    ; 0                    ; 0                              ;

+;     -- 6 input functions                                    ; 0                    ; 0                              ;

+;     -- 5 input functions                                    ; 0                    ; 0                              ;

+;     -- 4 input functions                                    ; 0                    ; 0                              ;

+;     -- <=3 input functions                                  ; 9                    ; 0                              ;

+; Combinational ALUT usage for route-throughs                 ; 0                    ; 0                              ;

+; Memory ALUT usage                                           ; 0                    ; 0                              ;

+;     -- 64-address deep                                      ; 0                    ; 0                              ;

+;     -- 32-address deep                                      ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Dedicated logic registers                                   ; 0                    ; 0                              ;

+;     -- By type:                                             ;                      ;                                ;

+;         -- Primary logic registers                          ; 8 / 112960 ( < 1 % ) ; 0 / 112960 ( 0 % )             ;

+;         -- Secondary logic registers                        ; 0 / 112960 ( 0 % )   ; 0 / 112960 ( 0 % )             ;

+;     -- By function:                                         ;                      ;                                ;

+;         -- Design implementation registers                  ; 8                    ; 0                              ;

+;         -- Routing optimization registers                   ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+;                                                             ;                      ;                                ;

+; Virtual pins                                                ; 0                    ; 0                              ;

+; I/O pins                                                    ; 10                   ; 0                              ;

+; I/O registers                                               ; 0                    ; 0                              ;

+; Total block memory bits                                     ; 0                    ; 0                              ;

+; Total block memory implementation bits                      ; 0                    ; 0                              ;

+; Clock enable block                                          ; 1 / 122 ( < 1 % )    ; 0 / 122 ( 0 % )                ;

+;                                                             ;                      ;                                ;

+; Connections                                                 ;                      ;                                ;

+;     -- Input Connections                                    ; 0                    ; 0                              ;

+;     -- Registered Input Connections                         ; 0                    ; 0                              ;

+;     -- Output Connections                                   ; 0                    ; 0                              ;

+;     -- Registered Output Connections                        ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Internal Connections                                        ;                      ;                                ;

+;     -- Total Connections                                    ; 58                   ; 0                              ;

+;     -- Registered Connections                               ; 17                   ; 0                              ;

+;                                                             ;                      ;                                ;

+; External Connections                                        ;                      ;                                ;

+;     -- Top                                                  ; 0                    ; 0                              ;

+;     -- hard_block:auto_generated_inst                       ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Partition Interface                                         ;                      ;                                ;

+;     -- Input Ports                                          ; 2                    ; 0                              ;

+;     -- Output Ports                                         ; 8                    ; 0                              ;

+;     -- Bidir Ports                                          ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Registered Ports                                            ;                      ;                                ;

+;     -- Registered Input Ports                               ; 0                    ; 0                              ;

+;     -- Registered Output Ports                              ; 0                    ; 0                              ;

+;                                                             ;                      ;                                ;

+; Port Connectivity                                           ;                      ;                                ;

+;     -- Input Ports driven by GND                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by GND                           ; 0                    ; 0                              ;

+;     -- Input Ports driven by VCC                            ; 0                    ; 0                              ;

+;     -- Output Ports driven by VCC                           ; 0                    ; 0                              ;

+;     -- Input Ports with no Source                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Source                          ; 0                    ; 0                              ;

+;     -- Input Ports with no Fanout                           ; 0                    ; 0                              ;

+;     -- Output Ports with no Fanout                          ; 0                    ; 0                              ;

++-------------------------------------------------------------+----------------------+--------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Input Pins                                                                                                                                                                                                                                                                            ;

++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;

++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+; clock  ; M16   ; 5B       ; 89           ; 35           ; 60           ; 8                     ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;

+; enable ; N16   ; 5B       ; 89           ; 35           ; 43           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;

++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;

++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;

++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+; count[0] ; M20   ; 5B       ; 89           ; 37           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[1] ; N21   ; 5B       ; 89           ; 35           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[2] ; N19   ; 5B       ; 89           ; 36           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[3] ; L22   ; 5B       ; 89           ; 36           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[4] ; N20   ; 5B       ; 89           ; 35           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[5] ; M18   ; 5B       ; 89           ; 36           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[6] ; M22   ; 5B       ; 89           ; 36           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

+; count[7] ; L18   ; 5B       ; 89           ; 38           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;

++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+

+

+

++----------------------------------------------------------------------------+

+; I/O Bank Usage                                                             ;

++----------+------------------+---------------+--------------+---------------+

+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;

++----------+------------------+---------------+--------------+---------------+

+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;

+; B1L      ; 0 / 14 ( 0 % )   ; --            ; --           ; --            ;

+; B0L      ; 0 / 14 ( 0 % )   ; --            ; --           ; --            ;

+; 3A       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 3B       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 4A       ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 5A       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 5B       ; 10 / 16 ( 63 % ) ; 2.5V          ; --           ; 2.5V          ;

+; 7A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

+; 8A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;

++----------+------------------+---------------+--------------+---------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; All Package Pins                                                                                                                                                            ;

++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;

++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+; A1       ;            ;          ; RREF                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A2       ; 538        ; 9A       ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A3       ;            ; --       ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;

+; A4       ; 540        ; 9A       ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; A5       ; 466        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A6       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A7       ; 475        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A8       ; 473        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A9       ; 464        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A10      ; 462        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A12      ; 444        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A13      ; 432        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A14      ; 420        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A15      ; 418        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A16      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; A17      ; 403        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A18      ; 401        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A19      ; 404        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A20      ; 402        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; A21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; A22      ; 396        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA1      ; 39         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA2      ; 38         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA3      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA4      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA5      ; 47         ; 3A       ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AA6      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA7      ; 105        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA8      ; 108        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA9      ; 115        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA10     ; 113        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA11     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AA12     ; 131        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA13     ; 139        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA14     ; 137        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA15     ; 142        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA16     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA17     ; 153        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA18     ; 155        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA19     ; 156        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA20     ; 158        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AA21     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; AA22     ; 163        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB1      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB2      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB3      ; 49         ; 3A       ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB4      ; 51         ; 3A       ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; AB5      ; 102        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB6      ; 100        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB7      ; 107        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB8      ; 110        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB9      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB10     ; 124        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB11     ; 126        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB12     ; 134        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB13     ; 132        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB14     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB15     ; 140        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB16     ;            ; 4A       ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB17     ; 145        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB18     ; 147        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB19     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; AB20     ; 148        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB21     ; 150        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; AB22     ; 161        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B3       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B4       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; B5       ; 468        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B6       ; 470        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B7       ; 472        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B8       ;            ; 8A       ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; B9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B10      ; 465        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B11      ; 452        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B12      ; 442        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B13      ; 430        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; B15      ; 427        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B16      ; 406        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B17      ; 384        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B18      ; 382        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B19      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; B20      ; 380        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B21      ; 387        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; B22      ; 394        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C1       ; 19         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C2       ; 18         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C5       ; 542        ; 9A       ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; C6       ; 474        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C7       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C8       ; 480        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C9       ; 467        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C10      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C11      ; 450        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C12      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; C13      ; 443        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C14      ;            ; 7A       ; VREFB7AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; C15      ; 425        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C16      ; 408        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; C18      ; 395        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C19      ; 393        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C20      ; 378        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C21      ; 385        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; C22      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D3       ; 16         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D4       ; 17         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; D5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D6       ; 476        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D7       ; 478        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D8       ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D9       ; 479        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D11      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D12      ; 449        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D13      ; 441        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D14      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D15      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D16      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D17      ; 409        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D18      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; D19      ; 379        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D20      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; D21      ; 376        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; D22      ; 392        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E1       ; 20         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E2       ; 21         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E5       ; 539        ; 9A       ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E6       ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E7       ; 484        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E8       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E9       ; 477        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E10      ; 469        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E11      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E12      ; 451        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; E14      ; 433        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E15      ; 417        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E16      ; 411        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E17      ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; E18      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; E19      ; 377        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E20      ; 398        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E21      ; 374        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; E22      ; 390        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F3       ; 541        ; 9A       ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F4       ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F5       ; 14         ; B1L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; F6       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F7       ; 482        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F8       ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; F9       ; 471        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F10      ; 455        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F11      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F12      ; 440        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F13      ; 435        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F14      ; 428        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F15      ; 419        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F16      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; F17      ; 372        ; 7A       ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; F18      ; 399        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F19      ; 397        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F20      ; 400        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; F21      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; F22      ; 388        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G1       ; 23         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G2       ; 22         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G4       ; 15         ; B1L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; G5       ; 537        ; 9A       ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; G6       ; 481        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G7       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G8       ; 460        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G10      ; 453        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G11      ; 438        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G12      ; 447        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G13      ; 439        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G14      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; G15      ; 426        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G16      ; 412        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G17      ; 410        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G18      ; 413        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G19      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; G20      ; 389        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G21      ; 375        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; G22      ; 386        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H5       ; 536        ; 9A       ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; H6       ; 483        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H8       ; 458        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H9       ; 463        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H10      ; 436        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H11      ; 445        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; H13      ; 437        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H14      ; 429        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H15      ; 423        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H16      ; 421        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H17      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H18      ; 415        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H19      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; H20      ; 391        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H21      ; 373        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; H22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J1       ; 24         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J2       ; 25         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J6       ; 535        ; 9A       ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; J7       ; 457        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J8       ; 459        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J9       ; 461        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J11      ; 434        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J13      ; 431        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J16      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; J17      ; 422        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J18      ; 416        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J19      ; 414        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J20      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; J21      ; 381        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; J22      ; 383        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K3       ;            ; --       ; VCCL_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K5       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K6       ; 534        ; 9A       ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; K7       ; 456        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K8       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K9       ; 448        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; K15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; K16      ; 424        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K17      ; 284        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K18      ;            ; 5B       ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; K19      ; 407        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K20      ; 405        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; K21      ; 289        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; K22      ; 291        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L1       ; 27         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L2       ; 26         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L6       ; 533        ; 9A       ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L7       ; 454        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; L8       ; 446        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; L9       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; L10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L16      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; L17      ; 286        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L18      ; 290        ; 5B       ; count[7]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; L19      ; 288        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; L20      ;            ; 5B       ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; L21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; L22      ; 283        ; 5B       ; count[3]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M3       ;            ; --       ; VCCH_GXBL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M5       ; 42         ; 3A       ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;

+; M6       ; 64         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M7       ; 66         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M8       ; 112        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M9       ; 114        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; M10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; M15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; M16      ; 278        ; 5B       ; clock                           ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M17      ;            ; 5B       ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M18      ; 282        ; 5B       ; count[5]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M19      ;            ; 5B       ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; M20      ; 285        ; 5B       ; count[0]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; M21      ; 287        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; M22      ; 281        ; 5B       ; count[6]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N1       ; 28         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; N2       ; 29         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; N3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N6       ; 58         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N8       ; 106        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N9       ; 130        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; N10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; N15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N16      ; 276        ; 5B       ; enable                          ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; N18      ;            ; 5B       ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; N19      ; 280        ; 5B       ; count[2]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N20      ; 277        ; 5B       ; count[4]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N21      ; 279        ; 5B       ; count[1]                        ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;

+; N22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P3       ;            ; --       ; VCCL_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P5       ; 44         ; 3A       ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; P6       ; 56         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P7       ; 67         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P8       ; 104        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P9       ; 128        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; P11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P12      ; 123        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P14      ; 168        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; P15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;

+; P16      ; 225        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P17      ; 227        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P18      ; 226        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P19      ; 224        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; P20      ;            ; 5A       ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P21      ;            ; 5A       ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; P22      ; 222        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R1       ; 31         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; R2       ; 30         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; R3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R4       ; 43         ; 3A       ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; R5       ; 54         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R6       ; 52         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R7       ; 65         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R8       ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R9       ; 119        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R10      ; 125        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R11      ; 127        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R12      ; 121        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; R14      ; 170        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; R15      ; 219        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R16      ; 221        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R17      ; 223        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R18      ;            ; 5A       ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; R19      ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; R20      ;            ; 5A       ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; R21      ; 220        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; R22      ; 218        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T3       ;            ; --       ; VCCH_GXBL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T4       ; 45         ; 3A       ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; T5       ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T6       ;            ; 3A       ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T7       ; 60         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T8       ; 62         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T9       ; 109        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T10      ; 117        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T11      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; T12      ; 136        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T13      ; 138        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T14      ; 152        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; T15      ; 217        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T16      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T17      ; 215        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T18      ; 213        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T19      ; 212        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T20      ; 214        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; T21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; T22      ; 216        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;

+; U1       ; 32         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; U2       ; 33         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; U3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U4       ; 41         ; B0L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; U5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U6       ; 61         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U7       ; 53         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U8       ; 55         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; U10      ; 111        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U11      ; 120        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U12      ; 122        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U13      ; 135        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U14      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U15      ; 154        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U16      ; 176        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U17      ; 178        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U18      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U19      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; U20      ; 179        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U21      ; 177        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; U22      ; 172        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V3       ; 50         ; 3A       ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;

+; V4       ; 40         ; B0L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;

+; V5       ; 46         ; 3A       ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; V6       ; 63         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V8       ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;

+; V9       ; 101        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V10      ; 103        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V11      ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; V12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V13      ; 133        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V14      ; 144        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V15      ; 146        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V16      ; 160        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; V18      ; 175        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V19      ; 173        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V20      ; 157        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V21      ; 174        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; V22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W1       ; 35         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; W2       ; 34         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; W3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; W5       ; 48         ; 3A       ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;

+; W6       ;            ; 3A       ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W7       ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W8       ; 57         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W9       ; 59         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W10      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W11      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W12      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W13      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W14      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W15      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W16      ; 162        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W17      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W18      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W19      ; 159        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W20      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; W21      ; 171        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; W22      ; 166        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y3       ; 36         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y4       ; 37         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y6       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y7       ;            ; 3A       ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y8       ;            ; 3A       ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y9       ; 118        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y10      ; 116        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y11      ; 129        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y12      ;            ; 3B       ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y13      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;

+; Y14      ; 141        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y15      ; 143        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y16      ; 149        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y17      ; 151        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y18      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;

+; Y19      ; 167        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y20      ; 165        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y21      ; 169        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

+; Y22      ; 164        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;

++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+

+Note: Pin directions (input, output or bidir) are based on device operating in user mode.

+

+

++------------------------------------------+

+; I/O Assignment Warnings                  ;

++----------+-------------------------------+

+; Pin Name ; Reason                        ;

++----------+-------------------------------+

+; count[0] ; Incomplete set of assignments ;

+; count[1] ; Incomplete set of assignments ;

+; count[2] ; Incomplete set of assignments ;

+; count[3] ; Incomplete set of assignments ;

+; count[4] ; Incomplete set of assignments ;

+; count[5] ; Incomplete set of assignments ;

+; count[6] ; Incomplete set of assignments ;

+; count[7] ; Incomplete set of assignments ;

+; clock    ; Incomplete set of assignments ;

+; enable   ; Incomplete set of assignments ;

+; count[0] ; Missing location assignment   ;

+; count[1] ; Missing location assignment   ;

+; count[2] ; Missing location assignment   ;

+; count[3] ; Missing location assignment   ;

+; count[4] ; Missing location assignment   ;

+; count[5] ; Missing location assignment   ;

+; count[6] ; Missing location assignment   ;

+; count[7] ; Missing location assignment   ;

+; clock    ; Missing location assignment   ;

+; enable   ; Missing location assignment   ;

++----------+-------------------------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                  ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+; |ex5                       ; 4.5 (4.5)            ; 4.5 (4.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 9 (9)               ; 8 (8)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 10   ; 0            ; |ex5                ; ex5         ; work         ;

++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Delay Chain Summary                                                                                                     ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+; count[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; count[7] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;

+; clock    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;

+; enable   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;

++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+

+

+

++----------------------------------------------------+

+; Pad To Core Delay Chain Fanout                     ;

++----------------------+-------------------+---------+

+; Source Pin / Fanout  ; Pad To Core Index ; Setting ;

++----------------------+-------------------+---------+

+; clock                ;                   ;         ;

+; enable               ;                   ;         ;

+;      - count[1]~reg0 ; 1                 ; 0       ;

+;      - count[2]~reg0 ; 1                 ; 0       ;

+;      - count[3]~reg0 ; 1                 ; 0       ;

+;      - count[4]~reg0 ; 1                 ; 0       ;

+;      - count[5]~reg0 ; 1                 ; 0       ;

+;      - count[6]~reg0 ; 1                 ; 0       ;

+;      - count[7]~reg0 ; 1                 ; 0       ;

+;      - count[0]~reg0 ; 1                 ; 0       ;

++----------------------+-------------------+---------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Control Signals                                                                                                           ;

++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+

+; Name   ; Location ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+

+; clock  ; PIN_M16  ; 8       ; Clock        ; yes    ; Global Clock         ; GCLK10           ; --                        ;

+; enable ; PIN_N16  ; 8       ; Clock enable ; no     ; --                   ; --               ; --                        ;

++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+

+

+

++--------------------------------------------------------------------------------------------------+

+; Global & Other Fast Signals                                                                      ;

++-------+----------+---------+----------------------+------------------+---------------------------+

+; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;

++-------+----------+---------+----------------------+------------------+---------------------------+

+; clock ; PIN_M16  ; 8       ; Global Clock         ; GCLK10           ; --                        ;

++-------+----------+---------+----------------------+------------------+---------------------------+

+

+

++------------------------------------------------------+

+; Routing Usage Summary                                ;

++------------------------------+-----------------------+

+; Routing Resource Type        ; Usage                 ;

++------------------------------+-----------------------+

+; Block interconnects          ; 9 / 374,484 ( < 1 % ) ;

+; C12 interconnects            ; 0 / 16,664 ( 0 % )    ;

+; C2 interconnects             ; 5 / 155,012 ( < 1 % ) ;

+; C4 interconnects             ; 0 / 72,600 ( 0 % )    ;

+; DQS bus muxes                ; 0 / 30 ( 0 % )        ;

+; DQS-18 I/O buses             ; 0 / 30 ( 0 % )        ;

+; DQS-9 I/O buses              ; 0 / 30 ( 0 % )        ;

+; Direct links                 ; 0 / 374,484 ( 0 % )   ;

+; Global clocks                ; 1 / 16 ( 6 % )        ;

+; Horizontal periphery clocks  ; 0 / 72 ( 0 % )        ;

+; Local interconnects          ; 1 / 112,960 ( < 1 % ) ;

+; Quadrant clocks              ; 0 / 88 ( 0 % )        ;

+; R14 interconnects            ; 0 / 15,868 ( 0 % )    ;

+; R14/C12 interconnect drivers ; 0 / 27,256 ( 0 % )    ;

+; R3 interconnects             ; 1 / 169,296 ( < 1 % ) ;

+; R6 interconnects             ; 5 / 330,800 ( < 1 % ) ;

+; Spine clocks                 ; 1 / 480 ( < 1 % )     ;

+; Wire stub REs                ; 0 / 20,834 ( 0 % )    ;

++------------------------------+-----------------------+

+

+

++------------------------------------------+

+; I/O Rules Summary                        ;

++----------------------------------+-------+

+; I/O Rules Statistic              ; Total ;

++----------------------------------+-------+

+; Total I/O Rules                  ; 28    ;

+; Number of I/O Rules Passed       ; 6     ;

+; Number of I/O Rules Failed       ; 0     ;

+; Number of I/O Rules Unchecked    ; 0     ;

+; Number of I/O Rules Inapplicable ; 22    ;

++----------------------------------+-------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Details                                                                                                                                                                                                                                                                 ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+

+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area                ; Extra Information ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+

+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;

+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;

+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;

+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;

+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;

+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;

+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;

+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;

+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;

+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;

+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;

+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;

+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;

+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;

+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;

+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;

+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;

+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;

+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                            ; None     ; ----                                                                     ; On Chip Termination ;                   ;

++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+

+

+

++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                              ;

++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;

++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 10        ; 0            ; 0            ; 10        ; 10        ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; Total Inapplicable ; 10           ; 10           ; 10           ; 10           ; 10           ; 0         ; 10           ; 10           ; 0         ; 0         ; 10           ; 2            ; 10           ; 10           ; 10           ; 10           ; 2            ; 10           ; 10           ; 10           ; 10           ; 2            ; 10           ; 10           ; 10           ; 10           ; 10           ; 10           ;

+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;

+; count[0]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[1]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[2]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[3]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[4]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[5]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[6]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; count[7]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; clock              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

+; enable             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;

++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+

+

+

++------------------------------------------------------------------------------------------------+

+; Fitter Device Options                                                                          ;

++------------------------------------------------------------------+-----------------------------+

+; Option                                                           ; Setting                     ;

++------------------------------------------------------------------+-----------------------------+

+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;

+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;

+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;

+; Enable INIT_DONE output                                          ; Off                         ;

+; Configuration scheme                                             ; Passive Serial              ;

+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;

+; Enable CvP_CONFDONE pin                                          ; Off                         ;

+; Enable open drain on CRC_ERROR pin                               ; On                          ;

+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;

+; Enable open drain on INIT_DONE pin                               ; On                          ;

+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;

+; Enable open drain on nCEO pin                                    ; On                          ;

+; Enable Partial Reconfiguration pins                              ; Off                         ;

+; Enable input tri-state on active configuration pins in user mode ; Off                         ;

+; Enable internal scrubbing                                        ; Off                         ;

+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;

+; Device initialization clock source                               ; Internal Oscillator         ;

+; Configuration via Protocol                                       ; Off                         ;

+; Configuration Voltage Level                                      ; Auto                        ;

+; Force Configuration Voltage Level                                ; Off                         ;

+; Enable nCEO output                                               ; Off                         ;

+; Data[15..8]                                                      ; Unreserved                  ;

+; Data[7..5]                                                       ; Unreserved                  ;

+; Base pin-out file on sameframe device                            ; Off                         ;

++------------------------------------------------------------------+-----------------------------+

+

+

++------------------------------------+

+; Operating Settings and Conditions  ;

++---------------------------+--------+

+; Setting                   ; Value  ;

++---------------------------+--------+

+; Nominal Core Voltage      ; 1.10 V ;

+; Low Junction Temperature  ; 0 °C   ;

+; High Junction Temperature ; 85 °C  ;

++---------------------------+--------+

+

+

++------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Summary              ;

++-----------------+----------------------+-------------------+

+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;

++-----------------+----------------------+-------------------+

+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.

+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.

+

+

++------------------------------------------------------------+

+; Estimated Delay Added for Hold Timing Details              ;

++-----------------+----------------------+-------------------+

+; Source Register ; Destination Register ; Delay Added in ns ;

++-----------------+----------------------+-------------------+

+; count[0]~reg0   ; count[7]~reg0        ; 0.463             ;

++-----------------+----------------------+-------------------+

+Note: This table only shows the top 1 path(s) that have the largest delay added for hold.

+

+

++-----------------+

+; Fitter Messages ;

++-----------------+

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected

+Info (119006): Selected device 5CGXFC7C7F23C8 for design "ex5"

+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.

+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.

+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.

+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

+Critical Warning (169085): No exact pin location assignment(s) for 10 pins of 10 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.

+Info (184020): Starting Fitter periphery placement operations

+Info (11191): Automatically promoted 1 clock (1 global)

+    Info (11162): clock~inputCLKENA0 with 8 fanout uses global clock CLKCTRL_G10

+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00

+Info (176233): Starting register packing

+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

+Info (332144): No user constrained base clocks found in the design

+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"

+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.

+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.

+Info (176235): Finished register packing

+    Extra Info (176219): No registers were packed into other blocks

+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:21

+Info (170189): Fitter placement preparation operations beginning

+Info (14951): The Fitter is using Advanced Physical Optimization.

+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:05

+Info (170191): Fitter placement operations beginning

+Info (170137): Fitter placement was successful

+Info (170192): Fitter placement operations ending: elapsed time is 00:00:04

+Info (170193): Fitter routing operations beginning

+Info (170195): Router estimated average interconnect usage is 0% of the available device resources

+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45

+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.

+    Info (170201): Optimizations that may affect the design's routability were skipped

+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02

+Info (11888): Total time spent on timing analysis during the Fitter is 0.42 seconds.

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (334003): Started post-fitting delay annotation

+Info (334004): Delay annotation completed successfully

+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:07

+Info (144001): Generated suppressed messages file C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg

+Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings

+    Info: Peak virtual memory: 2264 megabytes

+    Info: Processing ended: Tue Nov 22 09:28:31 2016

+    Info: Elapsed time: 00:01:28

+    Info: Total CPU time (on all processors): 00:01:40

+

+

++----------------------------+

+; Fitter Suppressed Messages ;

++----------------------------+

+The suppressed messages can be found in C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/output_files/ex5.fit.smsg.

+

+

diff --git a/part_2/ex5/output_files/ex5.fit.smsg b/part_2/ex5/output_files/ex5.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing

+Extra Info (176237): Finished Fast Input/Output/OE register processing

+Extra Info (176238): Start inferring scan chains for DSP blocks

+Extra Info (176239): Inferring scan chains for DSP blocks is complete

+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density

+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

diff --git a/part_2/ex5/output_files/ex5.fit.summary b/part_2/ex5/output_files/ex5.fit.summary
new file mode 100755
index 0000000..65b612c
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Nov 22 09:28:30 2016

+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Revision Name : ex5

+Top-level Entity Name : ex5

+Family : Cyclone V

+Device : 5CGXFC7C7F23C8

+Timing Models : Final

+Logic utilization (in ALMs) : 5 / 56,480 ( < 1 % )

+Total registers : 8

+Total pins : 10 / 268 ( 4 % )

+Total virtual pins : 0

+Total block memory bits : 0 / 7,024,640 ( 0 % )

+Total RAM Blocks : 0 / 686 ( 0 % )

+Total DSP Blocks : 0 / 156 ( 0 % )

+Total HSSI RX PCSs : 0 / 6 ( 0 % )

+Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % )

+Total HSSI TX PCSs : 0 / 6 ( 0 % )

+Total HSSI PMA TX Serializers : 0 / 6 ( 0 % )

+Total PLLs : 0 / 13 ( 0 % )

+Total DLLs : 0 / 4 ( 0 % )

diff --git a/part_2/ex5/output_files/ex5.flow.rpt b/part_2/ex5/output_files/ex5.flow.rpt
new file mode 100755
index 0000000..f868c8e
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.flow.rpt
@@ -0,0 +1,121 @@
+Flow report for ex5

+Tue Nov 22 09:28:58 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Flow Summary

+  3. Flow Settings

+  4. Flow Non-Default Global Settings

+  5. Flow Elapsed Time

+  6. Flow OS Summary

+  7. Flow Log

+  8. Flow Messages

+  9. Flow Suppressed Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-------------------------------------------------------------------------------+

+; Flow Summary                                                                  ;

++---------------------------------+---------------------------------------------+

+; Flow Status                     ; Successful - Tue Nov 22 09:28:58 2016       ;

+; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;

+; Revision Name                   ; ex5                                         ;

+; Top-level Entity Name           ; ex5                                         ;

+; Family                          ; Cyclone V                                   ;

+; Device                          ; 5CGXFC7C7F23C8                              ;

+; Timing Models                   ; Final                                       ;

+; Logic utilization (in ALMs)     ; 5 / 56,480 ( < 1 % )                        ;

+; Total registers                 ; 8                                           ;

+; Total pins                      ; 10 / 268 ( 4 % )                            ;

+; Total virtual pins              ; 0                                           ;

+; Total block memory bits         ; 0 / 7,024,640 ( 0 % )                       ;

+; Total DSP Blocks                ; 0 / 156 ( 0 % )                             ;

+; Total HSSI RX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % )                               ;

+; Total HSSI TX PCSs              ; 0 / 6 ( 0 % )                               ;

+; Total HSSI PMA TX Serializers   ; 0 / 6 ( 0 % )                               ;

+; Total PLLs                      ; 0 / 13 ( 0 % )                              ;

+; Total DLLs                      ; 0 / 4 ( 0 % )                               ;

++---------------------------------+---------------------------------------------+

+

+

++-----------------------------------------+

+; Flow Settings                           ;

++-------------------+---------------------+

+; Option            ; Setting             ;

++-------------------+---------------------+

+; Start date & time ; 11/22/2016 09:26:39 ;

+; Main task         ; Compilation         ;

+; Revision Name     ; ex5                 ;

++-------------------+---------------------+

+

+

++-------------------------------------------------------------------------------------------------------------------------+

+; Flow Non-Default Global Settings                                                                                        ;

++-------------------------------------+----------------------------------------+---------------+-------------+------------+

+; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id ;

++-------------------------------------+----------------------------------------+---------------+-------------+------------+

+; COMPILER_SIGNATURE_ID               ; 44883562331268.147980679801764         ; --            ; --          ; --         ;

+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;

+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;

+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;

+; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --         ;

++-------------------------------------+----------------------------------------+---------------+-------------+------------+

+

+

++--------------------------------------------------------------------------------------------------------------------------+

+; Flow Elapsed Time                                                                                                        ;

++----------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;

++----------------------+--------------+-------------------------+---------------------+------------------------------------+

+; Analysis & Synthesis ; 00:00:21     ; 1.0                     ; 686 MB              ; 00:00:43                           ;

+; Fitter               ; 00:01:27     ; 1.0                     ; 2264 MB             ; 00:01:39                           ;

+; Assembler            ; 00:00:23     ; 1.0                     ; 707 MB              ; 00:00:15                           ;

+; Total                ; 00:02:11     ; --                      ; --                  ; 00:02:37                           ;

++----------------------+--------------+-------------------------+---------------------+------------------------------------+

+

+

++------------------------------------------------------------------------------------+

+; Flow OS Summary                                                                    ;

++----------------------+------------------+------------+------------+----------------+

+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;

++----------------------+------------------+------------+------------+----------------+

+; Analysis & Synthesis ; Lenovo-PC-Marco  ; Windows 10 ; 10.0       ; x86_64         ;

+; Fitter               ; Lenovo-PC-Marco  ; Windows 10 ; 10.0       ; x86_64         ;

+; Assembler            ; Lenovo-PC-Marco  ; Windows 10 ; 10.0       ; x86_64         ;

++----------------------+------------------+------------+------------+----------------+

+

+

+------------

+; Flow Log ;

+------------

+quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5

+quartus_fit --read_settings_files=off --write_settings_files=off ex5 -c ex5

+quartus_asm --read_settings_files=off --write_settings_files=off ex5 -c ex5

+

+

+

diff --git a/part_2/ex5/output_files/ex5.jdi b/part_2/ex5/output_files/ex5.jdi
new file mode 100755
index 0000000..9f202d3
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>

+  <project>

+    <hash md5_digest_80b="a02c1fe6114b91718b29"/>

+  </project>

+  <file_info>

+    <file device="5CGXFC7C7F23C8" path="ex5.sof" usercode="0xFFFFFFFF"/>

+  </file_info>

+</sld_project_info>

diff --git a/part_2/ex5/output_files/ex5.map.rpt b/part_2/ex5/output_files/ex5.map.rpt
new file mode 100755
index 0000000..3808bd6
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.map.rpt
@@ -0,0 +1,299 @@
+Analysis & Synthesis report for ex5

+Tue Nov 22 09:27:01 2016

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+

+

+---------------------

+; Table of Contents ;

+---------------------

+  1. Legal Notice

+  2. Analysis & Synthesis Summary

+  3. Analysis & Synthesis Settings

+  4. Parallel Compilation

+  5. Analysis & Synthesis Source Files Read

+  6. Analysis & Synthesis Resource Usage Summary

+  7. Analysis & Synthesis Resource Utilization by Entity

+  8. General Register Statistics

+  9. Parameter Settings for User Entity Instance: Top-level Entity: |ex5

+ 10. Post-Synthesis Netlist Statistics for Top Partition

+ 11. Elapsed Time Per Partition

+ 12. Analysis & Synthesis Messages

+

+

+

+----------------

+; Legal Notice ;

+----------------

+Copyright (C) 2016  Intel Corporation. All rights reserved.

+Your use of Intel Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files from any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Intel Program License 

+Subscription Agreement, the Intel Quartus Prime License Agreement,

+the Intel MegaCore Function License Agreement, or other 

+applicable license agreement, including, without limitation, 

+that your use is for the sole purpose of programming logic 

+devices manufactured by Intel and sold by Intel or its 

+authorized distributors.  Please refer to the applicable 

+agreement for further details.

+

+

+

++-------------------------------------------------------------------------------+

+; Analysis & Synthesis Summary                                                  ;

++---------------------------------+---------------------------------------------+

+; Analysis & Synthesis Status     ; Successful - Tue Nov 22 09:27:01 2016       ;

+; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;

+; Revision Name                   ; ex5                                         ;

+; Top-level Entity Name           ; ex5                                         ;

+; Family                          ; Cyclone V                                   ;

+; Logic utilization (in ALMs)     ; N/A                                         ;

+; Total registers                 ; 8                                           ;

+; Total pins                      ; 10                                          ;

+; Total virtual pins              ; 0                                           ;

+; Total block memory bits         ; 0                                           ;

+; Total DSP Blocks                ; 0                                           ;

+; Total HSSI RX PCSs              ; 0                                           ;

+; Total HSSI PMA RX Deserializers ; 0                                           ;

+; Total HSSI TX PCSs              ; 0                                           ;

+; Total HSSI PMA TX Serializers   ; 0                                           ;

+; Total PLLs                      ; 0                                           ;

+; Total DLLs                      ; 0                                           ;

++---------------------------------+---------------------------------------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Settings                                                                                             ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Option                                                                          ; Setting            ; Default Value      ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+; Device                                                                          ; 5CGXFC7C7F23C8     ;                    ;

+; Top-level entity name                                                           ; ex5                ; ex5                ;

+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;

+; Use smart compilation                                                           ; Off                ; Off                ;

+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;

+; Enable compact report table                                                     ; Off                ; Off                ;

+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;

+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;

+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;

+; Preserve fewer node names                                                       ; On                 ; On                 ;

+; OpenCore Plus hardware evaluation                                               ; Enable             ; Enable             ;

+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;

+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;

+; State Machine Processing                                                        ; Auto               ; Auto               ;

+; Safe State Machine                                                              ; Off                ; Off                ;

+; Extract Verilog State Machines                                                  ; On                 ; On                 ;

+; Extract VHDL State Machines                                                     ; On                 ; On                 ;

+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;

+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;

+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;

+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;

+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;

+; Parallel Synthesis                                                              ; On                 ; On                 ;

+; DSP Block Balancing                                                             ; Auto               ; Auto               ;

+; NOT Gate Push-Back                                                              ; On                 ; On                 ;

+; Power-Up Don't Care                                                             ; On                 ; On                 ;

+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;

+; Remove Duplicate Registers                                                      ; On                 ; On                 ;

+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;

+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;

+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;

+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;

+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;

+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;

+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;

+; Optimization Technique                                                          ; Balanced           ; Balanced           ;

+; Carry Chain Length                                                              ; 70                 ; 70                 ;

+; Auto Carry Chains                                                               ; On                 ; On                 ;

+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;

+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;

+; Auto ROM Replacement                                                            ; On                 ; On                 ;

+; Auto RAM Replacement                                                            ; On                 ; On                 ;

+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;

+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;

+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;

+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;

+; Strict RAM Replacement                                                          ; Off                ; Off                ;

+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;

+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;

+; Auto Resource Sharing                                                           ; Off                ; Off                ;

+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;

+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;

+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;

+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;

+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;

+; Report Parameter Settings                                                       ; On                 ; On                 ;

+; Report Source Assignments                                                       ; On                 ; On                 ;

+; Report Connectivity Checks                                                      ; On                 ; On                 ;

+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;

+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;

+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;

+; HDL message level                                                               ; Level2             ; Level2             ;

+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;

+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;

+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;

+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;

+; Clock MUX Protection                                                            ; On                 ; On                 ;

+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;

+; Block Design Naming                                                             ; Auto               ; Auto               ;

+; SDC constraint protection                                                       ; Off                ; Off                ;

+; Synthesis Effort                                                                ; Auto               ; Auto               ;

+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;

+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;

+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;

+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;

+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;

+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;

+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;

++---------------------------------------------------------------------------------+--------------------+--------------------+

+

+

++------------------------------------------+

+; Parallel Compilation                     ;

++----------------------------+-------------+

+; Processors                 ; Number      ;

++----------------------------+-------------+

+; Number detected on machine ; 4           ;

+; Maximum allowed            ; 2           ;

+;                            ;             ;

+; Average used               ; 1.00        ;

+; Maximum used               ; 2           ;

+;                            ;             ;

+; Usage by Processor         ; % Time Used ;

+;     Processor 1            ; 100.0%      ;

+;     Processor 2            ;   0.0%      ;

++----------------------------+-------------+

+

+

++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Source Files Read                                                                                                                                                      ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+

+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                        ; Library ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+

+; verilog files/ex5.v              ; yes             ; User Verilog HDL File  ; C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v ;         ;

++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------+---------+

+

+

++-----------------------------------------------------------+

+; Analysis & Synthesis Resource Usage Summary               ;

++---------------------------------------------+-------------+

+; Resource                                    ; Usage       ;

++---------------------------------------------+-------------+

+; Estimate of Logic utilization (ALMs needed) ; 4           ;

+;                                             ;             ;

+; Combinational ALUT usage for logic          ; 8           ;

+;     -- 7 input functions                    ; 0           ;

+;     -- 6 input functions                    ; 0           ;

+;     -- 5 input functions                    ; 0           ;

+;     -- 4 input functions                    ; 0           ;

+;     -- <=3 input functions                  ; 8           ;

+;                                             ;             ;

+; Dedicated logic registers                   ; 8           ;

+;                                             ;             ;

+; I/O pins                                    ; 10          ;

+;                                             ;             ;

+; Total DSP Blocks                            ; 0           ;

+;                                             ;             ;

+; Maximum fan-out node                        ; clock~input ;

+; Maximum fan-out                             ; 8           ;

+; Total fan-out                               ; 57          ;

+; Average fan-out                             ; 1.58        ;

++---------------------------------------------+-------------+

+

+

++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                    ;

++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;

++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+; |ex5                       ; 8 (8)               ; 8 (8)                     ; 0                 ; 0          ; 10   ; 0            ; |ex5                ; ex5         ; work         ;

++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+

+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

+

+

++------------------------------------------------------+

+; General Register Statistics                          ;

++----------------------------------------------+-------+

+; Statistic                                    ; Value ;

++----------------------------------------------+-------+

+; Total registers                              ; 8     ;

+; Number of registers using Synchronous Clear  ; 0     ;

+; Number of registers using Synchronous Load   ; 0     ;

+; Number of registers using Asynchronous Clear ; 0     ;

+; Number of registers using Asynchronous Load  ; 0     ;

+; Number of registers using Clock Enable       ; 8     ;

+; Number of registers using Preset             ; 0     ;

++----------------------------------------------+-------+

+

+

++---------------------------------------------------------------------+

+; Parameter Settings for User Entity Instance: Top-level Entity: |ex5 ;

++----------------+-------+--------------------------------------------+

+; Parameter Name ; Value ; Type                                       ;

++----------------+-------+--------------------------------------------+

+; BIT_SZ         ; 8     ; Signed Integer                             ;

++----------------+-------+--------------------------------------------+

+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".

+

+

++-----------------------------------------------------+

+; Post-Synthesis Netlist Statistics for Top Partition ;

++-----------------------+-----------------------------+

+; Type                  ; Count                       ;

++-----------------------+-----------------------------+

+; arriav_ff             ; 8                           ;

+;     ENA               ; 8                           ;

+; arriav_lcell_comb     ; 8                           ;

+;     arith             ; 7                           ;

+;         1 data inputs ; 6                           ;

+;         2 data inputs ; 1                           ;

+;     normal            ; 1                           ;

+;         1 data inputs ; 1                           ;

+; boundary_port         ; 10                          ;

+;                       ;                             ;

+; Max LUT depth         ; 1.60                        ;

+; Average LUT depth     ; 1.27                        ;

++-----------------------+-----------------------------+

+

+

++-------------------------------+

+; Elapsed Time Per Partition    ;

++----------------+--------------+

+; Partition Name ; Elapsed Time ;

++----------------+--------------+

+; Top            ; 00:00:02     ;

++----------------+--------------+

+

+

++-------------------------------+

+; Analysis & Synthesis Messages ;

++-------------------------------+

+Info: *******************************************************************

+Info: Running Quartus Prime Analysis & Synthesis

+    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+    Info: Processing started: Tue Nov 22 09:26:38 2016

+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex5 -c ex5

+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected

+Info (12021): Found 1 design units, including 1 entities, in source file verilog files/counter_8.v

+    Info (12023): Found entity 1: counter_8 File: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/counter_8.v Line: 3

+Info (12021): Found 1 design units, including 1 entities, in source file verilog files/ex5.v

+    Info (12023): Found entity 1: ex5 File: C:/Users/Marco/OneDrive/Imperial College/Year 2/Electronics lab/VERI/part_2/ex5/verilog files/ex5.v Line: 3

+Info (12127): Elaborating entity "ex5" for the top level hierarchy

+Info (286030): Timing-Driven Synthesis is running

+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

+Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different

+    Info (21058): Implemented 2 input pins

+    Info (21059): Implemented 8 output pins

+    Info (21061): Implemented 8 logic cells

+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning

+    Info: Peak virtual memory: 698 megabytes

+    Info: Processing ended: Tue Nov 22 09:27:02 2016

+    Info: Elapsed time: 00:00:24

+    Info: Total CPU time (on all processors): 00:00:43

+

+

diff --git a/part_2/ex5/output_files/ex5.map.summary b/part_2/ex5/output_files/ex5.map.summary
new file mode 100755
index 0000000..1b964a4
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Nov 22 09:27:01 2016

+Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+Revision Name : ex5

+Top-level Entity Name : ex5

+Family : Cyclone V

+Logic utilization (in ALMs) : N/A

+Total registers : 8

+Total pins : 10

+Total virtual pins : 0

+Total block memory bits : 0

+Total DSP Blocks : 0

+Total HSSI RX PCSs : 0

+Total HSSI PMA RX Deserializers : 0

+Total HSSI TX PCSs : 0

+Total HSSI PMA TX Serializers : 0

+Total PLLs : 0

+Total DLLs : 0

diff --git a/part_2/ex5/output_files/ex5.pin b/part_2/ex5/output_files/ex5.pin
new file mode 100755
index 0000000..1439764
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.pin
@@ -0,0 +1,561 @@
+ -- Copyright (C) 2016  Intel Corporation. All rights reserved.

+ -- Your use of Intel Corporation's design tools, logic functions 

+ -- and other software and tools, and its AMPP partner logic 

+ -- functions, and any output files from any of the foregoing 

+ -- (including device programming or simulation files), and any 

+ -- associated documentation or information are expressly subject 

+ -- to the terms and conditions of the Intel Program License 

+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,

+ -- the Intel MegaCore Function License Agreement, or other 

+ -- applicable license agreement, including, without limitation, 

+ -- that your use is for the sole purpose of programming logic 

+ -- devices manufactured by Intel and sold by Intel or its 

+ -- authorized distributors.  Please refer to the applicable 

+ -- agreement for further details.

+ -- 

+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is

+ -- not intended for use as a Quartus Prime input file. This file cannot be used

+ -- to make Quartus Prime pin assignments - for instructions on how to make pin

+ -- assignments, please see Quartus Prime help.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- NC            : No Connect. This pin has no internal connection to the device.

+ -- DNU           : Do Not Use. This pin MUST NOT be connected.

+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.

+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).

+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC

+ --                 of its bank.

+ --                  Bank 3A:       2.5V

+ --                  Bank 3B:       2.5V

+ --                  Bank 4A:       2.5V

+ --                  Bank 5A:       2.5V

+ --                  Bank 5B:       2.5V

+ --                  Bank 7A:  2.5V

+ --                  Bank 8A:  2.5V

+ --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.

+ -- RREF          : External reference resistor for the quad, MUST be connected to

+ --                 GND via a 2k Ohm resistor.

+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.

+ --                  It can also be used to report unused dedicated pins. The connection

+ --                  on the board for unused dedicated pins depends on whether this will

+ --                  be used in a future design. One example is device migration. When

+ --                  using device migration, refer to the device pin-tables. If it is a

+ --                  GND pin in the pin table or if it will not be used in a future design

+ --                  for another purpose the it MUST be connected to GND. If it is an unused

+ --                  dedicated pin, then it can be connected to a valid signal on the board

+ --                  (low, high, or toggling) if that signal is required for a different

+ --                  revision of the design.

+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.

+ --                  This pin should be connected to GND. It may also be connected  to a

+ --                  valid signal  on the board  (low, high, or toggling)  if that signal

+ --                  is required for a different revision of the design.

+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*

+ --                  either individually through a 10k Ohm resistor to GND or tie all pins

+ --                  together and connect through a single 10k Ohm resistor to GND.

+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.

+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.

+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.

+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.

+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.

+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin

+ --                 must not be connected.

+ ---------------------------------------------------------------------------------

+

+

+

+ ---------------------------------------------------------------------------------

+ -- Pin directions (input, output or bidir) are based on device operating in user mode.

+ ---------------------------------------------------------------------------------

+

+Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition

+CHIP  "ex5"  ASSIGNED TO AN: 5CGXFC7C7F23C8

+

+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

+-------------------------------------------------------------------------------------------------------------

+RREF                         : A1        :        :                   :         :           :                

+MSEL2                        : A2        :        :                   :         : 9A        :                

+VCCBAT                       : A3        : power  :                   : 1.2V    :           :                

+nCONFIG                      : A4        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                

+VCCIO8A                      : A6        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                

+GND                          : A11       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7A        :                

+VCCIO7A                      : A16       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7A        :                

+GND                          : A21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : A22       :        :                   :         : 7A        :                

+GND                          : AA1       :        :                   :         : B0L       :                

+GND                          : AA2       :        :                   :         : B0L       :                

+GND                          : AA3       : gnd    :                   :         :           :                

+GND                          : AA4       : gnd    :                   :         :           :                

+AS_DATA2, DATA2              : AA5       :        :                   :         : 3A        :                

+GND                          : AA6       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3B        :                

+GND                          : AA11      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4A        :                

+VCCIO4A                      : AA16      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                

+VCCIO4A                      : AA21      : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 4A        :                

+GND                          : AB1       : gnd    :                   :         :           :                

+GND                          : AB2       : gnd    :                   :         :           :                

+AS_DATA1, DATA1              : AB3       :        :                   :         : 3A        :                

+AS_DATA0, ASDO, DATA0        : AB4       :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB6       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3B        :                

+GND                          : AB9       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB11      :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4A        :                

+GND                          : AB14      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4A        :                

+VREFB4AN0                    : AB16      : power  :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4A        :                

+GND                          : AB19      : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 4A        :                

+GND                          : B1        : gnd    :                   :         :           :                

+GND                          : B2        : gnd    :                   :         :           :                

+DNU                          : B3        :        :                   :         :           :                

+DNU                          : B4        :        :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                

+VREFB8AN0                    : B8        : power  :                   :         : 8A        :                

+GND                          : B9        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7A        :                

+GND                          : B14       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7A        :                

+VCCIO7A                      : B19       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                

+GND                          : C1        :        :                   :         : B1L       :                

+GND                          : C2        :        :                   :         : B1L       :                

+GND                          : C3        : gnd    :                   :         :           :                

+GND                          : C4        : gnd    :                   :         :           :                

+GND                          : C5        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8A        :                

+VCCIO8A                      : C7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                

+VCCPD7A8A                    : C10       : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7A        :                

+VCCIO7A                      : C12       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7A        :                

+VREFB7AN0                    : C14       : power  :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C16       :        :                   :         : 7A        :                

+GND                          : C17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 7A        :                

+VCCIO7A                      : C22       : power  :                   : 2.5V    : 7A        :                

+GND                          : D1        : gnd    :                   :         :           :                

+GND                          : D2        : gnd    :                   :         :           :                

+GXB_NC                       : D3        :        :                   :         : B1L       :                

+GXB_NC                       : D4        :        :                   :         : B1L       :                

+GND                          : D5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                

+VCCPD7A8A                    : D8        : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                

+GND                          : D10       : gnd    :                   :         :           :                

+VCC_AUX                      : D11       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7A        :                

+VCCPD7A8A                    : D14       : power  :                   : 2.5V    : 7A, 8A    :                

+VCCIO7A                      : D15       : power  :                   : 2.5V    : 7A        :                

+VCCPD7A8A                    : D16       : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7A        :                

+VCC_AUX                      : D18       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7A        :                

+GND                          : D20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                

+GXB_NC                       : E1        :        :                   :         : B1L       :                

+GXB_NC                       : E2        :        :                   :         : B1L       :                

+GND                          : E3        : gnd    :                   :         :           :                

+GND                          : E4        : gnd    :                   :         :           :                

+MSEL3                        : E5        :        :                   :         : 9A        :                

+VCC_AUX                      : E6        : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                

+VCCIO8A                      : E8        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8A        :                

+VCCPD7A8A                    : E11       : power  :                   : 2.5V    : 7A, 8A    :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7A        :                

+GND                          : E13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7A        :                

+DNU                          : E17       :        :                   :         :           :                

+VCCIO7A                      : E18       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 7A        :                

+GND                          : F1        : gnd    :                   :         :           :                

+GND                          : F2        : gnd    :                   :         :           :                

+MSEL4                        : F3        :        :                   :         : 9A        :                

+VCCA_FPLL                    : F4        : power  :                   : 2.5V    :           :                

+GND                          : F5        :        :                   :         : B1L       :                

+GND                          : F6        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8A        :                

+VCCPGM                       : F8        : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                

+VCCIO7A                      : F11       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7A        :                

+GND                          : F16       : gnd    :                   :         :           :                

+GND                          : F17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7A        :                

+VCCIO7A                      : F21       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 7A        :                

+GND                          : G1        :        :                   :         : B1L       :                

+GND                          : G2        :        :                   :         : B1L       :                

+GND                          : G3        : gnd    :                   :         :           :                

+GND                          : G4        :        :                   :         : B1L       :                

+nCE                          : G5        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G6        :        :                   :         : 8A        :                

+VCCIO8A                      : G7        : power  :                   : 2.5V    : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                

+GND                          : G9        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7A        :                

+VCCIO7A                      : G14       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7A        :                

+GND                          : G19       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                

+GND                          : H1        : gnd    :                   :         :           :                

+GND                          : H2        : gnd    :                   :         :           :                

+GND                          : H3        : gnd    :                   :         :           :                

+GND                          : H4        : gnd    :                   :         :           :                

+nSTATUS                      : H5        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 8A        :                

+GND                          : H7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 7A        :                

+GND                          : H12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 7A        :                

+VCCIO7A                      : H17       : power  :                   : 2.5V    : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7A        :                

+VCCA_FPLL                    : H19       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 7A        :                

+GND                          : H22       : gnd    :                   :         :           :                

+GXB_NC                       : J1        :        :                   :         : B1L       :                

+GXB_NC                       : J2        :        :                   :         : B1L       :                

+GND                          : J3        : gnd    :                   :         :           :                

+VCCE_GXBL                    : J4        : power  :                   : 1.1V    :           :                

+GND                          : J5        : gnd    :                   :         :           :                

+MSEL1                        : J6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J8        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                

+VCC                          : J10       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J11       :        :                   :         : 7A        :                

+VCC                          : J12       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 7A        :                

+VCC                          : J14       : power  :                   : 1.1V    :           :                

+GND                          : J15       : gnd    :                   :         :           :                

+VCC                          : J16       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7A        :                

+GND                          : J20       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 7A        :                

+GND                          : K1        : gnd    :                   :         :           :                

+GND                          : K2        : gnd    :                   :         :           :                

+VCCL_GXBL                    : K3        : power  :                   : 1.1V    :           :                

+GND                          : K4        : gnd    :                   :         :           :                

+VCCE_GXBL                    : K5        : power  :                   : 1.1V    :           :                

+CONF_DONE                    : K6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                

+GND                          : K8        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K9        :        :                   :         : 7A        :                

+GND                          : K10       : gnd    :                   :         :           :                

+VCC                          : K11       : power  :                   : 1.1V    :           :                

+GND                          : K12       : gnd    :                   :         :           :                

+VCC                          : K13       : power  :                   : 1.1V    :           :                

+GND                          : K14       : gnd    :                   :         :           :                

+VCC                          : K15       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 5B        :                

+VCCIO5B                      : K18       : power  :                   : 2.5V    : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K20       :        :                   :         : 7A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 5B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 5B        :                

+GND                          : L1        :        :                   :         : B1L       :                

+GND                          : L2        :        :                   :         : B1L       :                

+GND                          : L3        : gnd    :                   :         :           :                

+VCCE_GXBL                    : L4        : power  :                   : 1.1V    :           :                

+GND                          : L5        : gnd    :                   :         :           :                

+MSEL0                        : L6        :        :                   :         : 9A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 8A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 7A        :                

+DNU                          : L9        :        :                   :         :           :                

+VCC                          : L10       : power  :                   : 1.1V    :           :                

+GND                          : L11       : gnd    :                   :         :           :                

+VCC                          : L12       : power  :                   : 1.1V    :           :                

+GND                          : L13       : gnd    :                   :         :           :                

+VCC                          : L14       : power  :                   : 1.1V    :           :                

+GND                          : L15       : gnd    :                   :         :           :                

+VCC                          : L16       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : L17       :        :                   :         : 5B        :                

+count[7]                     : L18       : output : 2.5 V             :         : 5B        : N              

+RESERVED_INPUT_WITH_WEAK_PULLUP : L19       :        :                   :         : 5B        :                

+VREFB5BN0                    : L20       : power  :                   :         : 5B        :                

+GND                          : L21       : gnd    :                   :         :           :                

+count[3]                     : L22       : output : 2.5 V             :         : 5B        : N              

+GND                          : M1        : gnd    :                   :         :           :                

+GND                          : M2        : gnd    :                   :         :           :                

+VCCH_GXBL                    : M3        : power  :                   : 2.5V    :           :                

+GND                          : M4        : gnd    :                   :         :           :                

+TDO                          : M5        : output :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 3B        :                

+GND                          : M10       : gnd    :                   :         :           :                

+VCC                          : M11       : power  :                   : 1.1V    :           :                

+GND                          : M12       : gnd    :                   :         :           :                

+VCC                          : M13       : power  :                   : 1.1V    :           :                

+GND                          : M14       : gnd    :                   :         :           :                

+VCC                          : M15       : power  :                   : 1.1V    :           :                

+clock                        : M16       : input  : 2.5 V             :         : 5B        : N              

+VCCPD5B                      : M17       : power  :                   : 2.5V    : 5B        :                

+count[5]                     : M18       : output : 2.5 V             :         : 5B        : N              

+VCCIO5B                      : M19       : power  :                   : 2.5V    : 5B        :                

+count[0]                     : M20       : output : 2.5 V             :         : 5B        : N              

+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5B        :                

+count[6]                     : M22       : output : 2.5 V             :         : 5B        : N              

+GXB_NC                       : N1        :        :                   :         : B0L       :                

+GXB_NC                       : N2        :        :                   :         : B0L       :                

+GND                          : N3        : gnd    :                   :         :           :                

+VCCE_GXBL                    : N4        : power  :                   : 1.1V    :           :                

+GND                          : N5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3A        :                

+GND                          : N7        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 3B        :                

+VCC                          : N10       : power  :                   : 1.1V    :           :                

+GND                          : N11       : gnd    :                   :         :           :                

+VCC                          : N12       : power  :                   : 1.1V    :           :                

+GND                          : N13       : gnd    :                   :         :           :                

+VCC                          : N14       : power  :                   : 1.1V    :           :                

+GND                          : N15       : gnd    :                   :         :           :                

+enable                       : N16       : input  : 2.5 V             :         : 5B        : N              

+GND                          : N17       : gnd    :                   :         :           :                

+VCCPD5B                      : N18       : power  :                   : 2.5V    : 5B        :                

+count[2]                     : N19       : output : 2.5 V             :         : 5B        : N              

+count[4]                     : N20       : output : 2.5 V             :         : 5B        : N              

+count[1]                     : N21       : output : 2.5 V             :         : 5B        : N              

+GND                          : N22       : gnd    :                   :         :           :                

+GND                          : P1        : gnd    :                   :         :           :                

+GND                          : P2        : gnd    :                   :         :           :                

+VCCL_GXBL                    : P3        : power  :                   : 1.1V    :           :                

+GND                          : P4        : gnd    :                   :         :           :                

+TMS                          : P5        : input  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P9        :        :                   :         : 3B        :                

+GND                          : P10       : gnd    :                   :         :           :                

+VCC                          : P11       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P12       :        :                   :         : 3B        :                

+VCC                          : P13       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 4A        :                

+VCC                          : P15       : power  :                   : 1.1V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P18       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P19       :        :                   :         : 5A        :                

+VCCIO5A                      : P20       : power  :                   : 2.5V    : 5A        :                

+VCCPD5A                      : P21       : power  :                   : 2.5V    : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5A        :                

+GND                          : R1        :        :                   :         : B0L       :                

+GND                          : R2        :        :                   :         : B0L       :                

+GND                          : R3        : gnd    :                   :         :           :                

+nCSO, DATA4                  : R4        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 3A        :                

+VCCIO3B                      : R8        : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3B        :                

+GND                          : R13       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5A        :                

+VCCIO5A                      : R18       : power  :                   : 2.5V    : 5A        :                

+VCCPGM                       : R19       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+VREFB5AN0                    : R20       : power  :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5A        :                

+GND                          : T1        : gnd    :                   :         :           :                

+GND                          : T2        : gnd    :                   :         :           :                

+VCCH_GXBL                    : T3        : power  :                   : 2.5V    :           :                

+AS_DATA3, DATA3              : T4        :        :                   :         : 3A        :                

+VCCA_FPLL                    : T5        : power  :                   : 2.5V    :           :                

+VCCIO3A                      : T6        : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3B        :                

+VCCIO3B                      : T11       : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 5A        :                

+GND                          : T16       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T19       :        :                   :         : 5A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T20       :        :                   :         : 5A        :                

+GND                          : T21       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : T22       :        :                   :         : 5A        :                

+GXB_NC                       : U1        :        :                   :         : B0L       :                

+GXB_NC                       : U2        :        :                   :         : B0L       :                

+GND                          : U3        : gnd    :                   :         :           :                

+GND                          : U4        :        :                   :         : B0L       :                

+GND                          : U5        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U6        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3A        :                

+GND                          : U9        : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4A        :                

+VCCIO4A                      : U14       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U17       :        :                   :         : 4A        :                

+VCCA_FPLL                    : U18       : power  :                   : 2.5V    :           :                

+VCCIO4A                      : U19       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 4A        :                

+GND                          : V1        : gnd    :                   :         :           :                

+GND                          : V2        : gnd    :                   :         :           :                

+DCLK                         : V3        :        :                   :         : 3A        :                

+GND                          : V4        :        :                   :         : B0L       :                

+TCK                          : V5        : input  :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3A        :                

+GND                          : V7        : gnd    :                   :         :           :                

+VCCPGM                       : V8        : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3B        :                

+DNU                          : V11       :        :                   :         :           :                

+GND                          : V12       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                

+GND                          : V17       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V19       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 4A        :                

+GND                          : V22       : gnd    :                   :         :           :                

+GND                          : W1        :        :                   :         : B0L       :                

+GND                          : W2        :        :                   :         : B0L       :                

+GND                          : W3        : gnd    :                   :         :           :                

+GND                          : W4        : gnd    :                   :         :           :                

+TDI                          : W5        : input  :                   :         : 3A        :                

+VCCPD3A                      : W6        : power  :                   : 2.5V    : 3A        :                

+VCC_AUX                      : W7        : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W9        :        :                   :         : 3A        :                

+VCCIO3B                      : W10       : power  :                   : 2.5V    : 3B        :                

+VCCPD3B4A                    : W11       : power  :                   : 2.5V    : 3B, 4A    :                

+VCCPD3B4A                    : W12       : power  :                   : 2.5V    : 3B, 4A    :                

+VCC_AUX                      : W13       : power  :                   : 2.5V    :           :                

+VCCPD3B4A                    : W14       : power  :                   : 2.5V    : 3B, 4A    :                

+VCCIO4A                      : W15       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                

+VCCPD3B4A                    : W17       : power  :                   : 2.5V    : 3B, 4A    :                

+VCC_AUX                      : W18       : power  :                   : 2.5V    :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                

+VCCIO4A                      : W20       : power  :                   : 2.5V    : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 4A        :                

+GND                          : Y1        : gnd    :                   :         :           :                

+GND                          : Y2        : gnd    :                   :         :           :                

+GXB_NC                       : Y3        :        :                   :         : B0L       :                

+GXB_NC                       : Y4        :        :                   :         : B0L       :                

+GND                          : Y5        : gnd    :                   :         :           :                

+DNU                          : Y6        :        :                   :         :           :                

+VREFB3AN0                    : Y7        : power  :                   :         : 3A        :                

+VCCIO3A                      : Y8        : power  :                   : 2.5V    : 3A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y9        :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y11       :        :                   :         : 3B        :                

+VREFB3BN0                    : Y12       : power  :                   :         : 3B        :                

+VCCIO3B                      : Y13       : power  :                   : 2.5V    : 3B        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y14       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y15       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                

+GND                          : Y18       : gnd    :                   :         :           :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y20       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 4A        :                

+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 4A        :                

diff --git a/part_2/ex5/output_files/ex5.sld b/part_2/ex5/output_files/ex5.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.sld
@@ -0,0 +1 @@
+<sld_project_info/>

diff --git a/part_2/ex5/output_files/ex5.sof b/part_2/ex5/output_files/ex5.sof
new file mode 100755
index 0000000..808b964
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.sof
diff --git a/part_2/ex5/output_files/ex5.sta.summary b/part_2/ex5/output_files/ex5.sta.summary
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex5/output_files/ex5.sta.summary
diff --git a/part_2/ex5/pin_assignment.txt b/part_2/ex5/pin_assignment.txt
new file mode 100755
index 0000000..04a3a75
--- /dev/null
+++ b/part_2/ex5/pin_assignment.txt
@@ -0,0 +1,211 @@
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
\ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/ex5_run_msim_rtl_verilog.do b/part_2/ex5/simulation/modelsim/ex5_run_msim_rtl_verilog.do
new file mode 100755
index 0000000..cae582c
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/ex5_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on

+if {[file exists rtl_work]} {

+	vdel -lib rtl_work -all

+}

+vlib rtl_work

+vmap work rtl_work

+

+vlog -vlog01compat -work work +incdir+C:/New\ folder/verilog_files {C:/New folder/verilog_files/counter_8.v}

+

diff --git a/part_2/ex5/simulation/modelsim/modelsim.ini b/part_2/ex5/simulation/modelsim/modelsim.ini
new file mode 100755
index 0000000..3912feb
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/modelsim.ini
@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation

+;

+; All Rights Reserved.

+;

+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 

+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.

+;   

+

+[Library]

+others = $MODEL_TECH/../modelsim.ini

+

+; Altera Primitive libraries

+;

+; VHDL Section

+;

+;

+; Verilog Section

+;

+

+work = rtl_work

+[vcom]

+; VHDL93 variable selects language version as the default. 

+; Default is VHDL-2002.

+; Value of 0 or 1987 for VHDL-1987.

+; Value of 1 or 1993 for VHDL-1993.

+; Default or value of 2 or 2002 for VHDL-2002.

+; Default or value of 3 or 2008 for VHDL-2008.

+VHDL93 = 2002

+

+; Show source line containing error. Default is off.

+; Show_source = 1

+

+; Turn off unbound-component warnings. Default is on.

+; Show_Warning1 = 0

+

+; Turn off process-without-a-wait-statement warnings. Default is on.

+; Show_Warning2 = 0

+

+; Turn off null-range warnings. Default is on.

+; Show_Warning3 = 0

+

+; Turn off no-space-in-time-literal warnings. Default is on.

+; Show_Warning4 = 0

+

+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.

+; Show_Warning5 = 0

+

+; Turn off optimization for IEEE std_logic_1164 package. Default is on.

+; Optimize_1164 = 0

+

+; Turn on resolving of ambiguous function overloading in favor of the

+; "explicit" function declaration (not the one automatically created by

+; the compiler for each type declaration). Default is off.

+; The .ini file has Explicit enabled so that std_logic_signed/unsigned

+; will match the behavior of synthesis tools.

+Explicit = 1

+

+; Turn off acceleration of the VITAL packages. Default is to accelerate.

+; NoVital = 1

+

+; Turn off VITAL compliance checking. Default is checking on.

+; NoVitalCheck = 1

+

+; Ignore VITAL compliance checking errors. Default is to not ignore.

+; IgnoreVitalErrors = 1

+

+; Turn off VITAL compliance checking warnings. Default is to show warnings.

+; Show_VitalChecksWarnings = 0

+

+; Keep silent about case statement static warnings.

+; Default is to give a warning.

+; NoCaseStaticError = 1

+

+; Keep silent about warnings caused by aggregates that are not locally static.

+; Default is to give a warning.

+; NoOthersStaticError = 1

+

+; Turn off inclusion of debugging info within design units.

+; Default is to include debugging info.

+; NoDebug = 1

+

+; Turn off "Loading..." messages. Default is messages on.

+; Quiet = 1

+

+; Turn on some limited synthesis rule compliance checking. Checks only:

+;    -- signals used (read) by a process must be in the sensitivity list

+; CheckSynthesis = 1

+

+; Activate optimizations on expressions that do not involve signals,

+; waits, or function/procedure/task invocations. Default is off.

+; ScalarOpts = 1

+

+; Require the user to specify a configuration for all bindings,

+; and do not generate a compile time default binding for the

+; component. This will result in an elaboration error of

+; 'component not bound' if the user fails to do so. Avoids the rare

+; issue of a false dependency upon the unused default binding.

+; RequireConfigForAllDefaultBinding = 1

+

+; Inhibit range checking on subscripts of arrays. Range checking on

+; scalars defined with subtypes is inhibited by default.

+; NoIndexCheck = 1

+

+; Inhibit range checks on all (implicit and explicit) assignments to

+; scalar objects defined with subtypes.

+; NoRangeCheck = 1

+

+[vlog]

+

+; Turn off inclusion of debugging info within design units.

+; Default is to include debugging info.

+; NoDebug = 1

+

+; Turn off "loading..." messages. Default is messages on.

+; Quiet = 1

+

+; Turn on Verilog hazard checking (order-dependent accessing of global vars).

+; Default is off.

+; Hazard = 1

+

+; Turn on converting regular Verilog identifiers to uppercase. Allows case

+; insensitivity for module names. Default is no conversion.

+; UpCase = 1

+

+; Turn on incremental compilation of modules. Default is off.

+; Incremental = 1

+

+; Turns on lint-style checking.

+; Show_Lint = 1

+

+[vsim]

+; Simulator resolution

+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.

+Resolution = ps

+

+; User time unit for run commands

+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the

+; unit specified for Resolution. For example, if Resolution is 100ps,

+; then UserTimeUnit defaults to ps.

+; Should generally be set to default.

+UserTimeUnit = default

+

+; Default run length

+RunLength = 100

+

+; Maximum iterations that can be run without advancing simulation time

+IterationLimit = 5000

+

+; Directive to license manager:

+; vhdl          Immediately reserve a VHDL license

+; vlog          Immediately reserve a Verilog license

+; plus          Immediately reserve a VHDL and Verilog license

+; nomgc         Do not look for Mentor Graphics Licenses

+; nomti         Do not look for Model Technology Licenses

+; noqueue       Do not wait in the license queue when a license isn't available

+; viewsim	Try for viewer license but accept simulator license(s) instead

+;		of queuing for viewer license

+; License = plus

+

+; Stop the simulator after a VHDL/Verilog assertion message

+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal

+BreakOnAssertion = 3

+

+; Assertion Message Format

+; %S - Severity Level 

+; %R - Report Message

+; %T - Time of assertion

+; %D - Delta

+; %I - Instance or Region pathname (if available)

+; %% - print '%' character

+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

+

+; Assertion File - alternate file for storing VHDL/Verilog assertion messages

+; AssertFile = assert.log

+

+; Default radix for all windows and commands...

+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned

+DefaultRadix = symbolic

+

+; VSIM Startup command

+; Startup = do startup.do

+

+; File for saving command transcript

+TranscriptFile = transcript

+

+; File for saving command history

+; CommandHistory = cmdhist.log

+

+; Specify whether paths in simulator commands should be described

+; in VHDL or Verilog format.

+; For VHDL, PathSeparator = /

+; For Verilog, PathSeparator = .

+; Must not be the same character as DatasetSeparator.

+PathSeparator = /

+

+; Specify the dataset separator for fully rooted contexts.

+; The default is ':'. For example, sim:/top

+; Must not be the same character as PathSeparator.

+DatasetSeparator = :

+

+; Disable VHDL assertion messages

+; IgnoreNote = 1

+; IgnoreWarning = 1

+; IgnoreError = 1

+; IgnoreFailure = 1

+

+; Default force kind. May be freeze, drive, deposit, or default

+; or in other terms, fixed, wired, or charged.

+; A value of "default" will use the signal kind to determine the

+; force kind, drive for resolved signals, freeze for unresolved signals

+; DefaultForceKind = freeze

+

+; If zero, open files when elaborated; otherwise, open files on

+; first read or write.  Default is 0.

+; DelayFileOpen = 1

+

+; Control VHDL files opened for write.

+;   0 = Buffered, 1 = Unbuffered

+UnbufferedOutput = 0

+

+; Control the number of VHDL files open concurrently.

+; This number should always be less than the current ulimit

+; setting for max file descriptors.

+;   0 = unlimited

+ConcurrentFileLimit = 40

+

+; Control the number of hierarchical regions displayed as

+; part of a signal name shown in the Wave window.

+; A value of zero tells VSIM to display the full name.

+; The default is 0.

+; WaveSignalNameWidth = 0

+

+; Turn off warnings from the std_logic_arith, std_logic_unsigned

+; and std_logic_signed packages.

+; StdArithNoWarnings = 1

+

+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.

+; NumericStdNoWarnings = 1

+

+; Control the format of the (VHDL) FOR generate statement label

+; for each iteration.  Do not quote it.

+; The format string here must contain the conversion codes %s and %d,

+; in that order, and no other conversion codes.  The %s represents

+; the generate_label; the %d represents the generate parameter value

+; at a particular generate iteration (this is the position number if

+; the generate parameter is of an enumeration type).  Embedded whitespace

+; is allowed (but discouraged); leading and trailing whitespace is ignored.

+; Application of the format must result in a unique scope name over all

+; such names in the design so that name lookup can function properly.

+; GenerateFormat = %s__%d

+

+; Specify whether checkpoint files should be compressed.

+; The default is 1 (compressed).

+; CheckpointCompressMode = 0

+

+; List of dynamically loaded objects for Verilog PLI applications

+; Veriuser = veriuser.sl

+

+; Specify default options for the restart command. Options can be one

+; or more of: -force -nobreakpoint -nolist -nolog -nowave

+; DefaultRestartOptions = -force

+

+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs

+; (> 500 megabyte memory footprint). Default is disabled.

+; Specify number of megabytes to lock.

+; LockedMemory = 1000

+

+; Turn on (1) or off (0) WLF file compression.

+; The default is 1 (compress WLF file).

+; WLFCompress = 0

+

+; Specify whether to save all design hierarchy (1) in the WLF file

+; or only regions containing logged signals (0).

+; The default is 0 (save only regions with logged signals).

+; WLFSaveAllRegions = 1

+

+; WLF file time limit.  Limit WLF file by time, as closely as possible,

+; to the specified amount of simulation time.  When the limit is exceeded

+; the earliest times get truncated from the file.

+; If both time and size limits are specified the most restrictive is used.

+; UserTimeUnits are used if time units are not specified.

+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}

+; WLFTimeLimit = 0

+

+; WLF file size limit.  Limit WLF file size, as closely as possible,

+; to the specified number of megabytes.  If both time and size limits

+; are specified then the most restrictive is used.

+; The default is 0 (no limit).

+; WLFSizeLimit = 1000

+

+; Specify whether or not a WLF file should be deleted when the

+; simulation ends.  A value of 1 will cause the WLF file to be deleted.

+; The default is 0 (do not delete WLF file when simulation ends).

+; WLFDeleteOnQuit = 1

+

+; Automatic SDF compilation

+; Disables automatic compilation of SDF files in flows that support it.

+; Default is on, uncomment to turn off.

+; NoAutoSDFCompile = 1

+

+[lmc]

+

+[msg_system]

+; Change a message severity or suppress a message.

+; The format is: <msg directive> = <msg number>[,<msg number>...]

+; Examples:

+;   note = 3009

+;   warning = 3033

+;   error = 3010,3016

+;   fatal = 3016,3033

+;   suppress = 3009,3016,3043

+; The command verror <msg number> can be used to get the complete

+; description of a message.

+

+; Control transcripting of elaboration/runtime messages.

+; The default is to have messages appear in the transcript and 

+; recorded in the wlf file (messages that are recorded in the

+; wlf file can be viewed in the MsgViewer).  The other settings

+; are to send messages only to the transcript or only to the 

+; wlf file.  The valid values are

+;    both  {default}

+;    tran  {transcript only}

+;    wlf   {wlf file only}

+; msgmode = both

diff --git a/part_2/ex5/simulation/modelsim/msim_transcript b/part_2/ex5/simulation/modelsim/msim_transcript
new file mode 100755
index 0000000..966f386
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/msim_transcript
@@ -0,0 +1,102 @@
+# Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl 

+# Bad font spec for Editor textFont: t_fixed

+# do ex5_run_msim_rtl_verilog.do 

+# if {[file exists rtl_work]} {

+# 	vdel -lib rtl_work -all

+# }

+# vlib rtl_work

+# vmap work rtl_work

+# Copying C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini

+# Modifying modelsim.ini

+# ** Warning: Copied C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.

+#          Updated modelsim.ini.

+# 

+# vlog -vlog01compat -work work +incdir+C:/New\ folder/verilog_files {C:/New folder/verilog_files/counter_8.v}

+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012

+# -- Compiling module counter_8

+# 

+# Top level modules:

+# 	counter_8

+# 

+vsim -do ex5_run_msim_rtl_verilog.do -l msim_transcript -gui work.counter_8

+# vsim -do ex5_run_msim_rtl_verilog.do -l msim_transcript -gui work.counter_8 

+# Loading work.counter_8

+# do ex5_run_msim_rtl_verilog.do 

+# if {[file exists rtl_work]} {

+# 	vdel -lib rtl_work -all

+# }

+# vlib rtl_work

+# vmap work rtl_work

+# Modifying modelsim.ini

+# 

+# vlog -vlog01compat -work work +incdir+C:/New\ folder/verilog_files {C:/New folder/verilog_files/counter_8.v}

+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012

+# -- Compiling module counter_8

+# 

+# Top level modules:

+# 	counter_8

+# 

+add wave clock enable

+add wave -hexadecimal count

+force enable 1

+run 100ns

+force clock 0 0, 1 10ns -repeat 20ns

+run 100ns

+clear

+# invalid command name "clear"

+clr

+# invalid command name "clr"

+cls

+# 

+restart

+# Loading work.counter_8

+do ./tb_counter.do

+# Cannot open macro file: ./tb_counter.do

+restart

+do ./tb_counter.do

+step

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

+step -over

+# Next activity is in 10 ns.

+# 

+# Next activity is in 10 ns.

+step -over

+step -over

+step -over

diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_info b/part_2/ex5/simulation/modelsim/rtl_work/_info
new file mode 100755
index 0000000..9a599cc
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_info
@@ -0,0 +1,25 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\simulation\modelsim
+vcounter_8
+!i10b 1
+!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
+Ia91@O_<g0BVIc?WTzTbB62
+Vdn7aTnOzPKdeZA;zmQ`Cl3
+Z1 dC:\New folder\simulation\modelsim
+w1479807538
+8C:/New folder/verilog_files/counter_8.v
+FC:/New folder/verilog_files/counter_8.v
+L0 3
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1479807676.024000
+!s107 C:/New folder/verilog_files/counter_8.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_vmake b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
new file mode 100755
index 0000000..2f7e729
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
new file mode 100755
index 0000000..ea67fd1
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
new file mode 100755
index 0000000..8019c2d
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
new file mode 100755
index 0000000..0dd84bc
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
@@ -0,0 +1,14 @@
+library verilog;
+use verilog.vl_types.all;
+entity counter_8 is
+    generic(
+        BIT_SZ          : integer := 8
+    );
+    port(
+        clock           : in     vl_logic;
+        enable          : in     vl_logic;
+        count           : out    vl_logic_vector
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
+end counter_8;
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
new file mode 100755
index 0000000..a7325bf
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm
new file mode 100755
index 0000000..3efd040
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm
diff --git a/part_2/ex5/simulation/modelsim/tb_counter b/part_2/ex5/simulation/modelsim/tb_counter
new file mode 100755
index 0000000..6256691
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/tb_counter
@@ -0,0 +1,9 @@
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
+run 1000
\ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/tb_counter.do b/part_2/ex5/simulation/modelsim/tb_counter.do
new file mode 100755
index 0000000..6256691
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/tb_counter.do
@@ -0,0 +1,9 @@
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
+run 1000
\ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/vsim.wlf b/part_2/ex5/simulation/modelsim/vsim.wlf
new file mode 100755
index 0000000..85c5422
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/vsim.wlf
diff --git a/part_2/ex5/verilog files/counter_8.v b/part_2/ex5/verilog files/counter_8.v
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/ex5/verilog files/counter_8.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog files/counter_8.v.bak b/part_2/ex5/verilog files/counter_8.v.bak
new file mode 100755
index 0000000..bcdbc6b
--- /dev/null
+++ b/part_2/ex5/verilog files/counter_8.v.bak
@@ -0,0 +1,22 @@
+timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog files/ex5.v b/part_2/ex5/verilog files/ex5.v
new file mode 100755
index 0000000..b4adca4
--- /dev/null
+++ b/part_2/ex5/verilog files/ex5.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module ex5(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog files/ex5.v.bak b/part_2/ex5/verilog files/ex5.v.bak
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/ex5/verilog files/ex5.v.bak
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog_files/counter_8.v b/part_2/ex5/verilog_files/counter_8.v
new file mode 100755
index 0000000..61bc861
--- /dev/null
+++ b/part_2/ex5/verilog_files/counter_8.v
@@ -0,0 +1,18 @@
+`timescale 1ns / 100ps

+

+module counter_8(clock,enable,count);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex5/verilog_files/counter_8.v.bak b/part_2/ex5/verilog_files/counter_8.v.bak
new file mode 100755
index 0000000..b45154a
--- /dev/null
+++ b/part_2/ex5/verilog_files/counter_8.v.bak
@@ -0,0 +1,22 @@
+`timescale 1ns / 100ps

+

+module counter_8(

+	clock,

+	enable,

+	count

+	);

+

+	parameter BIT_SZ = 8;

+	input clock;

+	input enable;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		if(enable == 1'b1)

+			count <= count + 1'b1;

+			

+endmodule
\ No newline at end of file