adding part 2 and 3

7 files changed, 42 insertions, 0 deletions

diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_info b/part_2/ex5/simulation/modelsim/rtl_work/_info
new file mode 100755
index 0000000..9a599cc
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_info
@@ -0,0 +1,25 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\simulation\modelsim
+vcounter_8
+!i10b 1
+!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
+Ia91@O_<g0BVIc?WTzTbB62
+Vdn7aTnOzPKdeZA;zmQ`Cl3
+Z1 dC:\New folder\simulation\modelsim
+w1479807538
+8C:/New folder/verilog_files/counter_8.v
+FC:/New folder/verilog_files/counter_8.v
+L0 3
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1479807676.024000
+!s107 C:/New folder/verilog_files/counter_8.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_vmake b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
new file mode 100755
index 0000000..2f7e729
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
new file mode 100755
index 0000000..ea67fd1
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
new file mode 100755
index 0000000..8019c2d
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
new file mode 100755
index 0000000..0dd84bc
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
@@ -0,0 +1,14 @@
+library verilog;
+use verilog.vl_types.all;
+entity counter_8 is
+    generic(
+        BIT_SZ          : integer := 8
+    );
+    port(
+        clock           : in     vl_logic;
+        enable          : in     vl_logic;
+        count           : out    vl_logic_vector
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
+end counter_8;
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
new file mode 100755
index 0000000..a7325bf
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm
new file mode 100755
index 0000000..3efd040
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm