adding part 2 and 3

19 files changed, 612 insertions, 0 deletions

diff --git a/part_2/ex9_final/verilog_files/LFSR.v b/part_2/ex9_final/verilog_files/LFSR.v
new file mode 100755
index 0000000..46140b2
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/LFSR.v
@@ -0,0 +1,18 @@
+module LFSR(CLK, en, COUNT);

+

+	input CLK;

+	input en;

+	

+	output [7:1] COUNT;

+	

+	reg [7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		if(en == 1'b1)

+			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		else

+			COUNT <= COUNT;

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/LFSR.v.bak b/part_2/ex9_final/verilog_files/LFSR.v.bak
new file mode 100755
index 0000000..89ec82a
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/LFSR.v.bak
@@ -0,0 +1,11 @@
+module LFSR(CLK, COUNT);

+	input CLK;

+	output[7:1] COUNT;

+	reg[7:1] COUNT;

+	initial COUNT = 7'd1;

+		

+	always @ (posedge CLK)

+		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};

+		

+endmodule

+	
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/add3_ge5.v b/part_2/ex9_final/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..a3cd6a9
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/add3_ge5.v
@@ -0,0 +1,34 @@
+//------------------------------

+// Module name: add3_ge5

+// Function: Add 3 to input if it is 5 or above

+// Creator:  Peter Cheung

+// Version:  1.0

+// Date:     21 Jan 2014

+//------------------------------

+

+module add3_ge5(iW,oA);

+

+ input [3:0] iW; 

+ output reg [3:0] oA;  

+ 

+	always @ (iW)

+		case (iW) 

+		//****** input <5, pass to output unchanged ******

+			4'b0000: oA <= 4'b0000; 

+			4'b0001: oA <= 4'b0001; 

+			4'b0010: oA <= 4'b0010; 

+			4'b0011: oA <= 4'b0011; 

+			4'b0100: oA <= 4'b0100;

+			

+		//****** input >=5, output = input + 3	******	

+			4'b0101: oA <= 4'b1000; 

+			4'b0110: oA <= 4'b1001; 

+			4'b0111: oA <= 4'b1010; 

+			4'b1000: oA <= 4'b1011; 

+			4'b1001: oA <= 4'b1100;

+			4'b1010: oA <= 4'b1101;	

+			4'b1011: oA <= 4'b1110;	

+			4'b1100: oA <= 4'b1111;	

+			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow

+		endcase 

+endmodule

diff --git a/part_2/ex9_final/verilog_files/bin2bcd_16.v b/part_2/ex9_final/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..b25d0bd
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/bin2bcd_16.v
@@ -0,0 +1,109 @@
+//------------------------------

+// Module name: bin2bcd_16

+// Function: Converts a 16-bit binary number to 5 digits BCD

+//            .... it uses a shift-and-add3 algorithm

+// Creator:  Peter Cheung

+// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)

+// Date:     24 Nov 2016

+//------------------------------

+//   For more explanation of how this work, see 

+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment

+

+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+

+	input [15:0]	B;		// binary input number

+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD

+	

+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;

+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;

+	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;

+	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;

+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;

+	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;

+

+	// Instantiate a tree of add3-if-greater than or equal to 5 cells

+	//  ... input is w_n, and output is a_n

+	add3_ge5 A1 (w1,a1);

+	add3_ge5 A2 (w2,a2);

+	add3_ge5 A3 (w3,a3);

+	add3_ge5 A4 (w4,a4);

+	add3_ge5 A5 (w5,a5);

+	add3_ge5 A6 (w6,a6);

+	add3_ge5 A7 (w7,a7);

+	add3_ge5 A8 (w8,a8);

+	add3_ge5 A9 (w9,a9);

+	add3_ge5 A10 (w10,a10);

+	add3_ge5 A11 (w11,a11);

+	add3_ge5 A12 (w12,a12);

+	add3_ge5 A13 (w13,a13);

+	add3_ge5 A14 (w14,a14);

+	add3_ge5 A15 (w15,a15);

+	add3_ge5 A16 (w16,a16);

+	add3_ge5 A17 (w17,a17);

+	add3_ge5 A18 (w18,a18);

+	add3_ge5 A19 (w19,a19);

+	add3_ge5 A20 (w20,a20);

+	add3_ge5 A21 (w21,a21);

+	add3_ge5 A22 (w22,a22);

+	add3_ge5 A23 (w23,a23);

+	add3_ge5 A24 (w24,a24);

+	add3_ge5 A25 (w25,a25);

+	add3_ge5 A26 (w26,a26);

+	add3_ge5 A27 (w27,a27);

+	add3_ge5 A28 (w28,a28);

+	add3_ge5 A29 (w29,a29);

+	add3_ge5 A30 (w30,a30);

+	add3_ge5 A31 (w31,a31);

+	add3_ge5 A32 (w32,a32);

+	add3_ge5 A33 (w33,a33);

+	add3_ge5 A34 (w34,a34);

+	add3_ge5 A35 (w35,a35);

+		

+	// wire the tree of add3 modules together

+	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n

+	assign  w2 = {a1[2:0], B[12]};		

+	assign  w3 = {a2[2:0], B[11]};		

+	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};

+	assign  w5 = {a3[2:0], B[10]};

+	assign  w6 = {a4[2:0], a5[3]};

+	assign  w7 = {a5[2:0], B[9]};

+	assign  w8 = {a6[2:0], a7[3]};

+	assign  w9 = {a7[2:0], B[8]};

+	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};

+	assign  w11 = {a8[2:0], a9[3]};

+	assign  w12 = {a9[2:0], B[7]};

+	assign  w13 = {a10[2:0], a11[3]};

+	assign  w14 = {a11[2:0], a12[3]};

+	assign  w15 = {a12[2:0], B[6]};

+	assign  w16 = {a13[2:0], a14[3]};

+	assign  w17 = {a14[2:0], a15[3]};

+	assign  w18 = {a15[2:0], B[5]};

+	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};

+	assign  w20 = {a16[2:0], a17[3]};

+	assign  w21 = {a17[2:0], a18[3]};

+	assign  w22 = {a18[2:0], B[4]};

+	assign  w23 = {a19[2:0], a20[3]};

+	assign  w24 = {a20[2:0], a21[3]};

+	assign  w25 = {a21[2:0], a22[3]};

+	assign  w26 = {a22[2:0], B[3]};

+	assign  w27 = {a23[2:0], a24[3]};

+	assign  w28 = {a24[2:0], a25[3]};

+	assign  w29 = {a25[2:0], a26[3]};

+	assign  w30 = {a26[2:0], B[2]};

+	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};

+	assign  w32 = {a27[2:0], a28[3]};

+	assign  w33 = {a28[2:0], a29[3]};

+	assign  w34 = {a29[2:0], a30[3]};

+	assign  w35 = {a30[2:0], B[1]};

+	

+	// connect up to four BCD digit outputs	

+	assign BCD_0 = {a35[2:0],B[0]};

+	assign BCD_1 = {a34[2:0],a35[3]};

+	assign BCD_2 = {a33[2:0],a34[3]};

+	assign BCD_3 = {a32[2:0],a33[3]};

+	assign BCD_4 = {a31[2:0],a32[3]};	

+endmodule

+

+	

+	

+

diff --git a/part_2/ex9_final/verilog_files/counter_16.v b/part_2/ex9_final/verilog_files/counter_16.v
new file mode 100755
index 0000000..79c144c
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/counter_16.v
@@ -0,0 +1,31 @@
+module counter_16(clock, start, stop, count);

+

+	parameter BIT_SZ = 16;

+	input clock, start, stop;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	reg state;

+	

+	parameter COUNTING = 1'b1, IDLE = 1'b0;

+	

+	initial count = 0;

+	initial state = IDLE;

+	

+	always @ (posedge clock)

+		case(state)

+			IDLE:

+				if(start == 1'b1)

+					begin

+						count = 0;

+						state = COUNTING;

+					end

+			COUNTING:

+				if(stop == 1'b1)

+					state <= IDLE;

+				else

+					count <= count + 1'b1;

+		endcase

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/counter_16.v.bak b/part_2/ex9_final/verilog_files/counter_16.v.bak
new file mode 100755
index 0000000..c0ec549
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/counter_16.v.bak
@@ -0,0 +1,21 @@
+`timescale 1ns / 100ps

+

+module counter_16(clock,enable,reset,count);

+

+	parameter BIT_SZ = 16;

+	input clock, enable, reset;

+	output [BIT_SZ-1:0] count;

+	

+	reg [BIT_SZ-1:0] count;

+	

+	initial count = 0;

+	

+	always @ (posedge clock)

+		begin

+			if(enable == 1'b1)

+				count <= count + 1'b1;

+			if(reset == 1'b1)

+				count <= 16'b0;

+		end

+			

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/delay.v b/part_2/ex9_final/verilog_files/delay.v
new file mode 100755
index 0000000..a983085
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/delay.v
@@ -0,0 +1,60 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 14;

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+				begin

+					count <= N*128;

+					state <= COUNTING;

+				end

+			COUNTING: 

+				begin

+					if(count == 1'b0)

+						begin

+							state <= TIME_OUT;

+						end

+					else 

+						count <= count - 1'b1;

+				end

+			TIME_OUT: 

+				begin

+					if(trigger == 1'b0)

+						state <= IDLE;

+					else

+						state <= WAIT_LOW;

+				end

+			WAIT_LOW: 

+				if(trigger == 1'b0)

+					state <= IDLE;

+			default: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE:

+					time_out = 1'b0;

+			COUNTING: 

+					time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/delay.v.bak b/part_2/ex9_final/verilog_files/delay.v.bak
new file mode 100755
index 0000000..7b79342
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/delay.v.bak
@@ -0,0 +1,47 @@
+module delay(clk, N, trigger, time_out);

+

+	parameter BIT_SZ = 7

+

+	input clk, trigger;

+	input [BIT_SZ-1:0] N;

+	output time_out;

+

+	reg[BIT_SZ-1:0] count;

+	reg time_out;

+

+	reg [1:0] state;

+

+	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;

+

+	initial begin

+		state = IDLE;

+		count = N-1'b1;

+	end

+	

+	always @ (posedge clk)

+		case(state)

+			IDLE: if(trigger == 1'b1)

+					state <= COUNTING;

+			COUNTING: if(count == 1'b0) begin

+					count <= n - 1'b1;

+					state <= TIME_OUT;

+				end

+			TIME_OUT: if(trigger == 1'b0)

+					state <= IDLE;

+				else

+					state <= WAIT_LOW;

+			WAIT_LOW: if(trigger == 1'b0)

+					state <= IDLE;

+			defualt: ;

+		endcase

+		

+	always @ (*)

+		case(state)

+			IDLE: time_out = 1'b0;

+			COUNTING: time_out = 1'b0;

+			TIME_OUT: time_out = 1'b1;

+			WAIT_LOW: time_out = 1'b0;

+			default: ;

+		endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex8.v b/part_2/ex9_final/verilog_files/ex8.v
new file mode 100755
index 0000000..6ca51d6
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex8.v
@@ -0,0 +1,23 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex8.v.bak b/part_2/ex9_final/verilog_files/ex8.v.bak
new file mode 100755
index 0000000..ac293e7
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex8.v.bak
@@ -0,0 +1 @@
+module ex8(
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex9.v b/part_2/ex9_final/verilog_files/ex9.v
new file mode 100755
index 0000000..15446c2
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex9.v
@@ -0,0 +1,33 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	wire [15:0] count_out;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	

+	formula_fsm FSM(tick_ms, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	

+	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);

+	

+	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	hex_to_7seg SEG3(HEX3, BCD_3);

+	hex_to_7seg SEG4(HEX4, BCD_4);

+	hex_to_7seg SEG5(HEX5, 4'b0);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex9.v.bak b/part_2/ex9_final/verilog_files/ex9.v.bak
new file mode 100755
index 0000000..6ca51d6
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/ex9.v.bak
@@ -0,0 +1,23 @@
+module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);

+	

+	input CLOCK_50;

+	input [3:0] KEY;

+	output [9:0] LEDR;

+	output [6:0] HEX0, HEX1, HEX2;

+	

+	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;

+	wire [6:0] N;

+	wire [6:0] bcd_to_hex;

+	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;

+	

+	tick_50000 TICK0(CLOCK_50, tick_ms);

+	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);

+	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);

+	LFSR LFSR0(tick_ms, en_lfsr, N);

+	delay DEL0(tick_ms, N, start_delay, time_out);

+	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);

+	hex_to_7seg SEG0(HEX0, BCD_0);

+	hex_to_7seg SEG1(HEX1, BCD_1);

+	hex_to_7seg SEG2(HEX2, BCD_2);

+	

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/formula_fsm.v b/part_2/ex9_final/verilog_files/formula_fsm.v
new file mode 100755
index 0000000..2a79785
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/formula_fsm.v
@@ -0,0 +1,76 @@
+module formula_fsm(clk, trigger, time_out, en_lfsr, start_delay, ledr);

+

+input clk, time_out, trigger;

+output en_lfsr, start_delay;

+output [9:0] ledr;

+

+reg [1:0] state;

+reg led_on, en_lfsr, start_delay;

+reg [9:0] ledr;

+reg [11:0] count;

+

+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;

+

+initial 

+	begin

+		state = WAIT_TRIGGER;

+		en_lfsr = 1'b0;

+		start_delay = 1'b0;

+		count = 12'd2499;

+	end

+

+always @ (posedge clk)

+	case(state)

+		WAIT_TRIGGER: 

+			begin

+				if(trigger == 1'b1)

+					state <= LIGHT_UP_LEDS;

+			end

+		LIGHT_UP_LEDS:

+				if(ledr == 10'h3ff)

+					state <= WAIT_FOR_TIMEOUT;

+		WAIT_FOR_TIMEOUT:

+				if(time_out == 1'b1)

+					 state <= WAIT_TRIGGER;

+		default: ;

+	endcase

+

+always @ (posedge clk)

+	case(state)

+		WAIT_TRIGGER:

+			ledr = 0;

+		LIGHT_UP_LEDS:

+			begin

+				if(count == 1'b0)

+					begin

+						ledr <= {ledr[8:0], 1'b1};

+						count <= 12'd2499;

+					end

+				else

+					begin

+						count <= count - 1'b1;

+					end

+			end

+		default: count <= 12'd2499;

+	endcase

+	

+always @ (*)

+	case(state)

+		WAIT_TRIGGER:

+			begin

+				en_lfsr = 1'b0;

+				start_delay = 1'b0;

+			end

+		LIGHT_UP_LEDS:

+			begin

+				en_lfsr = 1'b1;

+			end

+		WAIT_FOR_TIMEOUT:

+			begin

+				start_delay = 1'b1;

+				en_lfsr = 1'b0;

+			end

+		default: ;

+	endcase

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/formula_fsm.v.bak b/part_2/ex9_final/verilog_files/formula_fsm.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/formula_fsm.v.bak
diff --git a/part_2/ex9_final/verilog_files/hex_to_7seg.v b/part_2/ex9_final/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);

+

+	output [6:0] out;

+	input [3:0] in;

+	

+	reg [6:0] out;

+	

+	always @ (*)

+		case(in)

+			4'h0: out = 7'b1000000;

+			4'h1: out = 7'b1111001;

+			4'h2: out = 7'b0100100;

+			4'h3: out = 7'b0110000;

+			4'h4: out = 7'b0011001;

+			4'h5: out = 7'b0010010;

+			4'h6: out = 7'b0000010;

+			4'h7: out = 7'b1111000;

+			4'h8: out = 7'b0000000;

+			4'h9: out = 7'b0011000;

+			4'ha: out = 7'b0001000;

+			4'hb: out = 7'b0000011;

+			4'hc: out = 7'b1000110;

+			4'hd: out = 7'b0100001;

+			4'he: out = 7'b0000110;

+			4'hf: out = 7'b0001110;

+		endcase

+endmodule

diff --git a/part_2/ex9_final/verilog_files/tick_2500.v b/part_2/ex9_final/verilog_files/tick_2500.v
new file mode 100755
index 0000000..e75a131
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_2500.v
@@ -0,0 +1,35 @@
+module tick_2500(CLOCK_IN, en, CLK_OUT);

+

+	parameter NBIT = 12;

+	

+	input CLOCK_IN, en;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 12'd2499;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		if(en == 1'b1)

+			begin

+				if(count == 1'b0)

+					begin

+						CLK_OUT <= 1'b1;

+						count <= 12'd2499;

+					end

+				else

+					begin

+						count <= count - 1'b1;

+						CLK_OUT <= 1'b0;

+					end

+			end

+		else 

+			CLK_OUT <= 1'b0;

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/tick_2500.v.bak b/part_2/ex9_final/verilog_files/tick_2500.v.bak
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_2500.v.bak
diff --git a/part_2/ex9_final/verilog_files/tick_50000.v b/part_2/ex9_final/verilog_files/tick_50000.v
new file mode 100755
index 0000000..7ccc81b
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_50000.v
@@ -0,0 +1,32 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd49999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= 1'b1;

+					count <= 16'd49999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+					CLK_OUT <= 1'b0;

+				end

+		end

+

+endmodule
\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/tick_50000.v.bak b/part_2/ex9_final/verilog_files/tick_50000.v.bak
new file mode 100755
index 0000000..45c4166
--- /dev/null
+++ b/part_2/ex9_final/verilog_files/tick_50000.v.bak
@@ -0,0 +1,31 @@
+module tick_50000(CLOCK_IN, CLK_OUT);

+

+	parameter NBIT = 16;

+	

+	input CLOCK_IN;

+	output CLK_OUT;

+	

+	reg [NBIT-1:0] count;

+	

+	reg CLK_OUT;

+	

+	initial 

+		begin

+			count = 16'd24999;

+			CLK_OUT = 1'b0;

+		end

+	

+	always @ (posedge CLOCK_IN)

+		begin

+			if(count == 16'b0)

+				begin

+					CLK_OUT <= ~CLK_OUT;

+					count <= 16'd24999;

+				end

+			else

+				begin

+					count <= count - 1'b1;

+				end

+		end

+

+endmodule
\ No newline at end of file