| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
|
|
| |
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
|
|
|
|
| |
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
|
| |
|
|
|
|
| |
removed on Ctrl-C
|
| |
|
| |
|
| |
|
|
|
|
| |
a5971eca338
|
| |
|
|\ |
|
| | |
|
| | |
|
| | |
|
|/ |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
|
|
|
|
|
| |
Verilator doesn't handle verilog code that deals with time, such
as delayed signals or the repeat task. Clock and reset generation
are therefore moved to a separate file that can be replaced by
a verilator module. VCD generation is also affected by this.
|
|
|
|
|
| |
This commit also adds support for setting the AXI_TEST and VERBOSE
defines as plusargs or parameters
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|