| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix CodeGen bug and add more property tests | Yann Herklotz Grave | 2019-02-16 | 2 | -2/+2 |
| * | Fix to parser | Yann Herklotz Grave | 2019-02-16 | 2 | -44/+39 |
| * | Fix lint errors | Yann Herklotz Grave | 2019-02-16 | 1 | -4/+3 |
| * | Change to Parsec and add Lexer | Yann Herklotz Grave | 2019-02-16 | 3 | -64/+280 |
| * | Change Port type, adding signed info | Yann Herklotz Grave | 2019-02-16 | 6 | -33/+47 |
| * | Fix lint errors | Yann Herklotz Grave | 2019-02-16 | 3 | -10/+9 |
| * | Add export lists | Yann Herklotz Grave | 2019-02-16 | 5 | -24/+41 |
| * | Fix warnings for -Wall | Yann Herklotz Grave | 2019-02-16 | 1 | -2/+0 |
| * | Add Parser to library | Yann Herklotz Grave | 2019-02-16 | 1 | -0/+2 |
| * | Add number parsing | Yann Herklotz Grave | 2019-02-16 | 1 | -8/+37 |
| * | Add expression parsing | Yann Herklotz Grave | 2019-02-15 | 1 | -75/+96 |
| * | Take out non synthesisable comparison | Yann Herklotz Grave | 2019-02-15 | 1 | -2/+2 |
| * | Fix all warnings | Yann Herklotz Grave | 2019-02-15 | 3 | -7/+9 |
| * | Add expression to parser | Yann Herklotz Grave | 2019-02-13 | 1 | -4/+111 |
| * | Fix parser build errorsv0.1.1.0 | Yann Herklotz Grave | 2019-02-11 | 1 | -1/+1 |
| * | Fix versions and tests | Yann Herklotz Grave | 2019-02-11 | 1 | -4/+0 |
| * | Fix reduce build | Yann Herklotz Grave | 2019-02-11 | 1 | -2/+1 |
| * | Add simple parser | Yann Herklotz Grave | 2019-02-11 | 1 | -0/+25 |
| * | Fix reducer | Yann Herklotz Grave | 2019-02-11 | 1 | -1/+1 |
| * | Fix tests in Mutate.hs | Yann Herklotz Grave | 2019-02-09 | 1 | -3/+16 |
| * | Also fix ModCA issue for Mutate.hs | Yann Herklotz | 2019-02-08 | 1 | -1/+47 |
| * | Remove _ModCA and replace it by modContAssign | Yann Herklotz | 2019-02-08 | 1 | -1/+1 |
| * | Add Data derivations to AST and Plated instance to Expr | Yann Herklotz | 2019-02-08 | 1 | -26/+42 |
| * | Move simulation into library | Yann Herklotz | 2019-02-08 | 1 | -1/+89 |
| * | Add Reduce which will contain the test reduction | Yann Herklotz | 2019-02-08 | 1 | -0/+29 |
| * | Set the timeout to 5 mins | Yann Herklotz | 2019-02-07 | 1 | -2/+2 |
| * | Add runner for verilog file | Yann Herklotz | 2019-02-07 | 1 | -3/+10 |
| * | Reduce the timeout | Yann Herklotz | 2019-02-07 | 1 | -3/+7 |
| * | Remove divide and mod from the generator list | Yann Herklotz | 2019-02-07 | 1 | -2/+2 |
| * | [Fix #21] Fix type signature to bytestring | Yann Herklotz | 2019-02-05 | 1 | -4/+4 |
| * | Add hashing of bytestring output | Yann Herklotz | 2019-02-05 | 1 | -16/+18 |
| * | Add conversion to bytestring | Yann Herklotz | 2019-02-05 | 1 | -6/+35 |
| * | Small fixes to module generation | Yann Herklotz | 2019-02-03 | 1 | -4/+7 |
| * | Fix logging | Yann Herklotz | 2019-02-03 | 2 | -2/+3 |
| * | Add timeout and timeout check | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Reset Xst and Yosys default | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Try to add logging | Yann Herklotz | 2019-02-02 | 5 | -16/+30 |
| * | Add mutation for declaration | Yann Herklotz | 2019-02-02 | 1 | -0/+5 |
| * | Add mutation to declare other wires | Yann Herklotz | 2019-02-02 | 1 | -7/+28 |
| * | Add brackets around number | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Add case for empty context | Yann Herklotz | 2019-02-02 | 1 | -0/+5 |
| * | Remove last warning | Yann Herklotz | 2019-02-01 | 1 | -1/+4 |
| * | Small warning fix | Yann Herklotz | 2019-02-01 | 1 | -1/+1 |
| * | Fix all the compile and test errors | Yann Herklotz | 2019-02-01 | 11 | -47/+66 |
| * | Fix imports | Yann Herklotz | 2019-02-01 | 13 | -57/+61 |
| * | Rename XST and add imports | Yann Herklotz | 2019-02-01 | 2 | -20/+32 |
| * | Fix internal modules | Yann Herklotz | 2019-02-01 | 1 | -1/+11 |
| * | More restructuring | Yann Herklotz | 2019-02-01 | 15 | -130/+26 |
| * | Structure changes | Yann Herklotz | 2019-02-01 | 8 | -14/+49 |
| * | Add back Show for tests | Yann Herklotz | 2019-02-01 | 1 | -21/+21 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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