verilog - Repository with some Verilog designs used to learn Verilog simulation.

	Commit message (Collapse)	Author	Age	Files	Lines
*	adding muxHEAD master	zedarider	2016-05-09	1	-1/+1
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*	Merge branch 'master' of https://github.com/zedarider/verilog	zedarider	2016-05-09	432	-37/+239923
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\| *	adding Quartus files	unknown	2016-05-07	432	-37/+239923
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* \|	adding mux	zedarider	2016-05-09	1	-0/+84
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*	adding column_chooser	zedarider	2016-05-07	1	-0/+77
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*	adding all files	zedarider	2016-05-06	2	-0/+40
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*	adding project verilog file for row detection	zedarider	2016-05-05	2	-0/+43
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*	Put into Folder	zedarider	2016-03-01	2	-0/+0
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*	adding HelloWorld Demo	zedarider	2016-03-01	1	-0/+0
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*	adding HelloWorld Demo	zedarider	2016-03-01	1	-8/+0
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*	adding HelloWorld Demo	zedarider	2016-03-01	4	-0/+38
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*	Update README.md	Yann Herklotz	2016-03-01	1	-1/+3
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*	Initial commit	Yann Herklotz	2016-03-01	1	-0/+1