| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Also fix ModCA issue for Mutate.hs | Yann Herklotz | 2019-02-08 | 1 | -1/+47 |
| * | Remove _ModCA and replace it by modContAssign | Yann Herklotz | 2019-02-08 | 1 | -1/+1 |
| * | Add Data derivations to AST and Plated instance to Expr | Yann Herklotz | 2019-02-08 | 1 | -26/+42 |
| * | Move simulation into library | Yann Herklotz | 2019-02-08 | 1 | -1/+89 |
| * | Add Reduce which will contain the test reduction | Yann Herklotz | 2019-02-08 | 1 | -0/+29 |
| * | Set the timeout to 5 mins | Yann Herklotz | 2019-02-07 | 1 | -2/+2 |
| * | Add runner for verilog file | Yann Herklotz | 2019-02-07 | 1 | -3/+10 |
| * | Reduce the timeout | Yann Herklotz | 2019-02-07 | 1 | -3/+7 |
| * | Remove divide and mod from the generator list | Yann Herklotz | 2019-02-07 | 1 | -2/+2 |
| * | [Fix #21] Fix type signature to bytestring | Yann Herklotz | 2019-02-05 | 1 | -4/+4 |
| * | Add hashing of bytestring output | Yann Herklotz | 2019-02-05 | 1 | -16/+18 |
| * | Add conversion to bytestring | Yann Herklotz | 2019-02-05 | 1 | -6/+35 |
| * | Small fixes to module generation | Yann Herklotz | 2019-02-03 | 1 | -4/+7 |
| * | Fix logging | Yann Herklotz | 2019-02-03 | 2 | -2/+3 |
| * | Add timeout and timeout check | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Reset Xst and Yosys default | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Try to add logging | Yann Herklotz | 2019-02-02 | 5 | -16/+30 |
| * | Add mutation for declaration | Yann Herklotz | 2019-02-02 | 1 | -0/+5 |
| * | Add mutation to declare other wires | Yann Herklotz | 2019-02-02 | 1 | -7/+28 |
| * | Add brackets around number | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Add case for empty context | Yann Herklotz | 2019-02-02 | 1 | -0/+5 |
| * | Remove last warning | Yann Herklotz | 2019-02-01 | 1 | -1/+4 |
| * | Small warning fix | Yann Herklotz | 2019-02-01 | 1 | -1/+1 |
| * | Fix all the compile and test errors | Yann Herklotz | 2019-02-01 | 11 | -47/+66 |
| * | Fix imports | Yann Herklotz | 2019-02-01 | 13 | -57/+61 |
| * | Rename XST and add imports | Yann Herklotz | 2019-02-01 | 2 | -20/+32 |
| * | Fix internal modules | Yann Herklotz | 2019-02-01 | 1 | -1/+11 |
| * | More restructuring | Yann Herklotz | 2019-02-01 | 15 | -130/+26 |
| * | Structure changes | Yann Herklotz | 2019-02-01 | 8 | -14/+49 |
| * | Add back Show for tests | Yann Herklotz | 2019-02-01 | 1 | -21/+21 |
| * | [Fix #28] Add Expression generation with context | Yann Herklotz | 2019-02-01 | 1 | -16/+29 |
| * | [Fix #27] Add function to Expr and add Generation type | Yann Herklotz | 2019-02-01 | 2 | -22/+54 |
| * | [Fix #24] Small changes and looked at always block output | Yann Herklotz | 2019-02-01 | 1 | -7/+9 |
| * | Make code a bit more readable | Yann Herklotz | 2019-02-01 | 1 | -1/+2 |
| * | Remove extra import | Yann Herklotz | 2019-02-01 | 1 | -1/+0 |
| * | Add echo do all the simulators | Yann Herklotz | 2019-01-23 | 3 | -0/+9 |
| * | Add better echo | Yann Herklotz | 2019-01-23 | 1 | -5/+14 |
| * | Better AST generation from DAG | Yann Herklotz | 2019-01-23 | 1 | -1/+4 |
| * | Better multithreading | Yann Herklotz | 2019-01-22 | 4 | -8/+12 |
| * | Make where clause nicer | Yann Herklotz | 2019-01-22 | 1 | -2/+4 |
| * | [Fix #22] Fix SAT solver equivalence checking | Yann Herklotz | 2019-01-20 | 3 | -4/+40 |
| * | [Fix #26] Add support for SymbiYosys | Yann Herklotz | 2019-01-20 | 2 | -4/+10 |
| * | Prettify files | Yann Herklotz | 2019-01-20 | 6 | -19/+37 |
| * | Add sby config | Yann Herklotz | 2019-01-20 | 1 | -5/+45 |
| * | Add template file | Yann Herklotz | 2019-01-20 | 4 | -47/+72 |
| * | Rename moduleId to modId | Yann Herklotz | 2019-01-20 | 7 | -22/+33 |
| * | Reformat with stylish-haskell | Yann Herklotz | 2019-01-19 | 15 | -87/+70 |
| * | Add hlint changes | Yann Herklotz | 2019-01-19 | 3 | -4/+3 |
| * | Set column to 100 | Yann Herklotz | 2019-01-19 | 9 | -83/+31 |
| * | Add brittany formatting instead of stylish-haskell | Yann Herklotz | 2019-01-19 | 17 | -290/+387 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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