verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
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*	Add helper function to turn port into expr	Yann Herklotz	2019-01-01	1	-0/+3
*	Add monoid instance for LVal	Yann Herklotz	2019-01-01	1	-1/+10
*	Fix Monoid instance for Expr	Yann Herklotz	2019-01-01	1	-1/+1
*	Add back monoid instance for statement	Yann Herklotz	2019-01-01	1	-0/+3
*	Fix logic in CodeGen with maybe	Yann Herklotz	2019-01-01	1	-2/+4
*	Fix linting warnings	Yann Herklotz	2019-01-01	8	-16/+14
*	Formatting	Yann Herklotz	2019-01-01	1	-3/+3
*	Remove empty statement and Monoid instance	Yann Herklotz	2019-01-01	1	-4/+0
*	Fix Semigroup instances	Yann Herklotz	2019-01-01	1	-4/+8
*	Use Monoid Statement instance to make code more concise	Yann Herklotz	2019-01-01	1	-5/+3
*	Add documentation	Yann Herklotz	2019-01-01	1	-0/+10
*	Add string instance to expression	Yann Herklotz	2019-01-01	1	-12/+42
*	Add missing case in function	Yann Herklotz	2018-12-31	1	-0/+2
*	Add show instance and add concat to reglval	Yann Herklotz	2018-12-31	4	-42/+88
*	Fix build errors	Yann Herklotz	2018-12-31	2	-2/+5
*	Remove sep and fromList in favour of fold	Yann Herklotz	2018-12-31	3	-26/+7
*	Separate arbitrary from types	Yann Herklotz	2018-12-31	1	-0/+184
*	Adding code to Icarus	Yann Herklotz	2018-12-31	1	-3/+15
*	Large refactor	Yann Herklotz	2018-12-31	7	-326/+149
*	Finish module instantiation	Yann Herklotz	2018-12-31	2	-5/+16
*	Add direction to Decl and add doctest	Yann Herklotz	2018-12-31	4	-11/+26
*	[Fix #17] Add size to ports	Yann Herklotz	2018-12-31	2	-5/+13
*	Add doctest test	Yann Herklotz	2018-12-31	1	-0/+8
*	[Fix #13, Fix #15] Fix type errors and add inst functions	Yann Herklotz	2018-12-30	4	-14/+17
*	Change modPort type from Maybe to List	Yann Herklotz	2018-12-30	1	-1/+1
*	[Fix #14] Add size to Port type	Yann Herklotz	2018-12-30	4	-14/+23
*	Move helper functions	Yann Herklotz	2018-12-30	3	-5/+7
*	Add remove duplicates	Yann Herklotz	2018-12-29	2	-6/+18
*	Add internal function for fix	Yann Herklotz	2018-12-29	1	-0/+6
*	Fix verilog output for output port	Yann Herklotz	2018-12-29	1	-1/+1
*	Add alternative generation method	Yann Herklotz	2018-12-29	1	-0/+29
*	Add new generation method	Yann Herklotz	2018-12-29	1	-14/+14
*	Style changes	Yann Herklotz	2018-12-29	1	-7/+7
*	Make generation more controlled	Yann Herklotz	2018-12-29	1	-2/+4
*	Rearrange instances	Yann Herklotz	2018-12-29	1	-5/+5
*	Changes to the API	Yann Herklotz	2018-12-29	5	-43/+60
*	Add simulator code	Yann Herklotz	2018-12-29	3	-8/+24
*	Fix documentation and copyright	Yann Herklotz	2018-12-28	17	-51/+51
*	Add simulator module	Yann Herklotz	2018-12-28	5	-0/+215
*	Fix imports and cabal file	Yann Herklotz	2018-12-28	3	-16/+13
*	Move verilog files into specific module	Yann Herklotz	2018-12-28	4	-21/+104
*	Add instantiation function	Yann Herklotz	2018-12-27	1	-2/+7
*	Remove OverloadedStrings in favour of declaration in module	Yann Herklotz	2018-12-27	5	-10/+1
*	Format fixes	Yann Herklotz	2018-12-27	1	-20/+20
*	Small style change	Yann Herklotz	2018-12-27	1	-1/+1
*	Improve expression and statement generation	Yann Herklotz	2018-12-27	1	-20/+96
*	Add documentation to main module	Yann Herklotz	2018-12-25	1	-0/+13
*	Add code generation for new types	Yann Herklotz	2018-12-25	1	-20/+130
*	Type fixes	Yann Herklotz	2018-12-25	1	-7/+8
*	Rename Node to Int	Yann Herklotz	2018-12-25	1	-1/+1