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diff --git a/part_1/README.md b/part_1/README.md deleted file mode 100644 index 03d35be..0000000 --- a/part_1/README.md +++ /dev/null @@ -1,226 +0,0 @@ -# Experiment VERI: FPGA Design with Verilog (Part 1) - -In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1-SoC Board that was made by Terasica. We will be using verilog in Quartus II to program the FPGA. - - -## Experiment 1: Schematic capture using Quartus II -- 7-Segment Display - - -### Introduction - -We first downloaded the solution for Exercise 1 and tried programming the FPGA using the Programmer from Quartus. The software didn't detect the DE1-SoC board and we had to turn it off and on again for the DE-SOC [USB-1] to appear. After we then added the right type of FPGA to the project (5CSEMA5) and deleted the ARM processor from the programmer window (SOCVHPS) we were able to add the solution to the FPGA and download it onto the board. - - -### Using Block Diagram - -We then used the truth table for the 7-Segment Decoder to create the K-map for the output number 4, so that we can extract the Sum of Products form from the K-map. We then added the missing output to the incomplete block diagram. - - - -We then created a new block diagram, and made a symbol file for the 7-Segment Decoder, so that we can include it in this block diagram. We then made this block diagram our top-level design. This is the file that will make the whole project work on the FPGA and will be programmed onto the FPGA. The other file is just a schematic file that describes how the block in the top level design works. - - - -We then compiled the Quartus project to see if there are any errors in the files, and then we added the pin assignments using the Pin Planner. - - - -Finally we compiled the project and downloaded it onto the FPGA and it worked like the solution. Using the block diagram to create the project took a lot of time though and it would have been much easier to make the project in Verilog as it would have taken much less time and effort. We also wouldn't have had to create the Karnaugh maps to simplify the design and be able to implement it in the block diagram, because in Verilog we only need to implement the truth table. It is also much quicker to type than drag the wires from logic element to logic element and trying to find the different logic elements in the list of IPs that come with Quartus II. Verilog is also much more flexible, as we can define the 7-Segment Decoder in different ways (behaviourly or structurally). - - -### Propagation Delays from inputs to outputs - -To analyze the propagation delays from inputs to outputs we used the TimeQuest Timing Analyzer to create a table that contains all the propagation delays of all the inputs and outputs. First we looked at the propagation delay under the conditions "Slow 1100mV 0°C". This gave the following table. - -__Slow 1100mV 0°C TimeQuest Timing Analyzer Table__ - - - - -Then for the second table we used the "Slow 1100mV 85°C" TimeQuest Analysis and got a slightly different table from it. - - -__Slow 1100mV 85°C TimeQuest Timing Analyzer Table__ - - - - -The output on these tables shows the propagation delays from the inputs to the outputs. The 4 different rows have 4 different abreviations RR, RF, FR and FF, that stand for Rise-Rise, Rise-Fall, Fall-Rise and Fall-Fall respectively. These describe the time it takes for the signal to travel from a rise or fall of the signal to produce a rise or fall in the output signal. There are some boxes in the table that do not have a time in there, this is because these connections never happen and therefore the FPGA simplifies them and does not even connect them, and therefore they do not have a time. The times are also measured in nanoseconds. - -With the help of these tables we can observe that when the FPGA is at 85°C, the times between the inputs and outputs is higher than when the FPGA is cooled at 0°C. This can be explained by how fast the gates switch due to the transistor voltages switching. The switching time increases as the temperature increases and therefore the time between the inputs and outputs will increase as well. - - -## Experiment 2: 7-Segment Decoder in Verilog HDL - - -As modern digital designers do not use schematics anymore to design hardware it is much more useful to learn how to describe the hardware using a Hardware Description Language (HDL) such as VHDL or Verilog HDL. - -We typed the code for the 7-Segment Decoder in Quartus and created the module as shown below. - -```verilog -module hex_to_7seg (out, in); - - output [6:0] out; - input [3:0] in; - - reg [6:0] out; - - always @ (*) - case(in) - 4'h0: out = 7'b1000000; - 4'h1: out = 7'b1111001; - 4'h2: out = 7'b0100100; - 4'h3: out = 7'b0110000; - 4'h4: out = 7'b0011001; - 4'h5: out = 7'b0010010; - 4'h6: out = 7'b0000010; - 4'h7: out = 7'b1111000; - 4'h8: out = 7'b0000000; - 4'h9: out = 7'b0011000; - 4'ha: out = 7'b0001000; - 4'hb: out = 7'b0000011; - 4'hc: out = 7'b1000110; - 4'hd: out = 7'b0100001; - 4'he: out = 7'b0000110; - 4'hf: out = 7'b0001110; - endcase -endmodule -``` - -Then we created a top level design file in Verilog as well. This process is much faster than doing everything using schematics as one can easily edit the file and change parameters easily as well. It is also much easier to get an overview of the project as complicated schematic files are very hard to read. The code for the top level design can be seen below. - -```verilog -module ex2(SW, HEX0); - - input [3:0] SW; - output [6:0] HEX0; - - hex_to_7seg SEG0(HEX0, SW); - -endmodule -``` - -We checked the syntax of the files and then ran analysis and elaboration which returns early errors that we made while writing the verilog and in the logic of the design. We then added the pin assignments in text directly in the "ex1.qsf" file which is also so much faster than using the Pin Planner as we can just copy and paste the pin assignments into our other projects that we are going to create in the future and won't have to waste time on using the Pin Planner and looking up the names of all the pins that we wanted to use. - -We then put the module into our mylib folder so that we can reuse the code in later projects. This is also another advantage of using Verilog instead of schematics as the code can easily be reused in other projects and even in other FPGAs as Verilog only describes the hardware and the program that has to program the FPGA is in charge of implementing it. - - -## Experiment 3: 10-bit binary switch values on three 7-Segment Displays - - -A 10-bit binary switch display program will collect all the input bits from the switches and output them to the 3 7-Segment Displays. This just means that we have to split up the 10 bits into groups of 4, as this gives the value for one hexadecimal number to be displayed. This will give two 4-bit hexadecimal numbers and one 2-bit hexadecimal number where we can just set the two most significant bits to 0. - -For this project we had to create a new top-level design file, howver we were able to reuse our 7-Segment Decoder code that we wrote for Experiment 2. Apart from that we didn't have to create any other module for this Experiment as the 7-Segment Decoders are just going to display the hexadecimal values of the switches, which does not require any converting. The code that we wrote for the top level design is shown below. - -```verilog -module ex3(SW, HEX0, HEX1, HEX2); - - input [9:0] SW; - output [6:0] HEX0; - output [6:0] HEX1; - output [6:0] HEX2; - - hex_to_7seg SEG0 (HEX0, SW[3:0]); - hex_to_7seg SEG1 (HEX1, SW[7:4]); - hex_to_7seg SEG2 (HEX2, SW[9:8]); - -endmodule -``` - -This takes in the 10-bit input from the 10 switches, which are assigned to by the text file, and set the output to be the hex display. We then checked the syntax again and ran the analysis and elaboration on the project to see if there are any errors. - -When programming the FPGA we tested it by setting known binary values into the switches and checked if the displays showed the correct values. - - -## Experiment 4: Displaying 10-bit binary as BCD digits on the 7-Segment Displays - - -```verilog -module bin2bcd_10 (B, BCD_0, BCD_1, BCD_2, BCD_3); - - input [9:0] B; - output [3:0] BCD_0, BCD_1, BCD_2, BCD_3; - - wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12; - wire [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12; - - add3_ge5 A1 (w1,a1); - add3_ge5 A2 (w2,a2); - add3_ge5 A3 (w3,a3); - add3_ge5 A4 (w4,a4); - add3_ge5 A5 (w5,a5); - add3_ge5 A6 (w6,a6); - add3_ge5 A7 (w7,a7); - add3_ge5 A8 (w8,a8); - add3_ge5 A9 (w9,a9); - add3_ge5 A10 (w10,a10); - add3_ge5 A11 (w11,a11); - add3_ge5 A12 (w12,a12); - - assign w1 = {1'b0, B[9:7]}; - assign w2 = {a1[2:0], B[6]}; - assign w3 = {a2[2:0], B[5]}; - assign w4 = {1'b0, a1[3], a2[3], a3[3]}; - assign w5 = {a3[2:0], B[4]}; - assign w6 = {a4[2:0], a5[3]}; - assign w7 = {a5[2:0], B[3]}; - assign w8 = {a6[2:0], a7[3]}; - assign w9 = {a7[2:0], B[2]}; - assign w10 = {1'b0, a4[3], a6[3], a8[3]}; - assign w11 = {a8[2:0], a9[3]}; - assign w12 = {a9[2:0], B[1]}; - - assign BCD_0 = {a12[2:0],B[0]}; - assign BCD_1 = {a11[2:0],a12[3]}; - assign BCD_2 = {a10[2:0],a11[3]}; - assign BCD_3 = {3'b000,a10[3]}; -endmodule -``` - -```verilog -module add3_ge5(w,a); - output [3:0] a; - input [3:0] w; - - reg [3:0] a; - - always @ (w) - case(w) - 4'b0000: a <= 4'b0000; - 4'b0001: a <= 4'b0001; - 4'b0010: a <= 4'b0010; - 4'b0011: a <= 4'b0011; - 4'b0100: a <= 4'b0100; - 4'b0101: a <= 4'b1000; - 4'b0110: a <= 4'b1001; - 4'b0111: a <= 4'b1010; - 4'b1000: a <= 4'b1011; - 4'b1001: a <= 4'b1100; - 4'b1010: a <= 4'b1101; - 4'b1011: a <= 4'b1110; - 4'b1100: a <= 4'b1111; - - default: a <= 4'b0000; - endcase -endmodule -``` - -```verilog - -module ex4(SW, HEX0, HEX1, HEX2, HEX3); - - input [9:0] SW; - output [6:0] HEX0, HEX1, HEX2, HEX3; - - wire [3:0] w0, w1, w2, w3; - - bin2bcd_10(SW, w0, w1, w2, w3); - - hex_to_7seg(HEX0, w0); - hex_to_7seg(HEX1, w1); - hex_to_7seg(HEX2, w2); - hex_to_7seg(HEX3, w3); - - -endmodule -``` diff --git a/part_1/ex1/BDF_Files/My7seg.bdf b/part_1/ex1/BDF_Files/My7seg.bdf index d410eda..d410eda 100644..100755 --- a/part_1/ex1/BDF_Files/My7seg.bdf +++ b/part_1/ex1/BDF_Files/My7seg.bdf diff --git a/part_1/ex1/BDF_Files/ex1.bdf b/part_1/ex1/BDF_Files/ex1.bdf index 21cfdb1..21cfdb1 100644..100755 --- a/part_1/ex1/BDF_Files/ex1.bdf +++ b/part_1/ex1/BDF_Files/ex1.bdf diff --git a/part_1/ex1/Chain1.cdf b/part_1/ex1/Chain1.cdf index acb1f32..acb1f32 100644..100755 --- a/part_1/ex1/Chain1.cdf +++ b/part_1/ex1/Chain1.cdf diff --git a/part_1/ex1/Chain2.cdf b/part_1/ex1/Chain2.cdf index 590eb03..590eb03 100644..100755 --- a/part_1/ex1/Chain2.cdf +++ b/part_1/ex1/Chain2.cdf diff --git a/part_1/ex1/Symbol_Files/My7seg.bsf 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a/part_1/ex4/verilog_files/add3_ge5.v.bak b/part_1/ex4/verilog_files/add3_ge5.v.bak index e69de29..e69de29 100644..100755 --- a/part_1/ex4/verilog_files/add3_ge5.v.bak +++ b/part_1/ex4/verilog_files/add3_ge5.v.bak diff --git a/part_1/ex4/verilog_files/bin2bcd_10.v b/part_1/ex4/verilog_files/bin2bcd_10.v index c6f7b6d..c6f7b6d 100644..100755 --- a/part_1/ex4/verilog_files/bin2bcd_10.v +++ b/part_1/ex4/verilog_files/bin2bcd_10.v diff --git a/part_1/ex4/verilog_files/bin2bcd_10.v.bak b/part_1/ex4/verilog_files/bin2bcd_10.v.bak index e69de29..e69de29 100644..100755 --- a/part_1/ex4/verilog_files/bin2bcd_10.v.bak +++ b/part_1/ex4/verilog_files/bin2bcd_10.v.bak diff --git a/part_1/ex4/verilog_files/bin2bcd_16.v b/part_1/ex4/verilog_files/bin2bcd_16.v index fdfb655..fdfb655 100644..100755 --- a/part_1/ex4/verilog_files/bin2bcd_16.v +++ b/part_1/ex4/verilog_files/bin2bcd_16.v diff --git a/part_1/ex4/verilog_files/hex_to_7seg.v b/part_1/ex4/verilog_files/hex_to_7seg.v index 82aa9a5..82aa9a5 100644..100755 --- a/part_1/ex4/verilog_files/hex_to_7seg.v +++ b/part_1/ex4/verilog_files/hex_to_7seg.v diff --git a/part_1/mylib/add3_ge5.v b/part_1/mylib/add3_ge5.v new file mode 100755 index 0000000..65a561d --- /dev/null +++ b/part_1/mylib/add3_ge5.v @@ -0,0 +1,25 @@ +module add3_ge5(w,a);
+ output [3:0] a;
+ input [3:0] w;
+
+ reg [3:0] a;
+
+ always @ (w)
+ case(w)
+ 4'b0000: a <= 4'b0000;
+ 4'b0001: a <= 4'b0001;
+ 4'b0010: a <= 4'b0010;
+ 4'b0011: a <= 4'b0011;
+ 4'b0100: a <= 4'b0100;
+ 4'b0101: a <= 4'b1000;
+ 4'b0110: a <= 4'b1001;
+ 4'b0111: a <= 4'b1010;
+ 4'b1000: a <= 4'b1011;
+ 4'b1001: a <= 4'b1100;
+ 4'b1010: a <= 4'b1101;
+ 4'b1011: a <= 4'b1110;
+ 4'b1100: a <= 4'b1111;
+
+ default: a <= 4'b0000;
+ endcase
+endmodule
diff --git a/part_1/mylib/bin2bcd_10.v b/part_1/mylib/bin2bcd_10.v new file mode 100755 index 0000000..c6f7b6d --- /dev/null +++ b/part_1/mylib/bin2bcd_10.v @@ -0,0 +1,46 @@ +module bin2bcd_10 (B, BCD_0, BCD_1, BCD_2, BCD_3);
+
+ input [9:0] B; // binary input number
+ output [3:0] BCD_0, BCD_1, BCD_2, BCD_3; // BCD digit LSD to MSD
+
+ wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
+ wire [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12;
+
+ // Instantiate a tree of add3-if-greater than or equal to 5 cells
+ // ... input is w_n, and output is a_n
+ add3_ge5 A1 (w1,a1);
+ add3_ge5 A2 (w2,a2);
+ add3_ge5 A3 (w3,a3);
+ add3_ge5 A4 (w4,a4);
+ add3_ge5 A5 (w5,a5);
+ add3_ge5 A6 (w6,a6);
+ add3_ge5 A7 (w7,a7);
+ add3_ge5 A8 (w8,a8);
+ add3_ge5 A9 (w9,a9);
+ add3_ge5 A10 (w10,a10);
+ add3_ge5 A11 (w11,a11);
+ add3_ge5 A12 (w12,a12);
+
+ // wire the tree of add3 modules together
+ assign w1 = {1'b0, B[9:7]}; // wn is the input port to module An
+ assign w2 = {a1[2:0], B[6]};
+ assign w3 = {a2[2:0], B[5]};
+ assign w4 = {1'b0, a1[3], a2[3], a3[3]};
+ assign w5 = {a3[2:0], B[4]};
+ assign w6 = {a4[2:0], a5[3]};
+ assign w7 = {a5[2:0], B[3]};
+ assign w8 = {a6[2:0], a7[3]};
+ assign w9 = {a7[2:0], B[2]};
+ assign w10 = {1'b0, a4[3], a6[3], a8[3]};
+ assign w11 = {a8[2:0], a9[3]};
+ assign w12 = {a9[2:0], B[1]};
+
+ // connect up to four BCD digit outputs
+ assign BCD_0 = {a12[2:0],B[0]};
+ assign BCD_1 = {a11[2:0],a12[3]};
+ assign BCD_2 = {a10[2:0],a11[3]};
+ assign BCD_3 = {3'b000,a10[3]};
+endmodule
+
+
+
diff --git a/part_1/mylib/bin2bcd_16.v b/part_1/mylib/bin2bcd_16.v new file mode 100755 index 0000000..fdfb655 --- /dev/null +++ b/part_1/mylib/bin2bcd_16.v @@ -0,0 +1,97 @@ +//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+// .... it uses a shift-and-add3 algorithm
+// Creator: Peter Cheung
+// Version: 1.0
+// Date: 18 Sept 2016
+//------------------------------
+// For more explanation of how this work, see
+// ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+ input [15:0] B; // binary input number
+ output [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4; // BCD digit LSD to MSD
+
+ wire [3:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+ wire [3:0] w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+ wire [3:0] w26,w27,w28,w29;
+ wire [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+ wire [3:0] a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+ wire [3:0] a26,a27,a28,a29;
+
+ // Instantiate a tree of add3-if-greater than or equal to 5 cells
+ // ... input is w_n, and output is a_n
+ add3_ge5 A1 (w1,a1);
+ add3_ge5 A2 (w2,a2);
+ add3_ge5 A3 (w3,a3);
+ add3_ge5 A4 (w4,a4);
+ add3_ge5 A5 (w5,a5);
+ add3_ge5 A6 (w6,a6);
+ add3_ge5 A7 (w7,a7);
+ add3_ge5 A8 (w8,a8);
+ add3_ge5 A9 (w9,a9);
+ add3_ge5 A10 (w10,a10);
+ add3_ge5 A11 (w11,a11);
+ add3_ge5 A12 (w12,a12);
+ add3_ge5 A13 (w13,a13);
+ add3_ge5 A14 (w14,a14);
+ add3_ge5 A15 (w15,a15);
+ add3_ge5 A16 (w16,a16);
+ add3_ge5 A17 (w17,a17);
+ add3_ge5 A18 (w18,a18);
+ add3_ge5 A19 (w19,a19);
+ add3_ge5 A20 (w20,a20);
+ add3_ge5 A21 (w21,a21);
+ add3_ge5 A22 (w22,a22);
+ add3_ge5 A23 (w23,a23);
+ add3_ge5 A24 (w24,a24);
+ add3_ge5 A25 (w25,a25);
+ add3_ge5 A26 (w26,a26);
+ add3_ge5 A27 (w27,a27);
+ add3_ge5 A28 (w28,a28);
+ add3_ge5 A29 (w29,a29);
+
+ // wire the tree of add3 modules together
+ assign w1 = {B[14:11]}; // wn is the input port to module An
+ assign w2 = {a1[2:0], B[10]};
+ assign w3 = {1'b0, B[15], a1[3], a2[3]};
+ assign w4 = {a2[2:0], B[9]};
+ assign w5 = {a3[2:0], a4[3]};
+ assign w6 = {a4[2:0], B[8]};
+ assign w7 = {a5[2:0], a6[3]};
+ assign w8 = {a6[2:0], B[7]};
+ assign w9 = {1'b0, a3[3], a5[3], a7[3]};
+ assign w10 = {a7[2:0], a8[3]};
+ assign w11 = {a8[2:0], B[6]};
+ assign w12 = {a9[2:0], a10[3]};
+ assign w13 = {a10[2:0], a11[3]};
+ assign w14 = {a11[2:0], B[5]};
+ assign w15 = {a12[2:0], a13[3]};
+ assign w16 = {a13[2:0], a14[3]};
+ assign w17 = {a14[2:0], B[4]};
+ assign w18 = {1'b0, a9[3], a12[3], a15[3]};
+ assign w19 = {a15[2:0], a16[3]};
+ assign w20 = {a16[2:0], a17[3]};
+ assign w21 = {a17[2:0], B[3]};
+ assign w22 = {a18[2:0], a19[3]};
+ assign w23 = {a19[2:0], a20[3]};
+ assign w24 = {a20[2:0], a21[3]};
+ assign w25 = {a21[2:0], B[2]};
+ assign w26 = {a22[2:0], a23[3]};
+ assign w27 = {a23[2:0], a24[3]};
+ assign w28 = {a24[2:0], a25[3]};
+ assign w29 = {a25[2:0], B[1]};
+
+ // connect up to four BCD digit outputs
+ assign BCD_0 = {a29[2:0],B[0]};
+ assign BCD_1 = {a28[2:0],a29[3]};
+ assign BCD_2 = {a27[2:0],a28[3]};
+ assign BCD_3 = {a26[2:0],a27[3]};
+ assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};
+endmodule
+
+
+
+
diff --git a/part_1/mylib/hex_to_7seg.v b/part_1/mylib/hex_to_7seg.v new file mode 100755 index 0000000..82aa9a5 --- /dev/null +++ b/part_1/mylib/hex_to_7seg.v @@ -0,0 +1,27 @@ +module hex_to_7seg (out, in);
+
+ output [6:0] out;
+ input [3:0] in;
+
+ reg [6:0] out;
+
+ always @ (*)
+ case(in)
+ 4'h0: out = 7'b1000000;
+ 4'h1: out = 7'b1111001;
+ 4'h2: out = 7'b0100100;
+ 4'h3: out = 7'b0110000;
+ 4'h4: out = 7'b0011001;
+ 4'h5: out = 7'b0010010;
+ 4'h6: out = 7'b0000010;
+ 4'h7: out = 7'b1111000;
+ 4'h8: out = 7'b0000000;
+ 4'h9: out = 7'b0011000;
+ 4'ha: out = 7'b0001000;
+ 4'hb: out = 7'b0000011;
+ 4'hc: out = 7'b1000110;
+ 4'hd: out = 7'b0100001;
+ 4'he: out = 7'b0000110;
+ 4'hf: out = 7'b0001110;
+ endcase
+endmodule
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