| Commit message (Collapse) | Author | Age | Files | Lines |
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Fix #151 (missing irqs)
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when another interrupt activates shortly before
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fix readme icebreaker links
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Workarround: Disable cmd_memtest() when starting firmware.
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It destroys bss and data section memory.
You are not able to use static or global vars.
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added default clk divider parameter to simpleuart
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added CROSS prefix and CFLAGS to the picsoc/Makefile
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so one can run it with other toolchains, e.g.
CROSS=riscv64-t2-linux-gnu- CFLAGS=-mabi=ilp32, too
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Short modification in the error string
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Add tracing support to dhrystone test
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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README.md: Also refer to picorv32_wb
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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fix typo in picosoc/Makefile for hx8k board
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Use SPRAM on ICE40UP5K based boards
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Various touchups to scripts/icestorm demo
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With arachne-pnr this circuit couldn't hit 60MHz, just barely under it.
OTOH, nextpnr hits about ~68 MHz. So let's set it somewhere inbetween to
make sure this is true over time!
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Notes about how to build proper simulation vs hardware bitstreams.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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This freestanding firmware doesn't need anything from the supporting
toolchain.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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This makes it easier to build separate bitstreams for simulation targets
vs the real bitstream for hardware, without editing any source code.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Signed-off-by: Austin Seipp <aseipp@pobox.com>
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This dumps a simple IceTime report for the bitstream; we fix the device
package to CT256, corresponding to the HX8K.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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The IceStorm example core doesn't include compressed instructions or the
MULT extension; it is an rv32i core, not rv32i[m|c]. If the given
riscv32 toolchain is not explicitly told to generate rv32i code for the
firmware, it may generate invalid instructions which cause a trap during
simulation or on the hardware itself (although CATCH_ILLINSN is set to
zero in this case, too).
Luckily, any rv32i* toolchain (rv32imc for example) can fit the bill
here -- there's no use of libgcc or anything (which might introduce
illegal instructions generated previously) so just forcing the compiler
to generate the right code works nicely.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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