picorv32 - Fork of https://github.com/YosysHQ/picorv32.

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed catching jumps to misaligned insn	Clifford Wolf	2016-11-29	1	-7/+9
*	Renamed rvfi_opcode to rvfi_insn	Clifford Wolf	2016-11-28	1	-2/+2
*	More RVFI bugfixes	Clifford Wolf	2016-11-27	1	-7/+18
*	Minor RVFI bugfix	Clifford Wolf	2016-11-24	1	-1/+1
*	Added RISC-V Formal Interfcae (RVFI)	Clifford Wolf	2016-11-23	1	-0/+74
*	Another bugfix regarding compressed ISA and unaligned insns	Clifford Wolf	2016-11-18	1	-2/+2
*	Fixed the nontrivial compressed ISA bug found by tracecmp2	Clifford Wolf	2016-09-16	1	-3/+15
*	More fixes related to assertpmux checks	Clifford Wolf	2016-09-13	1	-2/+9
*	Added more asserts for the memory interface	Clifford Wolf	2016-09-13	1	-2/+35
*	Merge pull request #21 from wallclimber21/mem_wdata	Clifford Wolf	2016-09-08	1	-1/+3
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\| *	Fix tabs	Tom Verbeure	2016-09-07	1	-2/+2
\| *	Only clock mem_wdata when necessary	Tom Verbeure	2016-09-07	1	-1/+3
* \|	Using assertpmux in "make check"	Clifford Wolf	2016-09-07	1	-1/+27
* \|	Two minor bugfixes	Clifford Wolf	2016-09-06	1	-2/+2
* \|	Added misisng MUL_CLKGATE stage	Clifford Wolf	2016-09-06	1	-4/+3
* \|	Added picorv32_pcpi_fast_mul MUL_CLKGATE	Clifford Wolf	2016-09-05	1	-4/+9
* \|	More picorv32_pcpi_mul timing improvements	Clifford Wolf	2016-09-04	1	-7/+12
* \|	Added optional FFs to picorv32_pcpi_fast_mul	Clifford Wolf	2016-09-04	1	-16/+24
* \|	Minor bugfix/cleanup (mostly for formal verification)	Clifford Wolf	2016-09-03	1	-1/+1
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*	Moved cpuregs read/write to extra always blocks	Clifford Wolf	2016-08-31	1	-45/+79
*	Be more explicit about single register file write port	Clifford Wolf	2016-08-31	1	-4/+16
*	Bugfix in picorv32_pcpi_fast_mul	Clifford Wolf	2016-08-30	1	-1/+1
*	Merge branch 'fast_mul_opt' of https://github.com/wallclimber21/picorv32	Clifford Wolf	2016-08-30	1	-1/+2
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\| *	Reduce rs1, rs2 from 64 to 33 bits to make life for synthesis tools easier.	Tom Verbeure	2016-08-29	1	-1/+2
* \|	Minor fixes/cleanups in mul reset logic	Clifford Wolf	2016-08-30	1	-1/+6
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*	Added picorv32_pcpi_fast_mul core	Clifford Wolf	2016-08-29	1	-5/+87
*	More asserts	Clifford Wolf	2016-08-29	1	-0/+9
*	Added more asserts to picorv32, more smtbmc examples	Clifford Wolf	2016-08-29	1	-47/+74
*	Some minor cleanups	Clifford Wolf	2016-08-26	1	-12/+10
*	Added next gen yosys-smtbmc verification scripts	Clifford Wolf	2016-08-26	1	-2/+5
*	Finalized tracer support	Clifford Wolf	2016-08-26	1	-3/+3
*	Added tracer support (under construction)	Clifford Wolf	2016-08-25	1	-3/+47
*	Added REGS_INIT_ZERO parameter	Clifford Wolf	2016-08-24	1	-0/+11
*	Fixed use-before-declaration problem with VCS	Clifford Wolf	2016-06-09	1	-2/+5
*	Added STACKADDR parameter	Clifford Wolf	2016-06-07	1	-1/+7
*	RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"	Clifford Wolf	2016-06-06	1	-15/+15
*	Encode in q0 LSB if interrupted instruction is compressed	Clifford Wolf	2016-06-01	1	-3/+7
*	Do not wait for PCPI core when handling SCALL and SBREAK	Clifford Wolf	2016-06-01	1	-6/+6
*	Deassert pcpi_valid upon asserting sbreak IRQ	Steve Kerrison	2016-05-31	1	-0/+2
*	Update dbg_ signals synchronous to the actual launch of the new insn	Clifford Wolf	2016-04-14	1	-32/+73
*	Fixed dbg_ signals: no latches (formal verification doesn't like latches)	Clifford Wolf	2016-04-13	1	-0/+21
*	Minor change in DEBUGASM output	Clifford Wolf	2016-04-13	1	-1/+1
*	Added SBREAK handling for CATCH_ILLINSN=0	Clifford Wolf	2016-04-13	1	-1/+7
*	Streamlined debug signals	Clifford Wolf	2016-04-13	1	-56/+87
*	Some area improvements	Clifford Wolf	2016-04-13	1	-5/+6
*	Use ifdef instead of generate if so we don't confuse Vivado	Clifford Wolf	2016-04-13	1	-34/+35
*	Added (by default disabled) register file access wires for debugging	Clifford Wolf	2016-04-12	1	-0/+34
*	Bugfix for CATCH_ILLINSN <-> WITH_PCPI interaction	Clifford Wolf	2016-04-12	1	-1/+1
*	Added ENABLE_COUNTERS64 config parameter	Clifford Wolf	2016-04-12	1	-6/+13
*	Added BARREL_SHIFTER config parameter	Clifford Wolf	2016-04-12	1	-7/+19