picorv32 - Fork of https://github.com/YosysHQ/picorv32.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Merged axi4_memory.v and picorv32_wrapper.v back into testbench.v	Clifford Wolf	2016-03-02	1	-1/+307
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*	Split out verilator-incompatible code to top-level testbench	Olof Kindgren	2016-02-18	1	-99/+7
\| \| \| \| \| \| \|	Verilator doesn't handle verilog code that deals with time, such as delayed signals or the repeat task. Clock and reset generation are therefore moved to a separate file that can be replaced by a verilator module. VCD generation is also affected by this.
*	Break out AXI4 memory to a separate module	Olof Kindgren	2016-02-18	1	-162/+40
\| \| \| \| \|	This commit also adds support for setting the AXI_TEST and VERBOSE defines as plusargs or parameters
*	Merged various testbench changes from compressed ISA branch	Clifford Wolf	2016-02-03	1	-1/+0
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*	Removed trailing whitespaces	Clifford Wolf	2015-07-02	1	-1/+1
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*	Some testbench-related improvements	Clifford Wolf	2015-07-02	1	-2/+4
\| \| \| \|	Patch by Larry Doolittle
*	Improvements in picorv32_pcpi_mul	Clifford Wolf	2015-06-28	1	-1/+3
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*	More README stuff	Clifford Wolf	2015-06-28	1	-0/+7
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*	Added "make test_sp"	Clifford Wolf	2015-06-26	1	-0/+3
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*	Added Pico Co-Processor Interface (PCPI)	Clifford Wolf	2015-06-26	1	-0/+1
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*	Refactoring of IRQ handling	Clifford Wolf	2015-06-26	1	-6/+10
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*	Added basic IRQ support	Clifford Wolf	2015-06-25	1	-1/+7
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*	Improved AXI tests	Clifford Wolf	2015-06-06	1	-73/+83
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*	Improved AXI Interface Testbench	Clifford Wolf	2015-06-06	1	-33/+108
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*	Initial import	Clifford Wolf	2015-06-06	1	-0/+148