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* Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal)Clifford Wolf2017-05-181-2/+2
* Fix decoding of C.ADDI instructionClifford Wolf2017-05-131-5/+3
* Add riscv-formal alu/regs blackboxingClifford Wolf2017-05-111-0/+14
* Fix decoding of illegal/reserved opcodes as other valid opcodesClifford Wolf2017-05-071-21/+29
* testbench_wb.v: unify verbose output with axi testbenchAntony Pavlov2017-04-061-2/+3
* Fix indenting in wishbone codeClifford Wolf2017-03-141-53/+46
* WIP: add WISHBONE interconnect supportAntony Pavlov2017-03-141-0/+202
* Fix in rvfi_mem_ handling (when compressed isa is enabled)Clifford Wolf2017-02-271-13/+12
* Add DEBUGNETS debug flagClifford Wolf2017-02-261-1/+6
* Fix verilog code for modelsimClifford Wolf2017-02-171-1/+7
* Fix "mem_xfer is used before its declaration" warningClifford Wolf2017-02-111-1/+2
* Rename RVFI portsClifford Wolf2017-01-271-22/+22
* Fix picorv32_axi STACKADDR default valueClifford Wolf2017-01-151-1/+1
* Add STACKADDR parameter to picorv32_axi moduleOguz Meteer2017-01-151-2/+4
* Added rvfi_mem interfaceClifford Wolf2016-12-201-4/+28
* Fixed some linter warnings in picorv32.vClifford Wolf2016-12-151-14/+14
* Added rvfi_post_trapClifford Wolf2016-12-131-1/+3
* Fixed catching jumps to misaligned insnClifford Wolf2016-11-291-7/+9
* Renamed rvfi_opcode to rvfi_insnClifford Wolf2016-11-281-2/+2
* More RVFI bugfixesClifford Wolf2016-11-271-7/+18
* Minor RVFI bugfixClifford Wolf2016-11-241-1/+1
* Added RISC-V Formal Interfcae (RVFI)Clifford Wolf2016-11-231-0/+74
* Another bugfix regarding compressed ISA and unaligned insnsClifford Wolf2016-11-181-2/+2
* Fixed the nontrivial compressed ISA bug found by tracecmp2Clifford Wolf2016-09-161-3/+15
* More fixes related to assertpmux checksClifford Wolf2016-09-131-2/+9
* Added more asserts for the memory interfaceClifford Wolf2016-09-131-2/+35
* Merge pull request #21 from wallclimber21/mem_wdataClifford Wolf2016-09-081-1/+3
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| * Fix tabsTom Verbeure2016-09-071-2/+2
| * Only clock mem_wdata when necessaryTom Verbeure2016-09-071-1/+3
* | Using assertpmux in "make check"Clifford Wolf2016-09-071-1/+27
* | Two minor bugfixesClifford Wolf2016-09-061-2/+2
* | Added misisng MUL_CLKGATE stageClifford Wolf2016-09-061-4/+3
* | Added picorv32_pcpi_fast_mul MUL_CLKGATEClifford Wolf2016-09-051-4/+9
* | More picorv32_pcpi_mul timing improvementsClifford Wolf2016-09-041-7/+12
* | Added optional FFs to picorv32_pcpi_fast_mulClifford Wolf2016-09-041-16/+24
* | Minor bugfix/cleanup (mostly for formal verification)Clifford Wolf2016-09-031-1/+1
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* Moved cpuregs read/write to extra always blocksClifford Wolf2016-08-311-45/+79
* Be more explicit about single register file write portClifford Wolf2016-08-311-4/+16
* Bugfix in picorv32_pcpi_fast_mulClifford Wolf2016-08-301-1/+1
* Merge branch 'fast_mul_opt' of https://github.com/wallclimber21/picorv32Clifford Wolf2016-08-301-1/+2
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| * Reduce rs1, rs2 from 64 to 33 bits to make life for synthesis tools easier.Tom Verbeure2016-08-291-1/+2
* | Minor fixes/cleanups in mul reset logicClifford Wolf2016-08-301-1/+6
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* Added picorv32_pcpi_fast_mul coreClifford Wolf2016-08-291-5/+87
* More assertsClifford Wolf2016-08-291-0/+9
* Added more asserts to picorv32, more smtbmc examplesClifford Wolf2016-08-291-47/+74
* Some minor cleanupsClifford Wolf2016-08-261-12/+10
* Added next gen yosys-smtbmc verification scriptsClifford Wolf2016-08-261-2/+5
* Finalized tracer supportClifford Wolf2016-08-261-3/+3
* Added tracer support (under construction)Clifford Wolf2016-08-251-3/+47
* Added REGS_INIT_ZERO parameterClifford Wolf2016-08-241-0/+11